diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 1ffc1b32d..259cc7417 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -1911,6 +1911,8 @@ private: // assignment. For speed, we only look 3 deep, then give up. if (!varNotReferenced(nodep->rhsp(), varref1p->varp())) return false; if (!varNotReferenced(nextp->rhsp(), varref2p->varp())) return false; + // If a variable is marked split_var, access to the variable should not be merged. + if (varref1p->varp()->attrSplitVar() || varref2p->varp()->attrSplitVar()) return false; // Swap? if ((con1p->toSInt() != con2p->toSInt() + sel2p->width()) && (con2p->toSInt() != con1p->toSInt() + sel1p->width())) { diff --git a/test_regress/t/t_split_var_0.pl b/test_regress/t/t_split_var_0.pl index f04359527..5f07afe64 100755 --- a/test_regress/t/t_split_var_0.pl +++ b/test_regress/t/t_split_var_0.pl @@ -22,7 +22,7 @@ execute( check_finished => 1, ); -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 11); +file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 13); file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 27); ok(1); 1; diff --git a/test_regress/t/t_split_var_2_trace.pl b/test_regress/t/t_split_var_2_trace.pl index 76513de86..c79ed778a 100755 --- a/test_regress/t/t_split_var_2_trace.pl +++ b/test_regress/t/t_split_var_2_trace.pl @@ -24,7 +24,7 @@ execute( ); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 10); +file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 12); file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 27); ok(1); diff --git a/test_regress/t/t_split_var_4.pl b/test_regress/t/t_split_var_4.pl new file mode 100755 index 000000000..9030a83e0 --- /dev/null +++ b/test_regress/t/t_split_var_4.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['--stats', '-DENABLE_SPLIT_VAR=1'], + ); + +execute( + check_finished => 1, + ); + +file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 1); +file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 0); +ok(1); +1; diff --git a/test_regress/t/t_split_var_4.v b/test_regress/t/t_split_var_4.v new file mode 100644 index 000000000..f8557f479 --- /dev/null +++ b/test_regress/t/t_split_var_4.v @@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 Yutetsu TAKATSUKASA. +// SPDX-License-Identifier: CC0-1.0 + +`ifdef ENABLE_SPLIT_VAR +`define SPLIT_VAR_COMMENT /* verilator split_var */ +`else +`define SPLIT_VAR_COMMENT +/* verilator lint_off UNOPTFLAT */ +`endif + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + wire o0; + + wire [15:0] vec_i = crc[15:0]; + wire [31:0] i = crc[31:0]; + + Test test(/*AUTOINST*/ + // Outputs + .o0 (o0), + // Inputs + .clk (clk), + .i (i[1:0])); + + // Aggregate outputs into a single result vector + // verilator lint_off WIDTH + wire [63:0] result = {o0}; + // verilator lint_on WIDTH + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); + $display("o %b", o0); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hb58b16c592557b30 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(/*AUTOARG*/ + // Outputs + o0, + // Inputs + clk, i + ); + + input wire clk; + input wire [1:0] i; + output reg o0; + + typedef struct packed { + logic v0, v1; + } packed_type0; + packed_type0 value0 `SPLIT_VAR_COMMENT; + wire value0_v0; + + assign value0.v0 = i[0]; + assign value0.v1 = i[1] & !value0_v0; + assign value0_v0 = value0.v0; + + always_ff @(posedge clk) begin + o0 <= |value0; + end +endmodule + + +`ifdef ENABLE_SPLIT_VAR +/* verilator lint_on UNOPTFLAT */ +`endif diff --git a/test_regress/t/t_split_var_5.pl b/test_regress/t/t_split_var_5.pl new file mode 100755 index 000000000..0fc4cc23a --- /dev/null +++ b/test_regress/t/t_split_var_5.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); +top_filename("t/t_split_var_4.v"); + +compile( + verilator_flags2 => ['--stats'] + ); + +execute( + check_finished => 1, + ); + +file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 0); +file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 0); +ok(1); +1; +