From f3a86bacdd501e2acf139b9d406c0fec3a6e0acc Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 19 May 2026 21:40:08 -0400 Subject: [PATCH] Commentary: Changes update --- Changes | 14 ++++- test_regress/t/t_array_pattern_concat.v | 4 +- test_regress/t/t_assert_consec_rep_large.v | 3 +- .../t_assert_consec_rep_unroll_limit_bad.out | 4 +- .../t/t_assert_consec_rep_unroll_limit_bad.v | 4 +- test_regress/t/t_class_param_module_typedef.v | 14 +++-- test_regress/t/t_class_param_nested_typedef.v | 30 +++++++---- test_regress/t/t_clocking_sampled_unpacked.v | 2 +- test_regress/t/t_iface_name_collision.v | 20 +++---- test_regress/t/t_param_order.v | 52 +++++++++---------- test_regress/t/t_property_accept_reject_on.v | 18 +++---- test_regress/t/t_semaphore_fifo_block.v | 14 +++-- 12 files changed, 110 insertions(+), 69 deletions(-) diff --git a/Changes b/Changes index 0fb419f78..6931d3765 100644 --- a/Changes +++ b/Changes @@ -30,7 +30,9 @@ Verilator 5.049 devel * Support followed-by operators `#-#` and `#=#` in properties (#7523). [Yilou Wang] * Support expression coverage on assign statements (#7542) (#7543). [Thomas Brown] * Support TERMUX (#7559). [Laurent CHARRIER] +* Support NBAs in initial blocks with delay/event controls (#7566) (#7600). [Muzaffer Kal] * Support SVA goto repetition with range `[->M:N]` (#7569). [Yilou Wang] +* Support property abort operators (accept_on, reject_on) (#7578). [Yilou Wang] * Support procedural concurrent assertions with inferred clock (#7581). [Yilou Wang] * Support calling interface functions without parens (#7584). [Krzysztof Bieganski, Antmicro Ltd.] * Add peak memory usage to `--stats`. [Geza Lore, Testorrent USA, Inc.] @@ -40,10 +42,12 @@ Verilator 5.049 devel * Change JSON to include parameter constant mnemonics for FSM Coverage (#7531). [Yogish Sekhar] * Optimize emitting to_string() for compiler speedup (#7468). [Jakub Michalski, Antmicro Ltd.] * Optimize additional DFG peephole cases (#7553). [Varun Koyyalagunta, Testorrent USA, Inc.] -* Optimize forced signal handling (#7554 partial) (#7572) (#7504_. [Krzysztof Bieganski, Artur Bieniek, Antmicro Ltd.] +* Optimize forced signal handling (#7554 partial) (#7572) (#7594) (#7596). [Krzysztof Bieganski, Artur Bieniek, Antmicro Ltd.] * Fix inlining static initializer in V3Gate (#5381) (#7503). [Andrew Nolte] [Geza Lore, Testorrent USA, Inc.] * Fix segmentation fault when using --trace with --lib-create (#7299) (#7518). [anonkey] * Fix destructive event state before dynamic waits (#7340). [Nick Brereton] +* Fix array pattern concatenation (#7401) (#7402). [Greg Davill] +* Fix fairness in `std::semaphore` (#7435) (#7605). [Krzysztof Bieganski, Antmicro Ltd.] * Fix generic interface port forwarded to a nested instance (#7454) (#7457). [Yilou Wang] * Fix internal error on multi-cycle SVA under default clocking (#7472) (#7506). [Yilou Wang] * Fix internal error instead of missing prototype error (#7485). [Alex Solomatnikov] @@ -56,15 +60,23 @@ Verilator 5.049 devel * Fix $bits on local struct with chained-interface (#7515) (#7517). * Fix array indexing side effects in compound assignments (#7519) (#7540) (#7544). [Kamil Danecki, Antmicro Ltd.] * Fix class::localparam during elaboration (#7524) (#7534). +* Fix nested parameterized class typedef chain (#7538). [Michael Rogenmoser] * Fix events in observed region (#7546). [Todd Strader] * Fix regression rejecting boolean `!x` inside sequence expressions (#7549) (#7551). [Yilou Wang] * Fix exponential expansion in V3Gate (#7550). [Geza Lore, Testorrent USA, Inc.] +* Fix internal error on consecutive repetition with N > 256 (#7552) (#7603). [Yilou Wang] * Fix display of %m in non-first argument (#7574). * Fix floating point compile warning on min/max delays. * Fix force of unpacked arrays (#7579) (#7580). [Zubin Jain] * Fix property argument retaining type of the previous variable (#7582). [Jakub Michalski] * Fix NBA to whole arrays (#7583) (#7575). [Geza Lore, Testorrent USA, Inc.] +* Fix interface instance name collision (#7591) (#7593). [Stuart Morris] * Fix process comparison compile error with `--public-flat-rw` (#7592). +* Fix CPU pinning when no 'core id' present (#7599). [Geza Lore, Testorrent USA, Inc.] +* Fix clocking-block sample of unpacked array (#7612) (#7613). [Nikolai Kumar] +* Fix type parameters order (#7615). [Kamil Danecki, Antmicro Ltd.] +* Fix unique_index method on assoc arrays with values differing from the keys (#7616). [Pawel Klopotek] +* Fix wide equality comparison in unpacked structs (#7618). [Geza Lore, Testorrent USA, Inc.] Verilator 5.048 2026-04-26 diff --git a/test_regress/t/t_array_pattern_concat.v b/test_regress/t/t_array_pattern_concat.v index 2c7f4900f..92db4365d 100644 --- a/test_regress/t/t_array_pattern_concat.v +++ b/test_regress/t/t_array_pattern_concat.v @@ -66,7 +66,9 @@ module t ( /*AUTOARG*/); // Keyed pattern where values are indexed from another array param // the key determines position, not the source array's element count. localparam logic [31:0] KEYED_FROM_ARR[3] = '{ - 0: BASE_ADDRS[2], 1: BASE_ADDRS[0], 2: BASE_ADDRS[1] + 0: BASE_ADDRS[2], + 1: BASE_ADDRS[0], + 2: BASE_ADDRS[1] }; // Package-scoped array as a positional pattern member diff --git a/test_regress/t/t_assert_consec_rep_large.v b/test_regress/t/t_assert_consec_rep_large.v index 4a0e332fc..359537ce7 100644 --- a/test_regress/t/t_assert_consec_rep_large.v +++ b/test_regress/t/t_assert_consec_rep_large.v @@ -36,7 +36,8 @@ module t ( crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc == 0) begin crc <= 64'h5aef0c8d_d70a4497; - end else if (cyc == 99) begin + end + else if (cyc == 99) begin `checkh(crc, 64'hc77bb9b3784ea091); `checkd(count_fail_257, 0); // Questa: 31 -- pre-existing ~26.5% NFA reject gap on |-> ##1 [*N] diff --git a/test_regress/t/t_assert_consec_rep_unroll_limit_bad.out b/test_regress/t/t_assert_consec_rep_unroll_limit_bad.out index 3ac575c90..e7be548e7 100644 --- a/test_regress/t/t_assert_consec_rep_unroll_limit_bad.out +++ b/test_regress/t/t_assert_consec_rep_unroll_limit_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_assert_consec_rep_unroll_limit_bad.v:12:37: Concurrent assertion repetition count 25700000 exceeds --assert-unroll-limit (1024); raise '--assert-unroll-limit' to compile +%Error: t/t_assert_consec_rep_unroll_limit_bad.v:14:37: Concurrent assertion repetition count 25700000 exceeds --assert-unroll-limit (1024); raise '--assert-unroll-limit' to compile : ... note: In instance 't' - 12 | assert property (@(posedge clk) a [* 25700000] |-> b); + 14 | assert property (@(posedge clk) a [* 25700000] |-> b); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_assert_consec_rep_unroll_limit_bad.v b/test_regress/t/t_assert_consec_rep_unroll_limit_bad.v index 061e8b1ce..f99fc2814 100644 --- a/test_regress/t/t_assert_consec_rep_unroll_limit_bad.v +++ b/test_regress/t/t_assert_consec_rep_unroll_limit_bad.v @@ -4,7 +4,9 @@ // SPDX-FileCopyrightText: 2026 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 -module t (input clk); +module t ( + input clk +); logic a, b; // Repetition count exceeds --assert-unroll-limit; pre-fix this hung the diff --git a/test_regress/t/t_class_param_module_typedef.v b/test_regress/t/t_class_param_module_typedef.v index e4632d09a..372cf55c7 100644 --- a/test_regress/t/t_class_param_module_typedef.v +++ b/test_regress/t/t_class_param_module_typedef.v @@ -18,16 +18,24 @@ // verilog_format: on package pkg; - class rand_master #(parameter int AW = 32, parameter int DW = 32); + class rand_master #( + parameter int AW = 32, + parameter int DW = 32 + ); typedef logic [AW-1:0] addr_t; endclass endpackage -module t #(parameter int unused = 1); +module t #( + parameter int unused = 1 +); // AW and DW are both overridden to non-default values so that a regression // in parameter propagation through the typedef chain shows up as a width // mismatch instead of silently succeeding. - typedef pkg::rand_master #(.AW(17), .DW(64)) rand_master_t; + typedef pkg::rand_master#( + .AW(17), + .DW(64) + ) rand_master_t; typedef rand_master_t::addr_t addr_t; initial begin static addr_t a = '0; diff --git a/test_regress/t/t_class_param_nested_typedef.v b/test_regress/t/t_class_param_nested_typedef.v index a69e7366c..cebf38cf4 100644 --- a/test_regress/t/t_class_param_nested_typedef.v +++ b/test_regress/t/t_class_param_nested_typedef.v @@ -25,12 +25,16 @@ package pkg; - class beat #(parameter int IW = 8); + class beat #( + parameter int IW = 8 + ); logic [IW-1:0] id; endclass - class driver #(parameter int IW = 8); - typedef beat #(.IW(IW)) beat_t; + class driver #( + parameter int IW = 8 + ); + typedef beat#(.IW(IW)) beat_t; // Verify the beat handed to us has the IW we were specialized for. task send(input beat_t b); `checkd($bits(b.id), IW); @@ -38,12 +42,16 @@ package pkg; endtask endclass - class master #(parameter int IW = 8); - typedef driver #(.IW(IW)) driver_t; - typedef driver_t::beat_t beat_t; + class master #( + parameter int IW = 8 + ); + typedef driver#(.IW(IW)) driver_t; + typedef driver_t::beat_t beat_t; driver_t drv; - function new(driver_t d); drv = d; endfunction + function new(driver_t d); + drv = d; + endfunction task run(); automatic beat_t b = new; @@ -64,8 +72,12 @@ module t; pkg::driver #(.IW(5)) da; pkg::driver #(.IW(6)) db; initial begin - da = new; ma = new(da); ma.run(); - db = new; mb = new(db); mb.run(); + da = new; + ma = new(da); + ma.run(); + db = new; + mb = new(db); + mb.run(); $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_clocking_sampled_unpacked.v b/test_regress/t/t_clocking_sampled_unpacked.v index 236ede51b..6459e2478 100644 --- a/test_regress/t/t_clocking_sampled_unpacked.v +++ b/test_regress/t/t_clocking_sampled_unpacked.v @@ -22,7 +22,7 @@ module t; data[1] = 2'd2; @(posedge clk); @(posedge clk); - if (snap[0] !== 2'd1 || snap[1] !==2'd2) $stop; + if (snap[0] !== 2'd1 || snap[1] !== 2'd2) $stop; $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_iface_name_collision.v b/test_regress/t/t_iface_name_collision.v index 69fac79bc..c37ef1691 100644 --- a/test_regress/t/t_iface_name_collision.v +++ b/test_regress/t/t_iface_name_collision.v @@ -16,34 +16,34 @@ interface avst_interface; logic ready; logic valid; - modport sink_mp (output ready, input valid); + modport sink_mp(output ready, input valid); endinterface module child ( - output logic ready_out + output logic ready_out ); - avst_interface my_avst_if(); + avst_interface my_avst_if (); assign ready_out = my_avst_if.ready; - assign my_avst_if.ready = 1'b1; // drives child.my_avst_if.ready only + assign my_avst_if.ready = 1'b1; // drives child.my_avst_if.ready only endmodule module wrapper ( - avst_interface.sink_mp my_avst_if + avst_interface.sink_mp my_avst_if ); child child_inst ( - .ready_out (my_avst_if.ready) // sole driver of outer my_avst_if.ready + .ready_out(my_avst_if.ready) // sole driver of outer my_avst_if.ready ); endmodule module top ( - input logic in_valid, - output logic out_ready + input logic in_valid, + output logic out_ready ); - avst_interface my_avst_if(); + avst_interface my_avst_if (); assign my_avst_if.valid = in_valid; assign out_ready = my_avst_if.ready; - wrapper wrapper_inst (.my_avst_if (my_avst_if)); + wrapper wrapper_inst (.my_avst_if(my_avst_if)); endmodule diff --git a/test_regress/t/t_param_order.v b/test_regress/t/t_param_order.v index 4fef2cb30..1a0d2ecaa 100644 --- a/test_regress/t/t_param_order.v +++ b/test_regress/t/t_param_order.v @@ -12,9 +12,9 @@ class obj; endclass class TypeParams #( - type T1 = obj, - type T2 = obj, - type T3 = obj + type T1 = obj, + type T2 = obj, + type T3 = obj ); T1 t1; T2 t2; @@ -22,48 +22,48 @@ class TypeParams #( endclass class ValueParams #( - int P1 = 1, - int P2 = 1, - int P3 = 1 + int P1 = 1, + int P2 = 1, + int P3 = 1 ); - logic[P1:0] x1; - logic[P2:0] x2; - logic[P3:0] x3; + logic [P1:0] x1; + logic [P2:0] x2; + logic [P3:0] x3; endclass class Mixed #( - type T1 = obj, - int P1 = 1, - type T2 = obj, - int P2 = 1, - type T3 = obj, - int P3 = 1 + type T1 = obj, + int P1 = 1, + type T2 = obj, + int P2 = 1, + type T3 = obj, + int P3 = 1 ); T1 t1; T2 t2; T3 t3; - logic[P1:0] x1; - logic[P2:0] x2; - logic[P3:0] x3; + logic [P1:0] x1; + logic [P2:0] x2; + logic [P3:0] x3; endclass module t; TypeParams #( - .T2 (int), - .T3 (logic) + .T2(int), + .T3(logic) ) t; obj o; ValueParams #( - .P3 (5), - .P2 (2) + .P3(5), + .P2(2) ) v; Mixed #( - .P3 (3), - .T1 (logic), - .T3 (int), - .P2 (7) + .P3(3), + .T1(logic), + .T3(int), + .P2(7) ) m; initial begin o = new; diff --git a/test_regress/t/t_property_accept_reject_on.v b/test_regress/t/t_property_accept_reject_on.v index 03c7be157..020e754f2 100644 --- a/test_regress/t/t_property_accept_reject_on.v +++ b/test_regress/t/t_property_accept_reject_on.v @@ -94,15 +94,15 @@ module t ( end else if (cyc == 99) begin `checkh(crc, 64'hc77bb9b3784ea091); - `checkd(count_fail1, 29); // Questa: 14 - `checkd(count_fail2, 65); // Questa: 64 - `checkd(count_fail3, 29); // Questa: 14 - `checkd(count_fail4, 65); // Questa: 64 - `checkd(count_fail5, 46); // Questa: 31 - `checkd(count_fail6, 65); // Questa: 59 - `checkd(count_fail7, 29); // Questa: 14 - `checkd(count_fail8, 14); // Questa: 10 - `checkd(count_fail9, 29); // Questa: 14 + `checkd(count_fail1, 29); // Questa: 14 + `checkd(count_fail2, 65); // Questa: 64 + `checkd(count_fail3, 29); // Questa: 14 + `checkd(count_fail4, 65); // Questa: 64 + `checkd(count_fail5, 46); // Questa: 31 + `checkd(count_fail6, 65); // Questa: 59 + `checkd(count_fail7, 29); // Questa: 14 + `checkd(count_fail8, 14); // Questa: 10 + `checkd(count_fail9, 29); // Questa: 14 `checkd(count_fail10, 29); // Questa: 14 $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_semaphore_fifo_block.v b/test_regress/t/t_semaphore_fifo_block.v index 44d163caf..ca812dd65 100644 --- a/test_regress/t/t_semaphore_fifo_block.v +++ b/test_regress/t/t_semaphore_fifo_block.v @@ -11,24 +11,28 @@ module t; initial begin fork begin - #1 sem.get(4); + #1; + sem.get(4); $write("[%0t] A got 4\n", $time); - #1 + #1; sem.put(3); $write("[%0t] A put 3\n", $time); end begin - #2 sem.get(3); + #2; + sem.get(3); $write("[%0t] B got 3\n", $time); end begin - #3 sem.get(1); + #3; + sem.get(1); $write("[%0t] C got 1\n", $time); sem.put(1); $write("[%0t] C put 1\n", $time); end begin - #4 sem.put(2); + #4; + sem.put(2); $write("[%0t] D put 2\n", $time); end join