diff --git a/Changes b/Changes
index bb2901461..a8d572d5a 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Fix generate operators not short circuiting, bug413.  [by Jeremy Bennett]
 
+****  Fix imports causing symbol table error, bug490.  [Alex Solomatnikov]
 
 * Verilator 3.833 2012/04/15
 
diff --git a/src/V3Link.cpp b/src/V3Link.cpp
index 86ef74e75..7894c1a7a 100644
--- a/src/V3Link.cpp
+++ b/src/V3Link.cpp
@@ -215,18 +215,17 @@ private:
     }
 
     // VISITs
-    virtual void visit(AstNetlist* nodep, AstNUser*) {
+    virtual void visit(AstNetlist* nodep, AstNUser* vup) {
 	// Top scope
 	m_curVarsp = symsFindNew(nodep, NULL);
-	// And recurse...
-	// Recurse...
+	// Recurse..., backward as must do packages before using packages
 	m_idState = ID_FIND;
-	nodep->iterateChildren(*this);
+	nodep->iterateChildrenBackwards(*this);
 	if (debug()==9) m_curVarsp->dump(cout,"-curvars: ",true/*user4p_is_table*/);
 	m_idState = ID_PARAM;
-	nodep->iterateChildren(*this);
+	nodep->iterateChildrenBackwards(*this);
 	m_idState = ID_RESOLVE;
-	nodep->iterateChildren(*this);
+	nodep->iterateChildrenBackwards(*this);
 	nodep->checkTree();
     }
 
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index d86cd579e..b87b1a17e 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -176,6 +176,13 @@ private:
 	m_modp = NULL;
     }
 
+    virtual void visit(AstPackageImport* nodep, AstNUser*) {
+	// Package Import: We need to do the package before the use of a package
+	nodep->iterateChildren(*this);
+	if (!nodep->packagep()) nodep->v3fatalSrc("Unlinked package");  // Parser should set packagep
+	new V3GraphEdge(&m_graph, vertex(m_modp), vertex(nodep->packagep()), 1, false);
+    }
+
     virtual void visit(AstCell* nodep, AstNUser*) {
 	// Cell: Resolve its filename.  If necessary, parse it.
 	if (!nodep->modp()) {
diff --git a/test_regress/t/t_package_abs.pl b/test_regress/t/t_package_abs.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_package_abs.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_package_abs.v b/test_regress/t/t_package_abs.v
new file mode 100644
index 000000000..fcb743051
--- /dev/null
+++ b/test_regress/t/t_package_abs.v
@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+// see bug491
+
+package functions;
+   function real abs (real num);
+      abs = (num <0) ? -num : num;
+   endfunction
+endpackage
+
+module t ();
+   import functions::*;
+   localparam P = 1;
+   generate
+      if (P == 1) begin
+	 initial begin
+	    if (abs(-2.1) != 2.1) $stop;
+	    if (abs(2.2) != 2.2) $stop;
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+      end
+   endgenerate
+endmodule