From f3684a85b9762151961596f85bb79bb1d256203e Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 30 Mar 2025 17:38:54 -0400
Subject: [PATCH] Fix delayed assignment malformed LHS assertion (#5904).

---
 Changes                                    |  1 +
 src/V3Delayed.cpp                          |  4 ++--
 test_regress/t/t_fork_dynscope_interface.v | 21 ++++++++++++++++-----
 3 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/Changes b/Changes
index a28d9285d..8fe7f28df 100644
--- a/Changes
+++ b/Changes
@@ -61,6 +61,7 @@ Verilator 5.035 devel
 * Fix V3Gate assertion on eliminated circular logic (#5889) (#5898). [Geza Lore]
 * Fix process comparisons (#5896).
 * Fix ccache with clang (#5899). [Geza Lore]
+* Fix delayed assignment malformed LHS assertion (#5904).
 
 
 Verilator 5.034 2025-02-24
diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp
index 709fb1fb7..82e0d5669 100644
--- a/src/V3Delayed.cpp
+++ b/src/V3Delayed.cpp
@@ -347,8 +347,8 @@ class DelayedVisitor final : public VNVisitor {
             arrSelp->bitp(captureVal(scopep, insertp, arrSelp->bitp()->unlinkFrBack(), tmpName));
             nodep = arrSelp->fromp();
         }
-        // What remains must be an AstVarRef
-        UASSERT_OBJ(VN_IS(nodep, VarRef), lhsp, "Malformed LHS in NBA");
+        // What remains must be an AstVarRef, or some sort of select, we assume can reuse it.
+        UASSERT_OBJ(nodep->isPure(), lhsp, "Malformed LHS in NBA");
         // Now have been converted to use the captured values
         return lhsp;
     }
diff --git a/test_regress/t/t_fork_dynscope_interface.v b/test_regress/t/t_fork_dynscope_interface.v
index 593a3eb6b..59132d448 100644
--- a/test_regress/t/t_fork_dynscope_interface.v
+++ b/test_regress/t/t_fork_dynscope_interface.v
@@ -6,7 +6,11 @@
 
 module t;
    Iface ifc();
+   rvlab_tests uut (.ifc);
 
+   always begin
+      uut.test_idcode();
+   end
    initial begin
       #1;
       $write("*-* All Finished *-*\n");
@@ -15,12 +19,19 @@ module t;
 endmodule
 
 interface Iface;
-  int tck;
-  int tdo;
+  logic tck;
+  logic tdo;
 
-  task tsk(input int data_i, output int data_o);
+  task tsk(output logic [31:0] data_o, input logic [31:0] data_i);
      @(posedge tck);
-     data_o <= tdo;
+     data_o[$size(data_i)-1] <= tdo;
   endtask
-
 endinterface
+
+module rvlab_tests (
+   Iface ifc);
+   task test_idcode();
+      bit [31:0] idcode_read;
+      ifc.tsk(idcode_read, '0);
+   endtask
+endmodule