From f26a7c2a5d281fa6bc7cd134c7c48d30e69c66b8 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 28 Mar 2021 20:18:18 -0400
Subject: [PATCH] Fix --comp-limit-parens with real data types

---
 src/V3Depth.cpp                            | 10 ++-------
 test_regress/t/t_flag_comp_limit_parens.pl | 24 ++++++++++++++++++++++
 test_regress/t/t_flag_comp_limit_parens.v  | 19 +++++++++++++++++
 3 files changed, 45 insertions(+), 8 deletions(-)
 create mode 100755 test_regress/t/t_flag_comp_limit_parens.pl
 create mode 100644 test_regress/t/t_flag_comp_limit_parens.v

diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp
index 4f8be0f75..5ff517a62 100644
--- a/src/V3Depth.cpp
+++ b/src/V3Depth.cpp
@@ -53,14 +53,8 @@ private:
         // if (debug() >= 9) nodep->dumpTree(cout, "deep:");
 
         string newvarname = (string("__Vdeeptemp") + cvtToStr(m_modp->varNumGetInc()));
-        AstVar* varp = new AstVar(nodep->fileline(), AstVarType::STMTTEMP, newvarname,
-                                  // Width, not widthMin, as we may be in
-                                  // middle of BITSEL expression which though
-                                  // it's one bit wide, needs the mask in the
-                                  // upper bits.  (Someday we'll have a valid
-                                  // bitmask instead of widths....)
-                                  // See t_func_crc for an example test that requires this
-                                  VFlagLogicPacked(), nodep->width());
+        AstVar* varp
+            = new AstVar(nodep->fileline(), AstVarType::STMTTEMP, newvarname, nodep->dtypep());
         UASSERT_OBJ(m_cfuncp, nodep, "Deep expression not under a function");
         m_cfuncp->addInitsp(varp);
         // Replace node tree with reference to var
diff --git a/test_regress/t/t_flag_comp_limit_parens.pl b/test_regress/t/t_flag_comp_limit_parens.pl
new file mode 100755
index 000000000..e1ffcfc7b
--- /dev/null
+++ b/test_regress/t/t_flag_comp_limit_parens.pl
@@ -0,0 +1,24 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["--comp-limit-parens 2"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+file_grep("$Self->{obj_dir}/Vt_flag_comp_limit_parens__Slow.cpp", qr/Vdeeptemp/x);
+
+ok(1);
+1;
diff --git a/test_regress/t/t_flag_comp_limit_parens.v b/test_regress/t/t_flag_comp_limit_parens.v
new file mode 100644
index 000000000..bda8c841f
--- /dev/null
+++ b/test_regress/t/t_flag_comp_limit_parens.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   r
+   );
+   input real r;
+
+   initial begin
+      $display("%g", $cos($cos($cos($cos($cos($cos($cos($cos(r + 0.1)))))))));
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule