From f25492df67642dc923e67d4e1ebd1887bb2a0eee Mon Sep 17 00:00:00 2001
From: Mateusz Gancarz <mgancarz@antmicro.com>
Date: Wed, 26 Feb 2025 12:30:06 +0100
Subject: [PATCH] [#73220] add t_trace_saif_sc_unsup test

---
 test_regress/t/t_trace_saif_sc_unsup.py | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100755 test_regress/t/t_trace_saif_sc_unsup.py

diff --git a/test_regress/t/t_trace_saif_sc_unsup.py b/test_regress/t/t_trace_saif_sc_unsup.py
new file mode 100755
index 000000000..251d73b83
--- /dev/null
+++ b/test_regress/t/t_trace_saif_sc_unsup.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=["--trace-saif --sc"])
+
+test.execute()
+
+test.passes()