From f197dd29cb9c20d8865eee3c576fb8c7d073dfc9 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 22 Sep 2008 19:36:08 -0400
Subject: [PATCH] Suppress width warnings between constant strings and wider
 vectors.

---
 Changes                           |  5 +++++
 src/V3Number.cpp                  |  2 ++
 src/V3Number.h                    |  2 ++
 src/V3Width.cpp                   |  7 +++++++
 test_regress/t/t_math_strwidth.pl | 18 ++++++++++++++++++
 test_regress/t/t_math_strwidth.v  | 19 +++++++++++++++++++
 6 files changed, 53 insertions(+)
 create mode 100755 test_regress/t/t_math_strwidth.pl
 create mode 100644 test_regress/t/t_math_strwidth.v

diff --git a/Changes b/Changes
index f64207ba9..52e5cb3c8 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,11 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.67**
+
+***  Suppress width warnings between constant strings and wider vectors.
+     [Rodney Sinclair]
+
 * Verilator 3.671 2008/09/19
 
 **   SystemC uint64_t pins are now the default instead of sc_bv<64>.
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index ce7d09ccb..ec24b2fee 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -45,6 +45,7 @@ void V3Number::init (FileLine* fileline, int swidth) {
     m_fileline = fileline;
     m_signed = false;
     m_autoExtend = false;
+    m_fromString = false;
     width(swidth);
     for (int i=0; i<words(); i++) m_value[i]=m_valueX[i] = 0;
 }
@@ -52,6 +53,7 @@ void V3Number::init (FileLine* fileline, int swidth) {
 V3Number::V3Number(VerilogString, FileLine* fileline, const string& str) {
     // Create a number using a verilog string as the value, thus 8 bits per character.
     init(fileline, str.length()*8);
+    m_fromString = true;
     for (unsigned pos=0; pos<str.length(); ++pos) {
 	int topos = str.length()-1-pos;
 	for (int bit=0; bit<8; ++bit) {
diff --git a/src/V3Number.h b/src/V3Number.h
index 8f377ab98..65323bc47 100644
--- a/src/V3Number.h
+++ b/src/V3Number.h
@@ -34,6 +34,7 @@ class V3Number {
     int		m_width;	// Width as specified/calculated.
     bool	m_sized:1;	// True if the user specified the width, else we track it.
     bool	m_signed:1;	// True if signed value
+    bool	m_fromString:1;	// True if from string
     bool	m_autoExtend:1;	// True if SystemVerilog extend-to-any-width
     FileLine*	m_fileline;
     vector<uint32_t>	m_value;	// The Value, with bit 0 being in bit 0 of this vector (unless X/Z)
@@ -124,6 +125,7 @@ public:
     int minWidth() const;	// Minimum width that can represent this number (~== log2(num)+1)
     bool sized() const { return m_sized; }
     bool autoExtend() const { return m_autoExtend; }
+    bool isFromString() const { return m_fromString; }
     bool isSigned() const { return m_signed; }	// Only correct for parsing of numbers from strings, otherwise not used (use AstConst::isSigned())
     bool isNegative() const { return bitIs1(width()-1); }
     bool isFourState() const { for (int i=0;i<words();i++) {if (m_valueX[i]) return true;} return false; }
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 0c8bfb989..011dd5ae1 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -911,6 +911,13 @@ void WidthVisitor::widthCheck (AstNode* nodep, const char* side,
     if (expWidthMin==0) expWidthMin = expWidth;
     bool bad = widthBad(underp,expWidth,expWidthMin);
     if (bad && fixAutoExtend(underp/*ref*/,expWidth)) bad=false;  // Changes underp
+    if (underp->castConst() && underp->castConst()->num().isFromString()
+	&& expWidth > underp->width()
+	&& (((expWidth - underp->width()) % 8) == 0)) {  // At least it's character sized
+	// reg [31:0] == "foo" we'll consider probably fine.
+	// Maybe this should be a special warning?  Not for now.
+	ignoreWarn = true;
+    }
     if (bad && !ignoreWarn) {
 	if (debug()>4) nodep->backp()->dumpTree(cout,"  back: ");
 	nodep->v3warn(WIDTH,"Operator "<<nodep->typeName()
diff --git a/test_regress/t/t_math_strwidth.pl b/test_regress/t/t_math_strwidth.pl
new file mode 100755
index 000000000..c32414387
--- /dev/null
+++ b/test_regress/t/t_math_strwidth.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => [],
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_math_strwidth.v b/test_regress/t/t_math_strwidth.v
new file mode 100644
index 000000000..87dc82e96
--- /dev/null
+++ b/test_regress/t/t_math_strwidth.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008-2008 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   reg [4*8:1] strg;
+
+   initial begin
+      strg = "CHK";
+      if (strg != "CHK") $stop;
+      if (strg == "JOE") $stop;
+      $write("String = %s = %x\n", strg, strg);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule