From f147b0854a212e727947b748e208913736ec172b Mon Sep 17 00:00:00 2001 From: Matthew Ballance Date: Mon, 2 Mar 2026 04:26:11 +0000 Subject: [PATCH] Fix infinite recursion in visit(AstCovergroup*) and fileline Two bugs in the covergroup -> AstClass transformation in V3LinkParse: 1. Infinite recursion: when a covergroup has a clocking event (e.g. `@(posedge clk)`), visit(AstCovergroup*) embeds a sentinel AstCovergroup node inside the new AstClass to carry the event for V3Covergroup.cpp. The subsequent iterate(cgClassp) call then visits the sentinel via visit(AstNodeModule*) -> iterateChildren -> which hits visit(AstCovergroup*) again, creating another class with another sentinel, infinitely. Fix: skip transformation in visit(AstCovergroup*) when already inside a covergroup class (m_modp->isCovergroup()), so sentinel nodes are left alone. 2. Wrong fileline column: AstCovergroup was created with the fileline of the identifier token ($2, the name position) rather than the 'covergroup' keyword token ($1). This caused warnings about the covergroup to point to the name column instead of the keyword column. Fix: use $1 (the 'covergroup' keyword fileline) when constructing AstCovergroup in the parser. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- src/V3LinkParse.cpp | 4 ++++ src/verilog.y | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 5bf8633a7..75c1e9445 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -1151,6 +1151,10 @@ class LinkParseVisitor final : public VNVisitor { } void visit(AstCovergroup* nodep) override { + // If we're already inside a covergroup class, this is the sentinel AstCovergroup + // node carrying the clocking event for V3Covergroup — don't re-transform it. + if (m_modp && VN_IS(m_modp, Class) && VN_CAST(m_modp, Class)->isCovergroup()) return; + // Transform raw parse-time AstCovergroup into a fully-formed AstClass cleanFileline(nodep); diff --git a/src/verilog.y b/src/verilog.y index 9af8218ad..c7b436625 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -6913,7 +6913,7 @@ covergroup_declaration: // ==IEEE: covergroup_declaration else sampleArgsp = $4; } - $$ = new AstCovergroup{$2, *$2, static_cast($3), + $$ = new AstCovergroup{$1, *$2, static_cast($3), static_cast(sampleArgsp), $6, clockp}; GRAMMARP->endLabel($8, $$, $8); } | yCOVERGROUP yEXTENDS idAny ';'