From f093c3d78b708817b0211a83996963ba03ef5000 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 22 Oct 2016 08:05:27 -0400
Subject: [PATCH] Fix error on bad interface name, bug1097.

---
 Changes                                |  2 ++
 src/V3LinkDot.cpp                      |  4 ++++
 test_regress/t/t_interface_typo_bad.pl | 25 ++++++++++++++++++++++
 test_regress/t/t_interface_typo_bad.v  | 29 ++++++++++++++++++++++++++
 4 files changed, 60 insertions(+)
 create mode 100755 test_regress/t/t_interface_typo_bad.pl
 create mode 100644 test_regress/t/t_interface_typo_bad.v

diff --git a/Changes b/Changes
index 495d9c102..5153176c7 100644
--- a/Changes
+++ b/Changes
@@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 3.889 devel
 
+****  Fix error on bad interface name, bug1097. [Todd Strader]
+
 
 * Verilator 3.888 2016-10-14
 
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index ded86a3f6..a7ec049c9 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -391,6 +391,9 @@ public:
 		} else {
 		    ifacerefp->v3fatalSrc("Unlinked interface");
 		}
+	    } else if (ifacerefp->ifaceViaCellp()->dead()) {
+		ifacerefp->v3error("Parent cell's interface is not found: "<<AstNode::prettyName(ifacerefp->ifaceName()));
+		continue;
 	    }
 	    VSymEnt* ifaceSymp = getNodeSym(ifacerefp->ifaceViaCellp());
 	    VSymEnt* ifOrPortSymp = ifaceSymp;
@@ -740,6 +743,7 @@ class LinkDotFindVisitor : public AstNVisitor {
 	    m_scope = m_scope+"."+nodep->name();
 	    m_curSymp = m_modSymp = m_statep->insertCell(aboveSymp, m_modSymp, nodep, m_scope);
 	    m_beginp = NULL;
+	    // We don't report NotFoundModule, as may be a unused module in a generate
 	    if (nodep->modp()) nodep->modp()->accept(*this);
 	}
 	m_scope = oldscope;
diff --git a/test_regress/t/t_interface_typo_bad.pl b/test_regress/t/t_interface_typo_bad.pl
new file mode 100755
index 000000000..7b36097c0
--- /dev/null
+++ b/test_regress/t/t_interface_typo_bad.pl
@@ -0,0 +1,25 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2005 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ["--lint-only"],
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    fails => 1,
+    # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x.
+    # However we no longer gate optimize this
+    expect=>
+q{%Error: t/t_interface_typo_bad.v:\d+: Parent cell's interface is not found: foo_intf
+%Warning-IMPLICIT: t/t_interface_typo_bad.v:\d+: Signal definition not found, creating implicitly: the_foo
+.*},
+	 );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_typo_bad.v b/test_regress/t/t_interface_typo_bad.v
new file mode 100644
index 000000000..b2b1e70da
--- /dev/null
+++ b/test_regress/t/t_interface_typo_bad.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2016 by Todd Strader.
+
+//bug1097
+
+interface foo_intf;
+endinterface
+
+module submod
+  (
+   foo_intf foo
+   );
+
+endmodule
+
+module t (/*AUTOARG*/);
+   // Intentional typo, compiler should point this out, or that fo_intf does
+   // not match foo_intf on the submod port map
+   fo_intf the_foo;
+
+   submod
+     submod_inst
+       (
+	.foo (the_foo)
+	);
+
+endmodule