diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h
index 2c3fcc50c..560191f68 100644
--- a/src/V3EmitCBase.h
+++ b/src/V3EmitCBase.h
@@ -74,8 +74,7 @@ public:
         return v3Global.opt.compLimitMembers() != 0  // Enabled
                && !varp->isStatic()  // Not a static variable
                && !varp->isSc()  // Aggregates can't be anon
-               && !VN_IS(dtp, SampleQueueDType)  // Aggregates can't be anon
-               && !(VN_IS(dtp, NodeUOrStructDType) && !VN_CAST(dtp, NodeUOrStructDType)->packed())
+               && !dtp->isCompound()  // Non-POD members are not allowed in an anonymous aggregate
                && (varp->basicp() && !varp->basicp()->isOpaque());  // Aggregates can't be anon
     }
     static bool isConstPoolMod(const AstNode* modp) {
diff --git a/test_regress/t/t_dyn_assoc_anon.py b/test_regress/t/t_dyn_assoc_anon.py
new file mode 100755
index 000000000..ac25e1bbc
--- /dev/null
+++ b/test_regress/t/t_dyn_assoc_anon.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["--comp-limit-members 1"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_dyn_assoc_anon.v b/test_regress/t/t_dyn_assoc_anon.v
new file mode 100644
index 000000000..6b0af9f8f
--- /dev/null
+++ b/test_regress/t/t_dyn_assoc_anon.v
@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+module t (
+    input clk
+);
+
+  reg [7:0] da0[*];
+  reg [7:0] da1[2][*];
+
+  integer cyc = 0;
+
+  always @(posedge clk) begin
+    cyc <= cyc + 1;
+    if (cyc == 0) begin
+      da0[1] = 8'h11;
+      da1[0][2] = 8'h22;
+      da1[1][3] = 8'h33;
+    end else if (cyc == 1) begin
+      `checkh(da0.size(), 1);
+      `checkh(da0[1], 8'h11);
+      `checkh(da1[0].size(), 1);
+      `checkh(da1[0][2], 8'h22);
+      `checkh(da1[1][3], 8'h33);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+endmodule