From ef5c31b4c9b7b211b181ce54caf9e6197e7c7fa3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 30 Aug 2018 20:05:13 -0400 Subject: [PATCH] Fix first clock edge and --x-initial-edge, bug1327. --- Changes | 2 + src/V3AstNodes.h | 8 +- src/V3CCtors.cpp | 3 +- src/V3Clock.cpp | 10 +- src/V3EmitC.cpp | 3 - test_regress/t/t_clk_inp_init.cpp | 67 ++++ test_regress/t/t_clk_inp_init.pl | 18 + test_regress/t/t_clk_inp_init.v | 82 +++++ test_regress/t/t_trace_cat.out | 194 +++++------ test_regress/t/t_trace_cat_renew_0000.out | 104 +++--- test_regress/t/t_trace_cat_renew_0100.out | 94 ++--- test_regress/t/t_trace_cat_reopen_0000.out | 104 +++--- test_regress/t/t_trace_cat_reopen_0100.out | 94 ++--- test_regress/t/t_trace_timescale.out | 382 ++++++++++----------- 14 files changed, 671 insertions(+), 494 deletions(-) create mode 100644 test_regress/t/t_clk_inp_init.cpp create mode 100755 test_regress/t/t_clk_inp_init.pl create mode 100644 test_regress/t/t_clk_inp_init.v diff --git a/Changes b/Changes index e9ea58416..ef7c31fde 100644 --- a/Changes +++ b/Changes @@ -29,6 +29,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix clocker attributes to not propagate on concats. [John Coiner] +**** Fix first clock edge and --x-initial-edge, bug1327. [Rupert Swarbrick] + * Verilator 3.926 2018-08-22 diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index f482cd2c7..b276a854b 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -1121,6 +1121,7 @@ private: bool m_isPullup:1; // Tri1 bool m_isIfaceParent:1; // dtype is reference to interface present in this module bool m_isDpiOpenArray:1; // DPI import open array + bool m_noReset:1; // Do not do automated reset/randomization bool m_noSubst:1; // Do not substitute out references bool m_trace:1; // Trace this variable AstVarAttrClocker m_attrClocker; @@ -1135,7 +1136,8 @@ private: m_funcLocal=false; m_funcReturn=false; m_attrClockEn=false; m_attrScBv=false; m_attrIsolateAssign=false; m_attrSFormat=false; m_fileDescr=false; m_isConst=false; m_isStatic=false; m_isPulldown=false; m_isPullup=false; - m_isIfaceParent=false; m_isDpiOpenArray=false; m_noSubst=false; m_trace=false; + m_isIfaceParent=false; m_isDpiOpenArray=false; + m_noReset=false; m_noSubst=false; m_trace=false; m_attrClocker=AstVarAttrClocker::CLOCKER_UNKNOWN; } public: @@ -1234,6 +1236,8 @@ public: void funcReturn(bool flag) { m_funcReturn = flag; } void isDpiOpenArray(bool flag) { m_isDpiOpenArray=flag; } bool isDpiOpenArray() const { return m_isDpiOpenArray; } + void noReset(bool flag) { m_noReset=flag; } + bool noReset() const { return m_noReset; } void noSubst(bool flag) { m_noSubst=flag; } bool noSubst() const { return m_noSubst; } void trace(bool flag) { m_trace=flag; } @@ -5669,7 +5673,7 @@ public: class AstCReset : public AstNodeStmt { - //Reset variable at startup + // Reset variable at startup public: AstCReset(FileLine* fl, AstNode* exprsp) : AstNodeStmt(fl) { diff --git a/src/V3CCtors.cpp b/src/V3CCtors.cpp index 596955b4f..faf1a9fc7 100644 --- a/src/V3CCtors.cpp +++ b/src/V3CCtors.cpp @@ -151,7 +151,8 @@ void V3CCtors::cctorsAll() { V3CCtorsVisitor var_reset (modp, "_ctor_var_reset"); for (AstNode* np = modp->stmtsp(); np; np = np->nextp()) { if (AstVar* varp = VN_CAST(np, Var)) { - if (!varp->isIfaceParent() && !varp->isIfaceRef()) { + if (!varp->isIfaceParent() && !varp->isIfaceRef() + && !varp->noReset()) { var_reset.add(new AstCReset(varp->fileline(), new AstVarRef(varp->fileline(), varp, true))); } } diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index 1adae9857..7ace2db48 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -51,9 +51,7 @@ private: // NODE STATE // Cleared each Module: // AstVarScope::user1p() -> AstVarScope*. Temporary signal that was created. - // AstVarScope::user2p() -> AstVarScope*. Temporary signal for change detects AstUser1InUse m_inuser1; - AstUser2InUse m_inuser2; // TYPES enum { DOUBLE_OR_RATE = 10 }; // How many | per ||, Determined experimentally as best @@ -79,10 +77,18 @@ private: if (!varp->width1()) varp->v3error("Unsupported: Clock edge on non-single bit signal: "<prettyName()); string newvarname = ((string)"__Vclklast__"+vscp->scopep()->nameDotless()+"__"+varp->name()); AstVar* newvarp = new AstVar(vscp->fileline(), AstVarType::MODULETEMP, newvarname, VFlagLogicPacked(), 1); + newvarp->noReset(true); // Reset by below assign m_modp->addStmtp(newvarp); AstVarScope* newvscp = new AstVarScope(vscp->fileline(), m_scopep, newvarp); vscp->user1p(newvscp); m_scopep->addVarp(newvscp); + // Add init + AstNode* fromp = new AstVarRef(newvarp->fileline(), vscp, false); + if (v3Global.opt.xInitialEdge()) fromp = new AstNot(fromp->fileline(), fromp); + AstNode* newinitp = new AstAssign(vscp->fileline(), + new AstVarRef(newvarp->fileline(), newvscp, true), + fromp); + addToInitial(newinitp); // At bottom, assign them AstAssign* finalp = new AstAssign(vscp->fileline(), diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index f478553d4..d22ce74c9 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -1696,9 +1696,6 @@ void EmitCImp::emitVarReset(AstVar* varp) { // with any initial block settings. if (zeroit || (v3Global.opt.xInitialEdge() && varp->isUsedClock())) { puts(" = 0;\n"); - } else if (v3Global.opt.xInitialEdge() - && (0 == varp->name().find("__Vclklast__"))) { - puts(" = 1;\n"); } else { puts(" = VL_RAND_RESET_"); emitIQW(varp); diff --git a/test_regress/t/t_clk_inp_init.cpp b/test_regress/t/t_clk_inp_init.cpp new file mode 100644 index 000000000..1f3f13991 --- /dev/null +++ b/test_regress/t/t_clk_inp_init.cpp @@ -0,0 +1,67 @@ +// Test defines +// Generated header +#include "Vt_clk_inp_init.h" +// General headers +#include "verilated.h" + +Vt_clk_inp_init* topp; + +vluint64_t main_time; +double sc_time_stamp() { + return main_time; +} + +void oneTest(int seed) { + double sim_time = 1000; + +#ifdef TEST_VERBOSE + VL_PRINTF("== Seed=%d\n", seed); +#endif + + // Randomise initial state + srand48(seed); + srand48(5); + Verilated::randReset(123); + + topp = new Vt_clk_inp_init("top"); + + // Start not in reset + topp->rst_n = 1; + topp->clk = 0; + topp->eval(); + + // Tick for a little bit + while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { + topp->clk = 0; + topp->eval(); + + main_time += 5; + + topp->clk = 1; + topp->eval(); + + main_time += 5; + } + + if (!Verilated::gotFinish()) { + vl_fatal(__FILE__,__LINE__,"main", "%Error: Timeout; never got a $finish"); + } + + topp->final(); + delete topp; topp=NULL; +} + +int main(int argc, char **argv, char **env) { + Verilated::commandArgs(argc, argv); +#if VL_DEBUG + //Verilated::debug(1); +#endif + + for (int seed=123; seed<133; ++seed) { + oneTest(seed); + } + + return 0; +} + + diff --git a/test_regress/t/t_clk_inp_init.pl b/test_regress/t/t_clk_inp_init.pl new file mode 100755 index 000000000..a752bc243 --- /dev/null +++ b/test_regress/t/t_clk_inp_init.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2018 by Argon Design. This program is free software; you +# can redistribute it and/or modify it under the terms of either the +# GNU Lesser General Public License Version 3 or the Perl Artistic +# License Version 2.0. + +scenarios(simulator => 1); + +compile(make_main => 0, + verilator_flags2 => ["-CFLAGS -g3 --exe $Self->{t_dir}/$Self->{name}.cpp"]); + +execute(check_finished => 1); + +ok(1); +1; diff --git a/test_regress/t/t_clk_inp_init.v b/test_regress/t/t_clk_inp_init.v new file mode 100644 index 000000000..d9f7b9726 --- /dev/null +++ b/test_regress/t/t_clk_inp_init.v @@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Check initialisation of cloned clock variables +// +// This tests issue 1327 (Strange initialisation behaviour with +// "VinpClk" cloned clock variables) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Rupert Swarbrick (Argon Design). + + +// bug1327 +// This models some device under test with an asynchronous reset pin +// which counts to 15. +module dut (input wire clk, + input wire rst_n, + output wire done); + + reg [3:0] counter; + + always @(posedge clk or negedge rst_n) begin + if (rst_n & ! clk) begin + $display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.", + $time, clk, rst_n); + $stop; + end + + if (! rst_n) begin + counter <= 4'd0; + end else begin + counter <= counter < 4'd15 ? counter + 4'd1 : counter; + end + end + + assign done = rst_n & (counter == 4'd15); +endmodule + + +module t(input wire clk, + input wire rst_n); + + wire dut_done; + + // A small FSM for driving the test + // + // This is just designed to be enough to force Verilator to make a + // "VinpClk" variant of dut_rst_n. + + // Possible states: + // + // 0: Device in reset + // 1: Device running + // 2: Device finished + reg [1:0] state; + always @(posedge clk or negedge rst_n) begin + if (! rst_n) begin + state <= 0; + end else begin + if (state == 2'd0) begin + // One clock after resetting the device, we switch to running + // it. + state <= 2'd1; + end + else if (state == 2'd1) begin + // If the device is running, we switch to finished when its + // done signal goes high. + state <= dut_done ? 2'd2 : 2'd1; + end + else begin + // If the dut has finished, the test is done. + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + wire dut_rst_n = rst_n & (state != 0); + + wire done; + dut dut_i (.clk (clk), + .rst_n (dut_rst_n), + .done (dut_done)); + +endmodule diff --git a/test_regress/t/t_trace_cat.out b/test_regress/t/t_trace_cat.out index f3182da5d..8181ac5fa 100644 --- a/test_regress/t/t_trace_cat.out +++ b/test_regress/t/t_trace_cat.out @@ -1,7 +1,7 @@ $version Generated by VerilatedVcd $end -$date Sat Feb 23 20:39:34 2013 +$date Thu Aug 30 16:11:10 2018 $end -$timescale 1ns $end +$timescale 1ns $end $scope module top $end $var wire 1 $ clk $end @@ -14,477 +14,477 @@ $enddefinitions $end #0 -b00000000000000000000000000000001 # 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1$ #157 0$ #158 -b00000000000000000000000001010000 # +b00000000000000000000000001001111 # 1$ #159 0$ #160 -b00000000000000000000000001010001 # +b00000000000000000000000001010000 # 1$ #161 0$ #162 -b00000000000000000000000001010010 # +b00000000000000000000000001010001 # 1$ #163 0$ #164 -b00000000000000000000000001010011 # +b00000000000000000000000001010010 # 1$ #165 0$ #166 -b00000000000000000000000001010100 # +b00000000000000000000000001010011 # 1$ #167 0$ #168 -b00000000000000000000000001010101 # +b00000000000000000000000001010100 # 1$ #169 0$ #170 -b00000000000000000000000001010110 # +b00000000000000000000000001010101 # 1$ #171 0$ #172 -b00000000000000000000000001010111 # +b00000000000000000000000001010110 # 1$ #173 0$ #174 -b00000000000000000000000001011000 # +b00000000000000000000000001010111 # 1$ #175 0$ #176 -b00000000000000000000000001011001 # +b00000000000000000000000001011000 # 1$ #177 0$ #178 -b00000000000000000000000001011010 # +b00000000000000000000000001011001 # 1$ #179 0$ #180 -b00000000000000000000000001011011 # +b00000000000000000000000001011010 # 1$ #181 0$ #182 -b00000000000000000000000001011100 # +b00000000000000000000000001011011 # 1$ #183 0$ #184 -b00000000000000000000000001011101 # +b00000000000000000000000001011100 # 1$ #185 0$ #186 -b00000000000000000000000001011110 # +b00000000000000000000000001011101 # 1$ #187 0$ #188 -b00000000000000000000000001011111 # +b00000000000000000000000001011110 # 1$ #189 0$ diff --git a/test_regress/t/t_trace_cat_reopen_0000.out b/test_regress/t/t_trace_cat_reopen_0000.out index a9bb8fde5..11edcfaad 100644 --- a/test_regress/t/t_trace_cat_reopen_0000.out +++ b/test_regress/t/t_trace_cat_reopen_0000.out @@ -1,7 +1,7 @@ $version Generated by VerilatedVcd $end -$date Sat Feb 23 20:40:11 2013 +$date Thu Aug 30 16:10:58 2018 $end -$timescale 1ns $end +$timescale 1ns $end $scope module top $end $var wire 1 $ clk $end @@ -14,252 +14,252 @@ $enddefinitions $end #0 -b00000000000000000000000000000001 # +b00000000000000000000000000000000 # 1$ #1 0$ #2 -b00000000000000000000000000000010 # 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+b00000000000000000000000000001101 # 1$ #27 0$ #28 -b00000000000000000000000000001111 # +b00000000000000000000000000001110 # 1$ #29 0$ #30 -b00000000000000000000000000010000 # +b00000000000000000000000000001111 # 1$ #31 0$ #32 -b00000000000000000000000000010001 # +b00000000000000000000000000010000 # 1$ #33 0$ #34 -b00000000000000000000000000010010 # +b00000000000000000000000000010001 # 1$ #35 0$ #36 -b00000000000000000000000000010011 # +b00000000000000000000000000010010 # 1$ #37 0$ #38 -b00000000000000000000000000010100 # +b00000000000000000000000000010011 # 1$ #39 0$ #40 -b00000000000000000000000000010101 # +b00000000000000000000000000010100 # 1$ #41 0$ #42 -b00000000000000000000000000010110 # +b00000000000000000000000000010101 # 1$ #43 0$ #44 -b00000000000000000000000000010111 # +b00000000000000000000000000010110 # 1$ #45 0$ #46 -b00000000000000000000000000011000 # +b00000000000000000000000000010111 # 1$ #47 0$ #48 -b00000000000000000000000000011001 # +b00000000000000000000000000011000 # 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1$ #95 0$ #96 -b00000000000000000000000000110001 # +b00000000000000000000000000110000 # 1$ #97 0$ #98 -b00000000000000000000000000110010 # +b00000000000000000000000000110001 # 1$ #99 0$ diff --git a/test_regress/t/t_trace_cat_reopen_0100.out b/test_regress/t/t_trace_cat_reopen_0100.out index f5fb14784..12d282b11 100644 --- a/test_regress/t/t_trace_cat_reopen_0100.out +++ b/test_regress/t/t_trace_cat_reopen_0100.out @@ -1,7 +1,7 @@ $version Generated by VerilatedVcd $end -$date Sat Feb 23 20:40:11 2013 +$date Thu Aug 30 16:10:58 2018 $end -$timescale 1ns $end +$timescale 1ns $end $scope module top $end $var wire 1 $ clk $end @@ -14,227 +14,227 @@ $enddefinitions $end #100 -b00000000000000000000000000110011 # +b00000000000000000000000000110010 # 1$ #101 0$ #102 -b00000000000000000000000000110100 # +b00000000000000000000000000110011 # 1$ #103 0$ #104 -b00000000000000000000000000110101 # +b00000000000000000000000000110100 # 1$ #105 0$ #106 -b00000000000000000000000000110110 # +b00000000000000000000000000110101 # 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