From edf6a40f1994d9a237b82e7aefeb9a83c85c2d5b Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 18 Jul 2020 17:35:20 -0400
Subject: [PATCH] Fix VL_CONSTHI truncation (#2473)

---
 include/verilated.h          | 16 +++++------
 test_regress/t/t_const_hi.pl | 21 ++++++++++++++
 test_regress/t/t_const_hi.v  | 53 ++++++++++++++++++++++++++++++++++++
 3 files changed, 82 insertions(+), 8 deletions(-)
 create mode 100755 test_regress/t/t_const_hi.pl
 create mode 100644 test_regress/t/t_const_hi.v

diff --git a/include/verilated.h b/include/verilated.h
index f9cb28fbe..29569ba5e 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -2538,25 +2538,25 @@ static inline WDataOutP VL_CONSTHI_W_1X(int obits, int lsb, WDataOutP obase,
                                         EData d0) VL_MT_SAFE {
     WDataOutP o = obase + VL_WORDS_I(lsb);
     o[0] = d0;
-    _END(obits,1);
+    _END(obits, VL_WORDS_I(lsb) + 1);
 }
 static inline WDataOutP VL_CONSTHI_W_2X(int obits, int lsb, WDataOutP obase,
                                         EData d1, EData d0) VL_MT_SAFE {
     WDataOutP o = obase + VL_WORDS_I(lsb);
     o[0] = d0;  o[1] = d1;
-    _END(obits,2);
+    _END(obits, VL_WORDS_I(lsb) + 2);
 }
 static inline WDataOutP VL_CONSTHI_W_3X(int obits, int lsb, WDataOutP obase,
                                         EData d2, EData d1, EData d0) VL_MT_SAFE {
     WDataOutP o = obase + VL_WORDS_I(lsb);
     o[0] = d0;  o[1] = d1;  o[2] = d2;
-    _END(obits,3);
+    _END(obits, VL_WORDS_I(lsb) + 3);
 }
 static inline WDataOutP VL_CONSTHI_W_4X(int obits, int lsb, WDataOutP obase,
                                         EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE {
     WDataOutP o = obase + VL_WORDS_I(lsb);
     o[0] = d0;  o[1] = d1;  o[2] = d2;  o[3] = d3;
-    _END(obits,4);
+    _END(obits, VL_WORDS_I(lsb) + 4);
 }
 static inline WDataOutP VL_CONSTHI_W_5X(int obits, int lsb, WDataOutP obase,
                                         EData d4,
@@ -2564,7 +2564,7 @@ static inline WDataOutP VL_CONSTHI_W_5X(int obits, int lsb, WDataOutP obase,
     WDataOutP o = obase + VL_WORDS_I(lsb);
     o[0] = d0;  o[1] = d1;  o[2] = d2;  o[3] = d3;
     o[4] = d4;
-    _END(obits,5);
+    _END(obits, VL_WORDS_I(lsb) + 5);
 }
 static inline WDataOutP VL_CONSTHI_W_6X(int obits, int lsb, WDataOutP obase,
                                         EData d5, EData d4,
@@ -2572,7 +2572,7 @@ static inline WDataOutP VL_CONSTHI_W_6X(int obits, int lsb, WDataOutP obase,
     WDataOutP o = obase + VL_WORDS_I(lsb);
     o[0] = d0;  o[1] = d1;  o[2] = d2;  o[3] = d3;
     o[4] = d4;  o[5] = d5;
-    _END(obits,6);
+    _END(obits, VL_WORDS_I(lsb) + 6);
 }
 static inline WDataOutP VL_CONSTHI_W_7X(int obits, int lsb, WDataOutP obase,
                                         EData d6, EData d5, EData d4,
@@ -2580,7 +2580,7 @@ static inline WDataOutP VL_CONSTHI_W_7X(int obits, int lsb, WDataOutP obase,
     WDataOutP o = obase + VL_WORDS_I(lsb);
     o[0] = d0;  o[1] = d1;  o[2] = d2;  o[3] = d3;
     o[4] = d4;  o[5] = d5;  o[6] = d6;
-    _END(obits,7);
+    _END(obits, VL_WORDS_I(lsb) + 7);
 }
 static inline WDataOutP VL_CONSTHI_W_8X(int obits, int lsb, WDataOutP obase,
                                         EData d7, EData d6, EData d5, EData d4,
@@ -2588,7 +2588,7 @@ static inline WDataOutP VL_CONSTHI_W_8X(int obits, int lsb, WDataOutP obase,
     WDataOutP o = obase + VL_WORDS_I(lsb);
     o[0] = d0;  o[1] = d1;  o[2] = d2;  o[3] = d3;
     o[4] = d4;  o[5] = d5;  o[6] = d6;  o[7] = d7;
-    _END(obits,8);
+    _END(obits, VL_WORDS_I(lsb) + 8);
 }
 
 #undef _END
diff --git a/test_regress/t/t_const_hi.pl b/test_regress/t/t_const_hi.pl
new file mode 100755
index 000000000..a17622844
--- /dev/null
+++ b/test_regress/t/t_const_hi.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2004 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_const_hi.v b/test_regress/t/t_const_hi.v
new file mode 100644
index 000000000..edf2afef4
--- /dev/null
+++ b/test_regress/t/t_const_hi.v
@@ -0,0 +1,53 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+   reg [1:0] reg_i;
+   reg [1049:0] pad0;
+   reg [1049:0] reg_o;
+   reg [1049:0] spad1;
+
+   /*AUTOWIRE*/
+
+   always_comb begin
+      if (reg_i[1] == 1'b1)
+        reg_o = {986'd0, 64'hffff0000ffff0000};
+      else if (reg_i[0] == 1'b1)
+        reg_o = {64'hffff0000ffff0000, 986'd0};
+      else
+        reg_o = 1050'd0;
+   end
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 0) begin
+         reg_i <= 2'b00;
+         pad0 <= '1;
+         spad1 <= '1;
+      end
+      else if (cyc == 1) begin
+         reg_i <= 2'b01;
+      end
+      else if (cyc == 2) begin
+         if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop;
+         reg_i <= 2'b10;
+      end
+      else if (cyc == 99) begin
+         if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop;
+         if (pad0 != '1) $stop;
+         if (spad1 != '1) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule