diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md index b5956e2de..630291446 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -1,6 +1,6 @@ --- name: Bug report -about: Something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) +about: Use this to report that something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) title: '' labels: new assignees: '' @@ -15,4 +15,4 @@ What 'verilator --version' are you using? Did you try it with the git master ve What OS and distribution are you using? -Would you be willing to try to fix Verilator yourself with assistance? +May we assist you in trying to fix this in Verilator yourself? diff --git a/.github/ISSUE_TEMPLATE/feature.md b/.github/ISSUE_TEMPLATE/feature.md index 3cc485eda..99f8f2689 100644 --- a/.github/ISSUE_TEMPLATE/feature.md +++ b/.github/ISSUE_TEMPLATE/feature.md @@ -1,6 +1,6 @@ --- name: Feature Request -about: Request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) +about: Use this to request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) title: '' labels: new assignees: '' @@ -13,4 +13,4 @@ What would you like added/supported? Can you attach an example that runs on other simulators? (Must be openly licensed, ideally in test_regress format.) -May we assist you in trying to fix this yourself? +May we assist you in trying to fix this in Verilator yourself? diff --git a/.github/ISSUE_TEMPLATE/questions.md b/.github/ISSUE_TEMPLATE/questions.md index 0571931ca..32f9385f7 100644 --- a/.github/ISSUE_TEMPLATE/questions.md +++ b/.github/ISSUE_TEMPLATE/questions.md @@ -1,6 +1,6 @@ --- name: Q and A, or Other -about: Ask a question, not related to a specific bug or feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) +about: Use this to ask a question, not related to a specific bug nor feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) title: '' labels: new assignees: '' diff --git a/CPPLINT.cfg b/CPPLINT.cfg new file mode 100644 index 000000000..3b872606e --- /dev/null +++ b/CPPLINT.cfg @@ -0,0 +1,17 @@ +set noparent +linelength=100 +filter=-build/c++11 +filter=-build/header_guard +filter=-build/include_order +filter=-build/include_subdir +filter=-readability/inheritance +filter=-readability/nolint +filter=-readability/todo +filter=-runtime/references +filter=-whitespace/blank_line +filter=-whitespace/empty_if_body +filter=-whitespace/indent +filter=-whitespace/newline +filter=-whitespace/braces +filter=-whitespace/parens +filter=-whitespace/todo diff --git a/Changes b/Changes index 5e63dfaec..b817abc5a 100644 --- a/Changes +++ b/Changes @@ -8,6 +8,72 @@ The changes in each Verilator version are described below. The contributors that suggested a given feature are shown in []. Thanks! +Verilator 4.220 2022-03-12 +========================== + +**Minor:** + +* Removed the deprecated lint_off flag -msg; use -rule instead. +* Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead. +* Suppress WIDTH warning on negate using carry bit (#3295). [Peter Monsson] +* Add trace dumpvars() call for selective runtime tracing (#3322). [Shunyao CAD] +* Add VERILATOR_VERSION_INTEGER for determining API (#3343). [Larry Doolittle] +* Improve various V3Combine algorithm details (#3328). [Yutetsu TAKATSUKASA] +* Improve various V3Order algorithm details. [Geza Lore] +* Fix macOS arm64 build (#3285) (#3291). [Guokai Chen] +* Fix signed number operation (#3294) (#3308). [Raynard Qiao] +* Fix FST traces to include vector range (#3296) (#3297). [Jamie Iles] +* Fix skipping public enum values with four-state values (#3303). +* Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman] +* Fix class stringification on wide arrays (#3312). [Iru Cai] +* Fix $fscanf etc to return -1 on EOF (#3313). [Jose Tejada] +* Fix public function arguments that are arrayed (#3316). [pawel256] +* Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka] +* Fix crash in recursive module inlining (#3324). [Larry Doolittle] +* Fix VL_RESTORER behavior on passing a lvalue reference (#3326). [HungMingWu] +* Fix compile error with --trace-fst --sc (#3332). [leavinel] +* Fix cast to array types (#3333). [Todd Strader] +* Fix Vdeeptemp error with --threads and --compiler clang (#3338). [Per Karlsson] + + +Verilator 4.218 2022-01-17 +========================== + +**Major:** + +* Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type. + In general this should be backward compatible, but may lead to some + wrapper code needing changes. +* Option --cdc is deprecated and is planned for removal, + file a bug if this is still being used. + +**Minor:** + +* Support class static members (#2233). +* Support force/release (#2431) (#2593). [Shunyao CAD] +* Add 'forceable' attribute to allow forcing from C++. (#3272). [Geza Lore, Shunyao CAD] +* Support lower dimension looping in foreach loops (#3172). [Ehab Ibrahim] +* Support up to 64 bit enums for .next/.prev/.name (#3244). [Alexander Grobman] +* Reduce .rodata footprint of trace initialization (#3250). [Geza Lore, Shunyao CAD] +* Support FST tracing in hierarchical Verilation (#3251). [Yutetsu TAKATSUKASA] +* Use C++11 standard types for MacOS portability (#3254) (#3257). [Adrien Le Masle] +* Fix make support for BSD ar (#2999) (#3256). [Julie Schwartz] +* Fix bad ending address on $readmem (#3205). [Julie Schwartz] +* Fix MSWIN compile error (#2681). [Unai Martinez-Corral] +* Fix break under foreach loop (#3230). +* Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235). [Adrien Le Masle] +* Fix $sformat of inputs/outputs (#3236). [Adrien Le Masle] +* Fix associative array first method as statement (#3228). [Adrien Le Masle] +* Fix associative array foreach loop (#3229). +* Fix $fclose not accepting expressions (#3237). [Julie Schwartz] +* Fix $random not updating seed (#3238). [Julie Schwartz] +* Fix top level param overwrite when package has same param (#3241) (#3247). [Adrien Le Masle] +* Fix spurious UNUSED by ignoring inout pin connections (#3242). [Julie Schwartz] +* Fix splitting of _eval and other top level functions. [Geza Lore, Shunyao CAD] +* Fix internal error by inout port (#3258). [Yutetsu TAKATSUKASA] +* Fix GCC 11 compile error (#3273). [HungMingWu] + + Verilator 4.216 2021-12-05 ========================== @@ -3762,7 +3828,7 @@ Verilator 0.0 1994-07-08 Copyright ========= -Copyright 2001-2021 by Wilson Snyder. This program is free software; you +Copyright 2001-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/Makefile.in b/Makefile.in index c381eda44..231fbf75b 100644 --- a/Makefile.in +++ b/Makefile.in @@ -7,7 +7,7 @@ # #***************************************************************************** # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/README.rst b/README.rst index 033567427..aab9e30af 100644 --- a/README.rst +++ b/README.rst @@ -137,7 +137,7 @@ Related Projects Open License ============ -Verilator is Copyright 2003-2021 by Wilson Snyder. (Report bugs to +Verilator is Copyright 2003-2022 by Wilson Snyder. (Report bugs to `Verilator Issues `_.) Verilator is free software; you can redistribute it and/or modify it under diff --git a/bin/verilator b/bin/verilator index 505933437..b216b6f7d 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1,7 +1,7 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -459,7 +459,7 @@ description of these arguments. The latest version is available from L. -Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +Copyright 2003-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_ccache_report b/bin/verilator_ccache_report index dd6d47897..f895db4ae 100755 --- a/bin/verilator_ccache_report +++ b/bin/verilator_ccache_report @@ -14,7 +14,7 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""Report ccache behavior of a Verilated model build.""", epilog= - """Copyright 2002-2021 by Wilson Snyder. This program is free software; you + """Copyright 2002-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_coverage b/bin/verilator_coverage index 0ec1f1bac..4b73550c5 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -1,7 +1,7 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -187,7 +187,7 @@ L. The latest version is available from L. -Copyright 2003-2021 by Wilson Snyder. This program is free software; you +Copyright 2003-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_difftree b/bin/verilator_difftree index ab612bc5c..3e8315691 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -38,10 +38,10 @@ def diff_dir(a, b): anyfile = False for base in sorted(files.keys()): + if (not 'a' in files[base]) or (not 'b' in files[base]): + continue a = files[base]['a'] b = files[base]['b'] - if not a or not b: - continue print("=" * 70) print("= %s <-> %s" % (a, b)) diff_file(a, b) @@ -113,7 +113,7 @@ directories, ignoring irrelevant pointer differences. For documentation see https://verilator.org/guide/latest/exe_verilator_difftree.html -Copyright 2005-2021 by Wilson Snyder. This program is free software; you +Copyright 2005-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 17d90e8e4..5958cc518 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -463,7 +463,7 @@ parser = argparse.ArgumentParser( For documentation see https://verilator.org/guide/latest/exe_verilator_gantt.html -Copyright 2018-2021 by Wilson Snyder. This program is free software; you +Copyright 2018-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_includer b/bin/verilator_includer index 356849827..5fe3ce6c5 100755 --- a/bin/verilator_includer +++ b/bin/verilator_includer @@ -1,7 +1,7 @@ #!/usr/bin/env perl # DESCRIPTION: Print include statements for each ARGV # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index 1b564b5ec..4f6b82442 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -182,7 +182,7 @@ in each Verilog block. For documentation see https://verilator.org/guide/latest/exe_verilator_profcfunc.html -Copyright 2002-2021 by Wilson Snyder. This program is free software; you +Copyright 2002-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/codecov.yml b/codecov.yml index c4e52ff0d..315072af8 100644 --- a/codecov.yml +++ b/codecov.yml @@ -1,6 +1,6 @@ # DESCRIPTION: codecov.io config # -# Copyright 2020-2021 by Wilson Snyder. This program is free software; you +# Copyright 2020-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/configure.ac b/configure.ac index 0b0ad9b3a..22e745ffd 100644 --- a/configure.ac +++ b/configure.ac @@ -1,13 +1,13 @@ # DESCRIPTION: Process this file with autoconf to produce a configure script. # -# Copyright 2003-2021 by Wilson Snyder. Verilator is free software; you +# Copyright 2003-2022 by Wilson Snyder. Verilator is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[4.216 2021-12-05], +AC_INIT([Verilator],[4.220 2022-03-12], [https://verilator.org], [verilator],[https://verilator.org]) # When releasing, also update header of Changes file @@ -22,6 +22,8 @@ AC_MSG_RESULT([configuring for $PACKAGE_STRING]) PACKAGE_VERSION_NUMBER=`AS_ECHO("$PACKAGE_VERSION") | sed 's/ .*//g'` AC_SUBST(PACKAGE_VERSION_NUMBER) AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number]) +VERILATOR_VERSION_INTEGER=`AS_ECHO("$PACKAGE_VERSION") | [sed 's/\([0-9]\)\.\([0-9][0-9][0-9]\) .*/\1\2000/g']` +AC_SUBST(VERILATOR_VERSION_INTEGER) # Ignore automake flags passed by Ubuntu builds AC_ARG_ENABLE([dependency-tracking], @@ -143,10 +145,10 @@ AC_SUBST(CFG_WITH_LONGTESTS) AC_MSG_RESULT($CFG_WITH_LONGTESTS) # Compiler flags (ensure they are not empty to avoid configure defaults) -CFLAGS+=" " -CPPFLAGS+=" " -CXXFLAGS+=" " -LDFLAGS+=" " +CFLAGS="$CFLAGS " +CPPFLAGS="$CPPFLAGS " +CXXFLAGS="$CXXFLAGS " +LDFLAGS="$LDFLAGS " # Checks for programs. AC_PROG_CC diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index ca842b952..90de66590 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -3,12 +3,14 @@ under the Developer Certificate of Origin (https://developercertificate.org/). Please see the Verilator manual for 200+ additional contributors. Thanks to all. +Adrien Le Masle Ahmed El-Mahmoudy Alex Chadwick Àlex Torregrosa Ameya Vikram Singh Andreas Kuster Chris Randall +Chuxuan Wang Conor McCullough Dan Petrisko Daniel Bates @@ -16,6 +18,7 @@ David Horton David Metz David Stanford David Turner +Drew Ranck Drew Taussig Driss Hafdi Edgar E. Iglesias @@ -27,9 +30,11 @@ Geza Lore Gianfranco Costamagna Glen Gibb Graham Rushton +Guokai Chen Harald Heckmann Howard Su Huang Rui +HungMingWu HyungKi Jeong Iru Cai Ivan Vnučec @@ -38,6 +43,7 @@ James Hanlon James Hutchinson James Pallister Jamey Hicks +Jamie Iles Jan Van Winkel Jean Berniolles Jeremy Bennett @@ -53,6 +59,7 @@ Keith Colbert Kevin Kiningham Krzysztof Bieganski Kuba Ober +Larry Doolittle Ludwig Rogiers Lukasz Dalek Maarten De Braekeleer @@ -81,6 +88,7 @@ Pieter Kapsenberg Piotr Binkowski Qingyao Sun Rafal Kapuscik +Raynard Qiao Richard Myers Rupert Swarbrick Samuel Riedel diff --git a/docs/Makefile b/docs/Makefile index aac5c9cc8..7e4a96d69 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -5,7 +5,7 @@ # # Code available from: https://verilator.org # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/docs/bin/vl_sphinx_extract b/docs/bin/vl_sphinx_extract index 1b2c27d07..97d5b1ec5 100755 --- a/docs/bin/vl_sphinx_extract +++ b/docs/bin/vl_sphinx_extract @@ -40,7 +40,7 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""Read a file and extract documentation data.""", epilog= - """ Copyright 2021-2021 by Wilson Snyder. This package is free software; + """ Copyright 2021-2022 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/bin/vl_sphinx_fix b/docs/bin/vl_sphinx_fix index ed6d06107..3c18cb1c7 100755 --- a/docs/bin/vl_sphinx_fix +++ b/docs/bin/vl_sphinx_fix @@ -55,7 +55,7 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""Post-process Sphinx HTML.""", epilog= - """ Copyright 2021-2021 by Wilson Snyder. This package is free software; + """ Copyright 2021-2022 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/guide/changes.rst b/docs/guide/changes.rst index 439aaae79..3688dc00e 100644 --- a/docs/guide/changes.rst +++ b/docs/guide/changes.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 **************** diff --git a/docs/guide/conf.py b/docs/guide/conf.py index 7bc25adee..0714e50c7 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -36,7 +36,7 @@ def setup(app): # -- Project information project = 'Verilator' -copyright = '2021 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0' +copyright = '2022 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0' author = 'Wilson Snyder' # The master toctree document. diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index bbe35e5aa..49fdc4f79 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Connecting: @@ -422,7 +422,7 @@ accesses the above signal "readme" would be: .. code-block:: bash - cat >sim_main.cpp <<'<sim_main.cpp <<'EOF' #include "Vour.h" #include "verilated.h" #include "verilated_vpi.h" // Required to get definitions diff --git a/docs/guide/contributing.rst b/docs/guide/contributing.rst index d3d091bae..4593f9355 100644 --- a/docs/guide/contributing.rst +++ b/docs/guide/contributing.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******************************* diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst index 849fa795b..54e5400e2 100644 --- a/docs/guide/contributors.rst +++ b/docs/guide/contributors.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ************************ diff --git a/docs/guide/copyright.rst b/docs/guide/copyright.rst index e00dc420a..50bccc55f 100644 --- a/docs/guide/copyright.rst +++ b/docs/guide/copyright.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********* @@ -8,7 +8,7 @@ Copyright The latest version of Verilator is available from `https://verilator.org `_. -Copyright 2003-2021 by Wilson Snyder. This program is free software; you +Copyright 2003-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst index 9f8edda3b..87107cca1 100644 --- a/docs/guide/deprecations.rst +++ b/docs/guide/deprecations.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Deprecations @@ -16,10 +16,6 @@ Verilated_heavy.h "verilated.h". Verilated_heavy.h is planned for removal no sooner than July 2022. -Configuration File -msg - The :vlopt:`lint_off` "-msg" option has been replaced with the "-rule" - option. "-msg" is planned for removal no sooner than January 2021. - -XML locations - The XML "fl" attribute has been replaced with the "loc" attribute. "fl" - is planned for removal no sooner than January 2021. +Option `--cdc` + The experimental `--cdc` option is believed to be generally unused and is + planned for removal no sooner than January 2023. diff --git a/docs/guide/environment.rst b/docs/guide/environment.rst index f52fe0a41..99c283e6b 100644 --- a/docs/guide/environment.rst +++ b/docs/guide/environment.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Environment diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst index 1894c2074..f5d55c8da 100644 --- a/docs/guide/example_cc.rst +++ b/docs/guide/example_cc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Example C++ Execution: diff --git a/docs/guide/example_common_install.rst b/docs/guide/example_common_install.rst index 5735b5150..07697c4f3 100644 --- a/docs/guide/example_common_install.rst +++ b/docs/guide/example_common_install.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 First you need Verilator installed, see :ref:`Installation`. In brief, if diff --git a/docs/guide/example_dist.rst b/docs/guide/example_dist.rst index 493e3d204..5b45ed1eb 100644 --- a/docs/guide/example_dist.rst +++ b/docs/guide/example_dist.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Examples in the Distribution: diff --git a/docs/guide/example_sc.rst b/docs/guide/example_sc.rst index 4e982f3b3..ef8eb03ca 100644 --- a/docs/guide/example_sc.rst +++ b/docs/guide/example_sc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Example SystemC Execution: diff --git a/docs/guide/examples.rst b/docs/guide/examples.rst index 83b94f770..d57a82d57 100644 --- a/docs/guide/examples.rst +++ b/docs/guide/examples.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Examples: diff --git a/docs/guide/exe_sim.rst b/docs/guide/exe_sim.rst index ba49b2ca7..e8af13bfe 100644 --- a/docs/guide/exe_sim.rst +++ b/docs/guide/exe_sim.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Simulation Runtime Arguments: diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 40d9fc8e2..55a356ee4 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator Arguments @@ -884,7 +884,7 @@ Summary: Using DPI imports/exports is allowed and generally relatively safe in terms of information disclosed, which is limited to the DPI function - prototyptes. Use of the VPI is not recommended as many design details + prototypes. Use of the VPI is not recommended as many design details may be exposed, and an INSECURE warning will be issued. .. option:: --protect-lib @@ -1364,9 +1364,10 @@ Summary: .. note:: This option applies only to values which are explicitly written as X - in the Verilog source code. Initial values of clocks are set to 0 - unless `--x-initial-edge` is specified. Initial values of all other - state holding variables are controlled with `--x-initial`. + in modules (not classes) in the Verilog source code. Initial values + of clocks are set to 0 unless `--x-initial-edge` is + specified. Initial values of all other state holding variables are + controlled with `--x-initial`. .. option:: --x-initial 0 @@ -1513,7 +1514,7 @@ The grammar of configuration commands is as follows: .. option:: no_clocker -module "" [-function ""] -var "" Indicates that the signal is used as clock or not. This information is - used by Verilator to mark the signal and any derrived signals as + used by Verilator to mark the signal and any derived signals as clocker. See :vlopt:`--clk`. Same as :option:`/*verilator&32;clocker*/` metacomment. @@ -1528,6 +1529,14 @@ The grammar of configuration commands is as follows: Same as :option:`/*verilator&32;coverage_block_off*/` metacomment. +.. option:: forceable -module "" -var "" + + Generate public `__VforceEn` and `__VforceVal` signals + that can be used to force/release a signal from C++ code. The force control + signals are created as :option:`public_flat` signals. + + Same as :option:`/*verilator&32;forceable*/` metacomment. + .. option:: full_case -file "" -lines .. option:: parallel_case -file "" -lines diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst index 41eba66cf..2bd93e7c0 100644 --- a/docs/guide/exe_verilator_coverage.rst +++ b/docs/guide/exe_verilator_coverage.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_coverage @@ -67,7 +67,7 @@ which have low coverage are written to the output directory. Specifies if the coverage point does not include the count number of coverage hits, then the coverage point will be considered above the -threashold, and the coverage report will put a "%" to indicate the coverage +threshold, and the coverage report will put a "%" to indicate the coverage is not sufficient. Defaults to 10. .. option:: --help diff --git a/docs/guide/exe_verilator_gantt.rst b/docs/guide/exe_verilator_gantt.rst index 3e313f507..2d0e03cc9 100644 --- a/docs/guide/exe_verilator_gantt.rst +++ b/docs/guide/exe_verilator_gantt.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_gantt @@ -13,7 +13,7 @@ For an overview of use of verilator_gantt, see :ref:`Profiling`. Gantt Chart VCD --------------- -Verilated_gnatt creates a value change dump (VCD) format dump file which +Verilated_gantt creates a value change dump (VCD) format dump file which may be viewed in a waveform viewer (e.g. C): .. figure:: figures/fig_gantt_min.png diff --git a/docs/guide/exe_verilator_profcfunc.rst b/docs/guide/exe_verilator_profcfunc.rst index 1283e6f2a..408db9e76 100644 --- a/docs/guide/exe_verilator_profcfunc.rst +++ b/docs/guide/exe_verilator_profcfunc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_profcfunc diff --git a/docs/guide/executables.rst b/docs/guide/executables.rst index 248553266..9bbb50f8c 100644 --- a/docs/guide/executables.rst +++ b/docs/guide/executables.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********************************* diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index ff79df1f4..19951334b 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******************* @@ -185,7 +185,7 @@ or "`ifdef`"'s may break other tools. .. option:: /*verilator&32;no_clocker*/ Specifies that the signal is used as clock or not. This information is - used by Verilator to mark the signal and any derrived signals as + used by Verilator to mark the signal and any derived signals as clocker. See :vlopt:`--clk`. Same as :option:`clocker` and :option:`no_clocker` in configuration @@ -209,6 +209,20 @@ or "`ifdef`"'s may break other tools. (if appropriate :vlopt:`--coverage` flags are passed) after being disabled earlier with :option:`/*verilator&32;coverage_off*/`. +.. option:: /*verilator&32;forceable*/ + + Specifies that the signal (net or variable) should be made forceable from + C++ code by generating public `__VforceEn` and + `__VforceVal` signals The force control signals are created as + :option:`public_flat` signals. + + To force a marked signal from C++, set the corresponding `__VforceVal` + variable to the desired value, and the `__VforceEn` signal to the bitmask + indicating which bits of the signal to force. To force all bits of the + target signal, set `__VforceEn` to all ones. To release the signal (or part + thereof), set appropriate bits of the `__VforceEn` signal to zero. + + Same as :option:`forceable` in configuration files. .. _verilator_hier_block: diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index 845830ae1..14f4281ea 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ****************************** @@ -37,15 +37,15 @@ Does Verilator run under Windows? Yes, ideally run Ubuntu under Windows Subsystem for Linux (WSL2). Alternatively use Cygwin, though this tends to be slower and is not -regurally tested. Verilated output also compiles under Microsoft Visual -C++, but this is also not regurally tested. +regularly tested. Verilated output also compiles under Microsoft Visual +C++, but this is also not regularly tested. Can you provide binaries? """"""""""""""""""""""""" You can install Verilator via the system package manager (apt, yum, etc.) -on many Linux distributions, including Debian, Ubuntu, SuSE, RedHat, and +on many Linux distributions, including Debian, Ubuntu, SuSE, Red Hat, and others. These packages are provided by the Linux distributions and generally will lag the version of the mainline Verilator repository. If no binary package is available for your distribution, how about you set one @@ -134,7 +134,8 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated ... Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; - topp->trace(tfp, 99); // Trace 99 levels of hierarchy + topp->trace(tfp, 99); // Trace 99 levels of hierarchy (or see below) + // tfp->dumpvars(1, "t"); // trace 1 level under "t" tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); ... while (contextp->time() < sim_time && !contextp->gotFinish()) { diff --git a/docs/guide/files.rst b/docs/guide/files.rst index 3f30fbb39..c0896f6df 100644 --- a/docs/guide/files.rst +++ b/docs/guide/files.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ***** @@ -157,7 +157,7 @@ The Verilated executable may produce the following: * - profile.vlt - -profile data file for :ref:`Thread PGO` * - profile_threads.dat - - -profile-threads data file for :command:`verilator_gnatt` + - -profile-threads data file for :command:`verilator_gantt` Verilator_gantt may produce the following: diff --git a/docs/guide/index.rst b/docs/guide/index.rst index d6a60ba57..38f36b9e9 100644 --- a/docs/guide/index.rst +++ b/docs/guide/index.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################### diff --git a/docs/guide/install.rst b/docs/guide/install.rst index b05547858..753215d68 100644 --- a/docs/guide/install.rst +++ b/docs/guide/install.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Installation: @@ -77,7 +77,7 @@ OS Requirements --------------- Verilator is developed and has primary testing on Ubuntu, with additional -testing on FreeBSD and Apple OS-X. Versions have also built on Redhat +testing on FreeBSD and Apple OS-X. Versions have also built on Red Hat Linux, and other flavors of GNU/Linux-ish platforms. Verilator also works on Windows Subsystem for Linux (WSL2), Windows under Cygwin, and Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator itself) diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index f09abbd26..c360b7429 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 *************** @@ -136,7 +136,7 @@ ___05F (5F is the hex code of an underscore.) Bind ---- -sVerilator only supports bind to a target module name, not to an +Verilator only supports bind to a target module name, not to an instance path. @@ -336,6 +336,24 @@ Verilator does not support SEREs yet. All assertion and coverage statements must be simple expressions that complete in one cycle. +Force statement +--------------- + +Verilator supports the procedural `force` (and corresponding `release`) +statement. The behavior of the `force` statement however does not entirely +comply with the IEEE 1800 SystemVerilog standard. According to the standard, +when a procedural statement of the form `force a = b;` is executed, the +simulation should behave as if from that point onwards, a continuous +assignment `assign a = b;` have been added to override the drivers of `a`. +More specifically: the value of `a` should be updated, whenever the value of +`b` changes, all the way until a `release a;` statement is executed. +Verilator instead evaluates the current value of `b` at the time the `force` +statement is executed, and forces `a` to that value, without updating it +until a new `force` or `release` statement is encountered that applies to +`a`. This non-standard behavior is nevertheless consistent with some other +simulators. + + Encrypted Verilog ----------------- diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst index 2c60dd2b8..d69100814 100644 --- a/docs/guide/overview.rst +++ b/docs/guide/overview.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******** diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst index 98114d886..064233697 100644 --- a/docs/guide/simulating.rst +++ b/docs/guide/simulating.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Simulating: diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst index e2e10c32b..d58153684 100644 --- a/docs/guide/verilating.rst +++ b/docs/guide/verilating.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********** @@ -68,7 +68,7 @@ multi-core SoC. Verilator is run in hierarchical mode on the whole SoC. Verilator will make two models, one for the CPU hierarchy block, and one for the SoC. The -Verialted code for the SoC will automatically call the CPU Verilated model. +Verilated code for the SoC will automatically call the CPU Verilated model. The current hierarchical Verilation is based on :vlopt:`--lib-create`. Each hierarchy block is Verilated into a library. User modules of the hierarchy diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index abc4a1ca4..d36133992 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2021 by Wilson Snyder. +.. Copyright 2003-2022 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******************* @@ -447,7 +447,7 @@ List Of Warnings p0(); endmodule - Other tools with similar warnings: Veriable's forbid_defparam_rule. + Other tools with similar warnings: Verible's forbid_defparam_rule. .. option:: DEPRECATED @@ -518,7 +518,7 @@ List Of Warnings Another way DIDNOTCONVERGE may occur is if # delays are used to generate clocks. Verilator ignores the delays and gives an :option:`ASSIGNDLY` or :option:`STMTDLY` warning. If these were suppressed, due to the - absense of the delay, the code may now oscillate. + absence of the delay, the code may now oscillate. Finally, rare, more difficult cases can be debugged like a C++ program; either enter :command:`gdb` and use its tracing facilities, or edit the @@ -528,7 +528,7 @@ List Of Warnings .. option:: ENDCAPSULATED Warns that a class member is declared is local or protected, but is - being accessed from outside that class (if local) or a derrived class + being accessed from outside that class (if local) or a derived class (if protected). Ignoring this warning will only suppress the lint check, it will @@ -924,7 +924,7 @@ List Of Warnings simulate correctly. Other tools with similar warnings: Icarus Verilog's portbind, "warning: - Instantiating module ... with dangling impot port (...)". Slang's + Instantiating module ... with dangling input port (...)". Slang's unconnected-port, "port '...' has no connection". @@ -1217,7 +1217,7 @@ List Of Warnings used to cause some important action at a later time, it might be an important difference. - Some possible work arounds: + Some possible workarounds: * Move the delayed statement into the C++ wrapper file, where the stimulus and clock generation can be done in C++. diff --git a/docs/internals.rst b/docs/internals.rst index 1b9b3e390..50cd05905 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -114,11 +114,11 @@ By convention, each function/method uses the variable ``nodep`` as a pointer to the ``AstNode`` currently being processed. -``AstNVisitor`` +``VNVisitor`` ^^^^^^^^^^^^^^^ The passes are implemented by AST visitor classes. These are implemented by -subclasses of the abstract class, ``AstNVisitor``. Each pass creates an +subclasses of the abstract class, ``VNVisitor``. Each pass creates an instance of the visitor class, which in turn implements a method to perform the pass. @@ -523,10 +523,10 @@ optimization passes. This allows separation of the pass algorithm from the AST on which it operates. Wikipedia provides an introduction to the concept at https://en.wikipedia.org/wiki/Visitor_pattern. -As noted above, all visitors are derived classes of ``AstNVisitor``. All +As noted above, all visitors are derived classes of ``VNVisitor``. All derived classes of ``AstNode`` implement the ``accept`` method, which takes -as argument a reference to an instance or a ``AstNVisitor`` derived class -and applies the visit method of the ``AstNVisitor`` to the invoking AstNode +as argument a reference to an instance or a ``VNVisitor`` derived class +and applies the visit method of the ``VNVisitor`` to the invoking AstNode instance (i.e. ``this``). One possible difficulty is that a call to ``accept`` may perform an edit @@ -604,8 +604,8 @@ There are three ways data is passed between visitor functions. Iterators --------- -``AstNVisitor`` provides a set of iterators to facilitate walking over -the tree. Each operates on the current ``AstNVisitor`` class (as this) +``VNVisitor`` provides a set of iterators to facilitate walking over +the tree. Each operates on the current ``VNVisitor`` class (as this) and takes an argument type ``AstNode*``. ``iterate`` @@ -1183,7 +1183,7 @@ Verilator ideally would support all of IEEE, and has the goal to get close to full support. However the following IEEE sections and features are not anticipated to be ever implemented for the reasons indicated. -IEEE 1800-2017 3.3 recursive modules +IEEE 1800-2017 3.3 modules within modules Little/no tool support, and arguably not a good practice. IEEE 1800-2017 6.12 "shortreal" Little/no tool support, and easily simply promoted to real. @@ -1208,7 +1208,7 @@ IEEE 1800-2017 33 Config Distribution ============ -Copyright 2008-2021 by Wilson Snyder. Verilator is free software; you can +Copyright 2008-2022 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/xml.rst b/docs/xml.rst index c145c5991..9a0656680 100644 --- a/docs/xml.rst +++ b/docs/xml.rst @@ -46,9 +46,6 @@ The XML document consists of 4 sections within the top level hierarchy. Each instance is represented with the ```` element with the following attributes: - - ``fl`` (deprecated): The file id and line number where the module - was instanced. Use ``loc`` instead. - - ``loc``: The file id, first line number, last line number, first column number and last column number of the identifier where the module was instanced, separated by commas. @@ -73,7 +70,7 @@ The XML document consists of 4 sections within the top level Distribution ============ -Copyright 2020-2021 by Wilson Snyder. Verilator is free software; you can +Copyright 2020-2022 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/examples/make_tracing_c/sim_main.cpp b/examples/make_tracing_c/sim_main.cpp index c8ee021a6..c9585dfe9 100644 --- a/examples/make_tracing_c/sim_main.cpp +++ b/examples/make_tracing_c/sim_main.cpp @@ -103,8 +103,8 @@ int main(int argc, char** argv, char** env) { top->eval(); // Read outputs - VL_PRINTF("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x" - " -> oquad=%" VL_PRI64 "x owide=%x_%08x_%08x\n", + VL_PRINTF("[%" PRId64 "] clk=%x rstl=%x iquad=%" PRIx64 " -> oquad=%" PRIx64 + " owide=%x_%08x_%08x\n", contextp->time(), top->clk, top->reset_l, top->in_quad, top->out_quad, top->out_wide[2], top->out_wide[1], top->out_wide[0]); } diff --git a/include/gtkwave/fstapi.c b/include/gtkwave/fstapi.c index 2e28e64ac..b19e0bcaa 100644 --- a/include/gtkwave/fstapi.c +++ b/include/gtkwave/fstapi.c @@ -140,6 +140,10 @@ void **JenkinsIns(void *base_i, const unsigned char *mem, uint32_t length, uint3 #include #endif +#if defined(FST_MACOSX) || defined(__MINGW32__) || defined(__OpenBSD__) || defined(__FreeBSD__) +#define FST_UNBUFFERED_IO +#endif + #ifdef __GNUC__ /* Boolean expression more often true than false */ #define FST_LIKELY(x) __builtin_expect(!!(x), 1) @@ -4577,12 +4581,11 @@ if(sectype == FST_BL_ZWRAPPER) if(!fcomp) { tmpfile_close(&fcomp, &xc->f_nam); return(0); } } -#if defined(FST_MACOSX) +#if defined(FST_UNBUFFERED_IO) setvbuf(fcomp, (char *)NULL, _IONBF, 0); /* keeps gzip from acting weird in tandem with fopen */ #endif #ifdef __MINGW32__ - setvbuf(fcomp, (char *)NULL, _IONBF, 0); /* keeps gzip from acting weird in tandem with fopen */ xc->filename_unpacked = hf; #else if(hf) @@ -4880,7 +4883,7 @@ if((!nam)||(!(xc->f=fopen(nam, "rb")))) char *hf = (char *)calloc(1, flen + 6); int rc; -#if defined(__MINGW32__) || defined(FST_MACOSX) +#if defined(FST_UNBUFFERED_IO) setvbuf(xc->f, (char *)NULL, _IONBF, 0); /* keeps gzip from acting weird in tandem with fopen */ #endif diff --git a/include/verilated.cpp b/include/verilated.cpp index 40c51f000..4401ffb45 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -168,6 +168,19 @@ void vl_stop_maybe(const char* filename, int linenum, const char* hier, bool may } #endif +#ifndef VL_USER_WARN ///< Define this to override the vl_warn function +void vl_warn(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_UNSAFE { + if (false && hier) {} + if (filename && filename[0]) { + // Not VL_PRINTF_MT, already on main thread + VL_PRINTF("%%Warning: %s:%d: %s\n", filename, linenum, msg); + } else { + VL_PRINTF("%%Warning: %s\n", msg); + } + Verilated::runFlushCallbacks(); +} +#endif + //=========================================================================== // Wrapper to call certain functions via messages when multithreaded @@ -201,6 +214,16 @@ void VL_FATAL_MT(const char* filename, int linenum, const char* hier, const char #endif } +void VL_WARN_MT(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_SAFE { +#ifdef VL_THREADED + VerilatedThreadMsgQueue::post(VerilatedMsg{[=]() { // + vl_warn(filename, linenum, hier, msg); + }}); +#else + vl_warn(filename, linenum, hier, msg); +#endif +} + //=========================================================================== // Debug prints @@ -248,13 +271,13 @@ void VL_DBG_MSGF(const char* formatp, ...) VL_MT_SAFE { va_start(ap, formatp); const std::string out = _vl_string_vprintf(formatp, ap); va_end(ap); - // printf("-imm-V{t%d,%" VL_PRI64 "d}%s", VL_THREAD_ID(), _vl_dbg_sequence_number(), + // printf("-imm-V{t%d,%" PRId64 "}%s", VL_THREAD_ID(), _vl_dbg_sequence_number(), // out.c_str()); // Using VL_PRINTF not VL_PRINTF_MT so that we can call VL_DBG_MSGF // from within the guts of the thread execution machinery (and it goes // to the screen and not into the queues we're debugging) - VL_PRINTF("-V{t%u,%" VL_PRI64 "u}%s", VL_THREAD_ID(), _vl_dbg_sequence_number(), out.c_str()); + VL_PRINTF("-V{t%u,%" PRIu64 "}%s", VL_THREAD_ID(), _vl_dbg_sequence_number(), out.c_str()); } #ifdef VL_THREADED @@ -314,11 +337,17 @@ WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp) VL_MT_SAFE { return outwp; } -IData VL_RANDOM_SEEDED_II(IData seed) VL_MT_SAFE { +IData VL_RANDOM_SEEDED_II(IData& seedr) VL_MT_SAFE { + // $random - seed is a new seed to apply, then we return new seed + Verilated::threadContextp()->randSeed(static_cast(seedr)); + seedr = VL_RANDOM_I(); + return VL_RANDOM_I(); +} +IData VL_URANDOM_SEEDED_II(IData seed) VL_MT_SAFE { + // $urandom - seed is a new seed to apply Verilated::threadContextp()->randSeed(static_cast(seed)); return VL_RANDOM_I(); } - IData VL_RAND_RESET_I(int obits) VL_MT_SAFE { if (Verilated::threadContextp()->randReset() == 0) return 0; IData data = ~0; @@ -678,18 +707,17 @@ std::string _vl_vsformat_time(char* tmp, T ld, int timeunit, bool left, size_t w if (!fracDigits) { digits = VL_SNPRINTF(tmp, VL_VALUE_STRING_MAX_WIDTH, "%s%s", ptr, suffix.c_str()); } else { - digits = VL_SNPRINTF(tmp, VL_VALUE_STRING_MAX_WIDTH, "%s.%0*" VL_PRI64 "u%s", ptr, + digits = VL_SNPRINTF(tmp, VL_VALUE_STRING_MAX_WIDTH, "%s.%0*" PRIu64 "%s", ptr, fracDigits, VL_SET_QW(frac), suffix.c_str()); } } else { const vluint64_t integer64 = VL_SET_QW(integer); if (!fracDigits) { - digits = VL_SNPRINTF(tmp, VL_VALUE_STRING_MAX_WIDTH, "%" VL_PRI64 "u%s", integer64, + digits = VL_SNPRINTF(tmp, VL_VALUE_STRING_MAX_WIDTH, "%" PRIu64 "%s", integer64, suffix.c_str()); } else { - digits = VL_SNPRINTF(tmp, VL_VALUE_STRING_MAX_WIDTH, - "%" VL_PRI64 "u.%0*" VL_PRI64 "u%s", integer64, fracDigits, - VL_SET_QW(frac), suffix.c_str()); + digits = VL_SNPRINTF(tmp, VL_VALUE_STRING_MAX_WIDTH, "%" PRIu64 ".%0*" PRIu64 "%s", + integer64, fracDigits, VL_SET_QW(frac), suffix.c_str()); } } } else { @@ -851,7 +879,7 @@ void _vl_vsformat(std::string& output, const char* formatp, va_list ap) VL_MT_SA std::string append; if (lbits <= VL_QUADSIZE) { digits = VL_SNPRINTF( - t_tmp, VL_VALUE_STRING_MAX_WIDTH, "%" VL_PRI64 "d", + t_tmp, VL_VALUE_STRING_MAX_WIDTH, "%" PRId64, static_cast(VL_EXTENDS_QQ(lbits, lbits, ld))); append = t_tmp; } else { @@ -880,8 +908,7 @@ void _vl_vsformat(std::string& output, const char* formatp, va_list ap) VL_MT_SA int digits = 0; std::string append; if (lbits <= VL_QUADSIZE) { - digits - = VL_SNPRINTF(t_tmp, VL_VALUE_STRING_MAX_WIDTH, "%" VL_PRI64 "u", ld); + digits = VL_SNPRINTF(t_tmp, VL_VALUE_STRING_MAX_WIDTH, "%" PRIu64, ld); append = t_tmp; } else { append = VL_DECIMAL_NW(lbits, lwp); @@ -1157,7 +1184,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "0123456789+-xXzZ?_"); if (!t_tmp[0]) goto done; vlsint64_t ld = 0; - std::sscanf(t_tmp, "%30" VL_PRI64 "d", &ld); + std::sscanf(t_tmp, "%30" PRId64, &ld); VL_SET_WQ(owp, ld); break; } @@ -1182,7 +1209,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "0123456789+-xXzZ?_"); if (!t_tmp[0]) goto done; QData ld = 0; - std::sscanf(t_tmp, "%30" VL_PRI64 "u", &ld); + std::sscanf(t_tmp, "%30" PRIu64, &ld); VL_SET_WQ(owp, ld); break; } @@ -1470,7 +1497,7 @@ void VL_FWRITEF(IData fpi, const char* formatp, ...) VL_MT_SAFE { IData VL_FSCANF_IX(IData fpi, const char* formatp, ...) VL_MT_SAFE { // While threadsafe, each thread can only access different file handles FILE* const fp = VL_CVT_I_FP(fpi); - if (VL_UNLIKELY(!fp)) return 0; + if (VL_UNLIKELY(!fp)) return ~0U; // -1 va_list ap; va_start(ap, formatp); @@ -1616,7 +1643,7 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M switch (std::tolower(fmt)) { case 'd': { vlsint64_t lld = 0; - std::sscanf(dp, "%30" VL_PRI64 "d", &lld); + std::sscanf(dp, "%30" PRId64, &lld); VL_SET_WQ(rwp, lld); break; } @@ -1817,7 +1844,7 @@ VlReadMem::VlReadMem(bool hex, int bits, const std::string& filename, QData star m_fp = std::fopen(filename.c_str(), "r"); if (VL_UNLIKELY(!m_fp)) { // We don't report the Verilog source filename as it slow to have to pass it down - VL_FATAL_MT(filename.c_str(), 0, "", "$readmem file not found"); + VL_WARN_MT(filename.c_str(), 0, "", "$readmem file not found"); // cppcheck-suppress resourceLeak // m_fp is nullptr - bug in cppcheck return; } @@ -1876,6 +1903,7 @@ bool VlReadMem::get(QData& addrr, std::string& valuer) { ignore_to_eol = true; } else if (c == '@') { reading_addr = true; + m_anyAddr = true; m_addr = 0; } // Check for hex or binary digits as file format requests @@ -1902,9 +1930,9 @@ bool VlReadMem::get(QData& addrr, std::string& valuer) { lastc = c; } - if (VL_UNLIKELY(m_end != ~0ULL && m_addr <= m_end)) { - VL_FATAL_MT(m_filename.c_str(), m_linenum, "", - "$readmem file ended before specified final address (IEEE 2017 21.4)"); + if (VL_UNLIKELY(m_end != ~0ULL && m_addr <= m_end && !m_anyAddr)) { + VL_WARN_MT(m_filename.c_str(), m_linenum, "", + "$readmem file ended before specified final address (IEEE 2017 21.4)"); } return false; // EOF @@ -1969,7 +1997,7 @@ VlWriteMem::~VlWriteMem() { void VlWriteMem::print(QData addr, bool addrstamp, const void* valuep) { if (VL_UNLIKELY(!m_fp)) return; if (addr != m_addr && addrstamp) { // Only assoc has time stamps - fprintf(m_fp, "@%" VL_PRI64 "x\n", addr); + fprintf(m_fp, "@%" PRIx64 "\n", addr); } m_addr = addr + 1; if (m_bits <= 8) { @@ -2625,14 +2653,11 @@ void Verilated::debug(int level) VL_MT_SAFE { } } -const char* Verilated::catName(const char* n1, const char* n2, int scopet, - const char* delimiter) VL_MT_SAFE { - // Returns new'ed data +const char* Verilated::catName(const char* n1, const char* n2, const char* delimiter) VL_MT_SAFE { // Used by symbol table creation to make module names static VL_THREAD_LOCAL char* t_strp = nullptr; static VL_THREAD_LOCAL size_t t_len = 0; - const size_t newlen - = std::strlen(n1) + std::strlen(n2) + std::strlen(delimiter) + (scopet > 0 ? 2 : 1); + const size_t newlen = std::strlen(n1) + std::strlen(n2) + std::strlen(delimiter) + 1; if (VL_UNLIKELY(!t_strp || newlen > t_len)) { if (t_strp) delete[] t_strp; t_strp = new char[newlen]; @@ -2640,8 +2665,6 @@ const char* Verilated::catName(const char* n1, const char* n2, int scopet, } char* dp = t_strp; for (const char* sp = n1; *sp;) *dp++ = *sp++; - // Add scope type - if (scopet) *dp++ = (char)(0x80 + scopet); for (const char* sp = delimiter; *sp;) *dp++ = *sp++; for (const char* sp = n2; *sp;) *dp++ = *sp++; *dp++ = '\0'; diff --git a/include/verilated.h b/include/verilated.h index 8e502fd08..368be6bcc 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,6 +33,7 @@ // clang-format off #include "verilatedos.h" +#include "verilated_config.h" #if VM_SC # include "verilated_sc.h" // Get SYSTEMC_VERSION and time declarations #endif @@ -86,6 +87,7 @@ class VerilatedCovContext; class VerilatedEvalMsgQueue; class VerilatedFst; class VerilatedFstC; +class VerilatedFstSc; class VerilatedScope; class VerilatedScopeNameMap; class VerilatedVar; @@ -823,8 +825,8 @@ public: public: // METHODS - INTERNAL USE ONLY (but public due to what uses it) // Internal: Create a new module name by concatenating two strings - static const char* catName(const char* n1, const char* n2, int scopet = 0, - const char* delimiter = "."); // Returns static data + // Returns pointer to thread-local static data (overwritten on next call) + static const char* catName(const char* n1, const char* n2, const char* delimiter = "."); // Internal: Throw signal assertion static void nullPointerError(const char* filename, int linenum) VL_ATTR_NORETURN VL_MT_SAFE; diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 150196d0f..99fd533c2 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -2,7 +2,7 @@ ###################################################################### # DESCRIPTION: Makefile commands for all verilated target files # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -223,7 +223,9 @@ endif $(info Archive $(AR) -rcs $@ $^) $(foreach L, $(filter-out %.a,$^), $(shell echo $L >>$@.verilator_deplist.tmp)) @if test $(words $(filter %.a,$^)) -eq 0; then \ - $(AR) -rcs $@ @$@.verilator_deplist.tmp; \ + $(RM) -f $@; \ + cat $@.verilator_deplist.tmp | xargs $(AR) -rc $@; \ + $(AR) -s $@; \ else \ $(RM) -rf $@.tmpdir; \ for archive in $(filter %.a,$^); do \ @@ -232,7 +234,9 @@ endif $(AR) -x ../../$${archive}; \ cd ../..; \ done; \ - $(AR) -rcs $@ @$@.verilator_deplist.tmp $@.tmpdir/*/*.o; \ + $(RM) -f $@; \ + cat $@.verilator_deplist.tmp | xargs $(AR) -rc $@; \ + $(AR) -rcs $@ $@.tmpdir/*/*.o; \ fi \ ; $(RM) -rf $@.verilator_deplist.tmp $@.tmpdir diff --git a/include/verilated.v b/include/verilated.v index bfd98d29a..9de7d615c 100644 --- a/include/verilated.v +++ b/include/verilated.v @@ -2,7 +2,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_config.h.in b/include/verilated_config.h.in index 953332221..d64a0b9eb 100644 --- a/include/verilated_config.h.in +++ b/include/verilated_config.h.in @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,6 +20,11 @@ // Autoconf substitutes this with the strings from AC_INIT. #define VERILATOR_PRODUCT "@PACKAGE_NAME@" -/// Verilator version name, e.g. "1.000 2000-01-01" +/// Verilator version name, e.g. "1.002 2000-01-01" // Autoconf substitutes this with the strings from AC_INIT. #define VERILATOR_VERSION "@PACKAGE_VERSION@" + +/// Verilator version number as integer +/// As major * 100000 + minor * 1000, e.g. 1002000 == 1.002 +// Autoconf substitutes this with the strings from AC_INIT. +#define VERILATOR_VERSION_INTEGER @VERILATOR_VERSION_INTEGER@ diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index d52ecc8f8..6a1fcf69a 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -29,6 +29,7 @@ #include #include #include +#include //============================================================================= // VerilatedCovConst @@ -231,7 +232,7 @@ private: // Little selftest #define SELF_CHECK(got, exp) \ do { \ - if ((got) != (exp)) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: selftest\n"); \ + if ((got) != (exp)) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: selftest"); \ } while (0) SELF_CHECK(combineHier("a.b.c", "a.b.c"), "a.b.c"); SELF_CHECK(combineHier("a.b.c", "a.b"), "a.b*"); @@ -358,7 +359,7 @@ public: Verilated::quiesce(); const VerilatedLockGuard lock{m_mutex}; #ifndef VM_COVERAGE - VL_FATAL_MT("", 0, "", "%Error: Called VerilatedCov::write when VM_COVERAGE disabled\n"); + VL_FATAL_MT("", 0, "", "%Error: Called VerilatedCov::write when VM_COVERAGE disabled"); #endif selftest(); diff --git a/include/verilated_cov.h b/include/verilated_cov.h index 3217163c1..30ca063c6 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_cov_key.h b/include/verilated_cov_key.h index 7bf8339a9..ee7ed06a9 100644 --- a/include/verilated_cov_key.h +++ b/include/verilated_cov_key.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index 429838cb3..eb152b7d4 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_dpi.h b/include/verilated_dpi.h index c1638f5d1..f37679f91 100644 --- a/include/verilated_dpi.h +++ b/include/verilated_dpi.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 73275f9c7..365834b88 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -122,7 +122,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) { // convert m_code2symbol into an array for fast lookup if (!m_symbolp) { - m_symbolp = new fstHandle[nextCode()]; + m_symbolp = new fstHandle[nextCode()]{0}; for (const auto& i : m_code2symbol) m_symbolp[i.first] = i.second; } m_code2symbol.clear(); @@ -158,18 +158,20 @@ void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, vluint32_t elem } void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, - fstVarType vartype, bool array, int arraynum, int msb, int lsb) { + fstVarType vartype, bool array, int arraynum, bool bussed, int msb, + int lsb) { const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; - VerilatedTrace::declCode(code, bits, false); + const bool enabled = VerilatedTrace::declCode(code, name, bits, false); + if (!enabled) return; - std::istringstream nameiss{name}; + std::string nameasstr = namePrefix() + name; + std::istringstream nameiss{nameasstr}; std::istream_iterator beg(nameiss); std::istream_iterator end; std::list tokens(beg, end); // Split name std::string symbol_name{tokens.back()}; tokens.pop_back(); // Remove symbol name from hierarchy - tokens.insert(tokens.begin(), moduleName()); // Add current module to the hierarchy std::string tmpModName; // Find point where current and new scope diverge @@ -195,9 +197,9 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV // If the scope ends with a non-ascii character, it will be 0x80 + fstScopeType fstWriterSetScope(m_fst, static_cast(new_it->back() & 0x7f), tmpModName.c_str(), nullptr); - } else + } else { fstWriterSetScope(m_fst, FST_ST_VCD_SCOPE, new_it->c_str(), nullptr); - + } m_curScope.push_back(*new_it); new_it = tokens.erase(new_it); } @@ -205,6 +207,7 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV std::stringstream name_ss; name_ss << symbol_name; if (array) name_ss << "[" << arraynum << "]"; + if (bussed) name_ss << " [" << msb << ":" << lsb << "]"; std::string name_str = name_ss.str(); if (dtypenum > 0) { @@ -223,23 +226,23 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV void VerilatedFst::declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum) { - declare(code, name, dtypenum, vardir, vartype, array, arraynum, 0, 0); + declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 0, 0); } void VerilatedFst::declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { - declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb); + declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb); } void VerilatedFst::declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { - declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb); + declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb); } void VerilatedFst::declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { - declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb); + declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb); } void VerilatedFst::declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum) { - declare(code, name, dtypenum, vardir, vartype, array, arraynum, 63, 0); + declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 63, 0); } // Note: emit* are only ever called from one place (full* in @@ -248,12 +251,14 @@ void VerilatedFst::declDouble(vluint32_t code, const char* name, int dtypenum, f VL_ATTR_ALWINLINE void VerilatedFst::emitBit(vluint32_t code, CData newval) { + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); fstWriterEmitValueChange(m_fst, m_symbolp[code], newval ? "1" : "0"); } VL_ATTR_ALWINLINE void VerilatedFst::emitCData(vluint32_t code, CData newval, int bits) { char buf[VL_BYTESIZE]; + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); cvtCDataToStr(buf, newval << (VL_BYTESIZE - bits)); fstWriterEmitValueChange(m_fst, m_symbolp[code], buf); } @@ -261,6 +266,7 @@ void VerilatedFst::emitCData(vluint32_t code, CData newval, int bits) { VL_ATTR_ALWINLINE void VerilatedFst::emitSData(vluint32_t code, SData newval, int bits) { char buf[VL_SHORTSIZE]; + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); cvtSDataToStr(buf, newval << (VL_SHORTSIZE - bits)); fstWriterEmitValueChange(m_fst, m_symbolp[code], buf); } @@ -268,6 +274,7 @@ void VerilatedFst::emitSData(vluint32_t code, SData newval, int bits) { VL_ATTR_ALWINLINE void VerilatedFst::emitIData(vluint32_t code, IData newval, int bits) { char buf[VL_IDATASIZE]; + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); cvtIDataToStr(buf, newval << (VL_IDATASIZE - bits)); fstWriterEmitValueChange(m_fst, m_symbolp[code], buf); } @@ -275,6 +282,7 @@ void VerilatedFst::emitIData(vluint32_t code, IData newval, int bits) { VL_ATTR_ALWINLINE void VerilatedFst::emitQData(vluint32_t code, QData newval, int bits) { char buf[VL_QUADSIZE]; + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); cvtQDataToStr(buf, newval << (VL_QUADSIZE - bits)); fstWriterEmitValueChange(m_fst, m_symbolp[code], buf); } diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 2426a3e5a..3e48daf92 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -54,7 +54,7 @@ private: // CONSTRUCTORS VL_UNCOPYABLE(VerilatedFst); void declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, - fstVarType vartype, bool array, int arraynum, int msb, int lsb); + fstVarType vartype, bool array, int arraynum, bool bussed, int msb, int lsb); protected: //========================================================================= @@ -121,6 +121,7 @@ template <> void VerilatedTrace::set_time_unit(const char* unitp); template <> void VerilatedTrace::set_time_unit(const std::string& unit); template <> void VerilatedTrace::set_time_resolution(const char* unitp); template <> void VerilatedTrace::set_time_resolution(const std::string& unit); +template <> void VerilatedTrace::dumpvars(int level, const std::string& hier); #endif //============================================================================= @@ -139,7 +140,7 @@ public: explicit VerilatedFstC(void* filep = nullptr) : m_sptrace{filep} {} /// Destruct, flush, and close the dump - ~VerilatedFstC() { close(); } + virtual ~VerilatedFstC() { close(); } // METHODS - User called @@ -178,9 +179,14 @@ public: void set_time_resolution(const std::string& unit) VL_MT_SAFE { m_sptrace.set_time_resolution(unit); } + // Set variables to dump, using $dumpvars format + // If level = 0, dump everything and hier is then ignored + void dumpvars(int level, const std::string& hier) VL_MT_SAFE { + m_sptrace.dumpvars(level, hier); + } // Internal class access - inline VerilatedFst* spTrace() { return &m_sptrace; }; + inline VerilatedFst* spTrace() { return &m_sptrace; } }; #endif // guard diff --git a/include/verilated_fst_sc.cpp b/include/verilated_fst_sc.cpp index 4f14fffdb..fc6693a87 100644 --- a/include/verilated_fst_sc.cpp +++ b/include/verilated_fst_sc.cpp @@ -3,7 +3,7 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -27,6 +27,17 @@ //====================================================================== //====================================================================== +void VerilatedFstSc::open(const char* filename) { + if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) { + vl_fatal(__FILE__, __LINE__, "VerilatedFstSc", + ("%Error: VerilatedFstSc::open(\"" + std::string(filename) + + "\") is called before sc_core::sc_start(). " + "Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before opening a wave file.") + .c_str()); + } + VerilatedFstC::open(filename); +} + //-------------------------------------------------- // SystemC 2.1.v1 // cppcheck-suppress unusedFunction diff --git a/include/verilated_fst_sc.h b/include/verilated_fst_sc.h index c9ad874d7..e0958db9e 100644 --- a/include/verilated_fst_sc.h +++ b/include/verilated_fst_sc.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -26,6 +26,8 @@ #include "verilated_sc.h" #include "verilated_fst_c.h" +#include + //============================================================================= // VerilatedFstSc /// @@ -57,6 +59,9 @@ public: if (!delta_cycle) { this->dump(sc_time_stamp().to_double()); } } + // Override VerilatedFstC. Must be called after starting simulation. + virtual void open(const char* filename) /*override*/ VL_MT_SAFE; + private: /// Fake outs for linker diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index bd1369421..988b5d807 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -28,6 +28,8 @@ #error "verilated_funcs.h should only be included by verilated.h" #endif +#include + //========================================================================= // Extern functions -- User may override -- See verilated.cpp @@ -43,12 +45,17 @@ extern void vl_finish(const char* filename, int linenum, const char* hier); /// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this. extern void vl_stop(const char* filename, int linenum, const char* hier); -/// Routine to call for a couple of fatal messages +/// Routine to call for fatal messages /// User code may wish to replace this function, to do so, define VL_USER_FATAL. /// This code does not have to be thread safe. /// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this. extern void vl_fatal(const char* filename, int linenum, const char* hier, const char* msg); +/// Routine to call for warning messages +/// User code may wish to replace this function, to do so, define VL_USER_WARN. +/// This code does not have to be thread safe. +extern void vl_warn(const char* filename, int linenum, const char* hier, const char* msg); + //========================================================================= // Extern functions -- Slow path @@ -57,9 +64,12 @@ extern void VL_FINISH_MT(const char* filename, int linenum, const char* hier) VL /// Multithread safe wrapper for calls to $stop extern void VL_STOP_MT(const char* filename, int linenum, const char* hier, bool maybe = true) VL_MT_SAFE; -/// Multithread safe wrapper to call for a couple of fatal messages +/// Multithread safe wrapper to call for fatal messages extern void VL_FATAL_MT(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_SAFE; +/// Multithread safe wrapper to call for warning messages +extern void VL_WARN_MT(const char* filename, int linenum, const char* hier, + const char* msg) VL_MT_SAFE; // clang-format off /// Print a string, multithread safe. Eventually VL_PRINTF will get called. @@ -77,7 +87,8 @@ extern void VL_DBG_MSGF(const char* formatp, ...) VL_ATTR_PRINTF(1) VL_MT_SAFE; inline IData VL_RANDOM_I() VL_MT_SAFE { return vl_rand64(); } inline QData VL_RANDOM_Q() VL_MT_SAFE { return vl_rand64(); } extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp); -extern IData VL_RANDOM_SEEDED_II(IData seed) VL_MT_SAFE; +extern IData VL_RANDOM_SEEDED_II(IData& seedr) VL_MT_SAFE; +extern IData VL_URANDOM_SEEDED_II(IData seed) VL_MT_SAFE; inline IData VL_URANDOM_RANGE_I(IData hi, IData lo) { const vluint64_t rnd = vl_rand64(); if (VL_LIKELY(hi > lo)) { @@ -151,10 +162,6 @@ extern const char* vl_mc_scan_plusargs(const char* prefixp); // PLIish // Base macros // Return true if data[bit] set; not 0/1 return, but 0/non-zero return. -#define VL_BITISSET_I(data, bit) ((data) & (VL_UL(1) << VL_BITBIT_I(bit))) -#define VL_BITISSET_Q(data, bit) ((data) & (1ULL << VL_BITBIT_Q(bit))) -#define VL_BITISSET_E(data, bit) ((data) & (VL_EUL(1) << VL_BITBIT_E(bit))) -#define VL_BITISSET_W(data, bit) ((data)[VL_BITWORD_E(bit)] & (VL_EUL(1) << VL_BITBIT_E(bit))) #define VL_BITISSETLIMIT_W(data, width, bit) (((bit) < (width)) && VL_BITISSET_W(data, bit)) // Shift appropriate word by bit. Does not account for wrapping between two words @@ -332,13 +339,19 @@ double vl_time_multiplier(int scale) VL_PURE; vluint64_t vl_time_pow10(int n) VL_PURE; #ifdef VL_DEBUG -/// Evaluate statement if Verilated::debug() enabled +/// Evaluate statement if VL_DEBUG defined +# define VL_DEBUG_IFDEF(stmt) \ + do { \ + stmt \ + } while (false) +/// Evaluate statement if VL_DEBUG defined and Verilated::debug() enabled # define VL_DEBUG_IF(stmt) \ do { \ if (VL_UNLIKELY(Verilated::debug())) {stmt} \ } while (false) #else // We intentionally do not compile the stmt to improve compile speed +# define VL_DEBUG_IFDEF(stmt) do {} while (false) # define VL_DEBUG_IF(stmt) do {} while (false) #endif @@ -1430,7 +1443,7 @@ static inline QData VL_STREAML_FAST_QQI(int lbits, QData ld, IData rd_log2) VL_P if (rd_log2) { const vluint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); const vluint32_t lbitsRem = lbits - lbitsFloor; - const QData msbMask = VL_MASK_Q(lbitsRem) << lbitsFloor; + const QData msbMask = lbitsFloor == 64 ? 0ULL : VL_MASK_Q(lbitsRem) << lbitsFloor; ret = (ret & ~msbMask) | ((ret & msbMask) << ((1ULL << rd_log2) - lbitsRem)); } switch (rd_log2) { @@ -1781,7 +1794,7 @@ static inline WDataOutP VL_SHIFTRS_WWW(int obits, int lbits, int rbits, WDataOut WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { EData overshift = 0; // Huge shift 1>>32 or more for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; - if (VL_UNLIKELY(overshift || rwp[0] >= obits)) { + if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { const int lmsw = VL_WORDS_I(obits) - 1; const EData sign = VL_SIGNONES_E(lbits, lwp[lmsw]); for (int j = 0; j <= lmsw; ++j) owp[j] = sign; @@ -1800,7 +1813,7 @@ static inline IData VL_SHIFTRS_IIW(int obits, int lbits, int rbits, IData lhs, WDataInP const rwp) VL_MT_SAFE { EData overshift = 0; // Huge shift 1>>32 or more for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; - if (VL_UNLIKELY(overshift || rwp[0] >= obits)) { + if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { const IData sign = -(lhs >> (lbits - 1)); // ffff_ffff if negative return VL_CLEAN_II(obits, obits, sign); } @@ -1810,7 +1823,7 @@ static inline QData VL_SHIFTRS_QQW(int obits, int lbits, int rbits, QData lhs, WDataInP const rwp) VL_MT_SAFE { EData overshift = 0; // Huge shift 1>>32 or more for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; - if (VL_UNLIKELY(overshift || rwp[0] >= obits)) { + if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { const QData sign = -(lhs >> (lbits - 1)); // ffff_ffff if negative return VL_CLEAN_QQ(obits, obits, sign); } @@ -1962,42 +1975,33 @@ static inline WDataOutP VL_RTOIROUND_W_D(int obits, WDataOutP owp, double lhs) V // Range assignments // EMIT_RULE: VL_ASSIGNRANGE: rclean=dirty; -static inline void VL_ASSIGNSEL_IIII(int rbits, int obits, int lsb, CData& lhsr, - IData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_II(int rbits, int obits, int lsb, CData& lhsr, IData rhs) VL_PURE { _vl_insert_II(lhsr, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_IIII(int rbits, int obits, int lsb, SData& lhsr, - IData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_II(int rbits, int obits, int lsb, SData& lhsr, IData rhs) VL_PURE { _vl_insert_II(lhsr, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_IIII(int rbits, int obits, int lsb, IData& lhsr, - IData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_II(int rbits, int obits, int lsb, IData& lhsr, IData rhs) VL_PURE { _vl_insert_II(lhsr, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_QIII(int rbits, int obits, int lsb, QData& lhsr, - IData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_QI(int rbits, int obits, int lsb, QData& lhsr, IData rhs) VL_PURE { _vl_insert_QQ(lhsr, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_QQII(int rbits, int obits, int lsb, QData& lhsr, - QData rhs) VL_PURE { - _vl_insert_QQ(lhsr, rhs, lsb + obits - 1, lsb, rbits); -} -static inline void VL_ASSIGNSEL_QIIQ(int rbits, int obits, int lsb, QData& lhsr, - QData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_QQ(int rbits, int obits, int lsb, QData& lhsr, QData rhs) VL_PURE { _vl_insert_QQ(lhsr, rhs, lsb + obits - 1, lsb, rbits); } // static inline void VL_ASSIGNSEL_IIIW(int obits, int lsb, IData& lhsr, WDataInP const rwp) // VL_MT_SAFE { Illegal, as lhs width >= rhs width -static inline void VL_ASSIGNSEL_WIII(int rbits, int obits, int lsb, WDataOutP owp, - IData rhs) VL_MT_SAFE { +static inline void VL_ASSIGNSEL_WI(int rbits, int obits, int lsb, WDataOutP owp, + IData rhs) VL_MT_SAFE { _vl_insert_WI(owp, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_WIIQ(int rbits, int obits, int lsb, WDataOutP owp, - QData rhs) VL_MT_SAFE { +static inline void VL_ASSIGNSEL_WQ(int rbits, int obits, int lsb, WDataOutP owp, + QData rhs) VL_MT_SAFE { _vl_insert_WQ(owp, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_WIIW(int rbits, int obits, int lsb, WDataOutP owp, - WDataInP const rwp) VL_MT_SAFE { +static inline void VL_ASSIGNSEL_WW(int rbits, int obits, int lsb, WDataOutP owp, + WDataInP const rwp) VL_MT_SAFE { _vl_insert_WW(owp, rwp, lsb + obits - 1, lsb, rbits); } @@ -2036,40 +2040,40 @@ static inline WDataOutP VL_CONST_W_2X(int obits, WDataOutP o, EData d1, EData d0 static inline WDataOutP VL_CONST_W_3X(int obits, WDataOutP o, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; - VL_C_END_(obits,3); + VL_C_END_(obits, 3); } static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; - VL_C_END_(obits,4); + VL_C_END_(obits, 4); } static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; - VL_C_END_(obits,5); + VL_C_END_(obits, 5); } static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; - VL_C_END_(obits,6); + VL_C_END_(obits, 6); } static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o, EData d6, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; o[6] = d6; - VL_C_END_(obits,7); + VL_C_END_(obits, 7); } static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o, EData d7, EData d6, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; o[6] = d6; o[7] = d7; - VL_C_END_(obits,8); + VL_C_END_(obits, 8); } // static inline WDataOutP VL_CONSTHI_W_1X(int obits, int lsb, WDataOutP obase, diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index 80129772f..e4acd8142 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2010-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2010-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_imp.h b/include/verilated_imp.h index f612c55f5..7f07587db 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,10 +32,14 @@ #include "verilated.h" #include "verilated_syms.h" +#include #include -#include -#include +#include #include +#include +#include +#include +#include #ifdef VL_THREADED # include # include @@ -312,14 +316,14 @@ public: // But only for verilated*.cpp IData fdSeek(IData fdi, IData offset, IData origin) VL_MT_SAFE_EXCLUDES(m_fdMutex) { const VerilatedLockGuard lock{m_fdMutex}; const VerilatedFpList fdlist = fdToFpList(fdi); - if (VL_UNLIKELY(fdlist.size() != 1)) return 0; + if (VL_UNLIKELY(fdlist.size() != 1)) return ~0U; // -1 return static_cast( std::fseek(*fdlist.begin(), static_cast(offset), static_cast(origin))); } IData fdTell(IData fdi) VL_MT_SAFE_EXCLUDES(m_fdMutex) { const VerilatedLockGuard lock{m_fdMutex}; const VerilatedFpList fdlist = fdToFpList(fdi); - if (VL_UNLIKELY(fdlist.size() != 1)) return 0; + if (VL_UNLIKELY(fdlist.size() != 1)) return ~0U; // -1 return static_cast(std::ftell(*fdlist.begin())); } void fdWrite(IData fdi, const std::string& output) VL_MT_SAFE_EXCLUDES(m_fdMutex) { diff --git a/include/verilated_intrinsics.h b/include/verilated_intrinsics.h index 6c4dd0e70..51e916223 100644 --- a/include/verilated_intrinsics.h +++ b/include/verilated_intrinsics.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_profiler.h b/include/verilated_profiler.h index 9895b6062..46df1c249 100644 --- a/include/verilated_profiler.h +++ b/include/verilated_profiler.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2021 by Wilson Snyder. This program is free software; you +// Copyright 2012-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -25,6 +25,9 @@ #include "verilatedos.h" #include "verilated.h" // for VerilatedMutex and clang annotations +#include +#include + // Profile record, private class used only by this header class VerilatedProfilerRec final { const std::string m_name; // Hashed name of mtask/etc @@ -103,7 +106,7 @@ void VerilatedProfiler::write(const char* modelp, for (const auto& it : m_records) { const std::string& name = it.name(); - fprintf(fp, "profile_data -model \"%s\" -mtask \"%s\" -cost 64'd%" VL_PRI64 "u\n", modelp, + fprintf(fp, "profile_data -model \"%s\" -mtask \"%s\" -cost 64'd%" PRIu64 "\n", modelp, name.c_str(), m_counters[it.counterNumber()]); } diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index 0c2d2e3c2..e63bc0d28 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_save.h b/include/verilated_save.h index 8f95a85b9..f78da143a 100644 --- a/include/verilated_save.h +++ b/include/verilated_save.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2000-2021 by Wilson Snyder. This program is free software; you +// Copyright 2000-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_sc.h b/include/verilated_sc.h index 649b388ed..aadccedf8 100644 --- a/include/verilated_sc.h +++ b/include/verilated_sc.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_sym_props.h b/include/verilated_sym_props.h index 990b4564d..362afdfaf 100644 --- a/include/verilated_sym_props.h +++ b/include/verilated_sym_props.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_syms.h b/include/verilated_syms.h index 160bd31c9..72243c268 100644 --- a/include/verilated_syms.h +++ b/include/verilated_syms.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index edfa8891b..6051b8967 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2012-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -26,6 +26,8 @@ #include #include +#include +#include //============================================================================= // Globals @@ -161,12 +163,12 @@ void VlThreadPool::profileDump(const char* filenamep, vluint64_t tickStart, vlui // TODO Perhaps merge with verilated_coverage output format, so can // have a common merging and reporting tool, etc. fprintf(fp, "VLPROFTHREAD 1.1 # Verilator thread profile dump version 1.1\n"); - fprintf(fp, "VLPROF arg --threads %" VL_PRI64 "u\n", vluint64_t(m_workers.size() + 1)); - fprintf(fp, "VLPROF arg +verilator+prof+threads+start+%" VL_PRI64 "u\n", + fprintf(fp, "VLPROF arg --threads %" PRIu64 "\n", vluint64_t(m_workers.size() + 1)); + fprintf(fp, "VLPROF arg +verilator+prof+threads+start+%" PRIu64 "\n", Verilated::threadContextp()->profThreadsStart()); fprintf(fp, "VLPROF arg +verilator+prof+threads+window+%u\n", Verilated::threadContextp()->profThreadsWindow()); - fprintf(fp, "VLPROF stat yields %" VL_PRI64 "u\n", VlMTaskVertex::yields()); + fprintf(fp, "VLPROF stat yields %" PRIu64 "\n", VlMTaskVertex::yields()); // Copy /proc/cpuinfo into this output so verilator_gantt can be run on // a different machine @@ -191,15 +193,14 @@ void VlThreadPool::profileDump(const char* filenamep, vluint64_t tickStart, vlui case VlProfileRec::TYPE_EVAL: if (!printing) break; fprintf(fp, - "VLPROF eval start %" VL_PRI64 "u elapsed %" VL_PRI64 "u" - " cpu %u on thread %u\n", + "VLPROF eval start %" PRIu64 " elapsed %" PRIu64 " cpu %u on thread %u\n", ei.m_startTime - tickStart, (ei.m_endTime - ei.m_startTime), ei.m_cpu, thread_id); break; case VlProfileRec::TYPE_EVAL_LOOP: if (!printing) break; fprintf(fp, - "VLPROF eval_loop start %" VL_PRI64 "u elapsed %" VL_PRI64 "u" + "VLPROF eval_loop start %" PRIu64 " elapsed %" PRIu64 " cpu %u on thread %u\n", ei.m_startTime - tickStart, (ei.m_endTime - ei.m_startTime), ei.m_cpu, thread_id); @@ -208,7 +209,7 @@ void VlThreadPool::profileDump(const char* filenamep, vluint64_t tickStart, vlui if (!printing) break; fprintf(fp, "VLPROF mtask %d" - " start %" VL_PRI64 "u elapsed %" VL_PRI64 "u" + " start %" PRIu64 " elapsed %" PRIu64 " predict_start %u predict_cost %u cpu %u on thread %u\n", ei.m_mtaskId, ei.m_startTime - tickStart, (ei.m_endTime - ei.m_startTime), ei.m_predictStart, ei.m_predictCost, ei.m_cpu, thread_id); @@ -217,7 +218,7 @@ void VlThreadPool::profileDump(const char* filenamep, vluint64_t tickStart, vlui } } } - fprintf(fp, "VLPROF stat ticks %" VL_PRI64 "u\n", tickEnd - tickStart); + fprintf(fp, "VLPROF stat ticks %" PRIu64 "\n", tickEnd - tickStart); std::fclose(fp); } diff --git a/include/verilated_threads.h b/include/verilated_threads.h index c3af2f681..ffaf02e98 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2021 by Wilson Snyder. This program is free software; you +// Copyright 2012-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -43,7 +43,7 @@ #if defined(__linux) # include // For sched_getcpu() #endif -#if defined(__APPLE__) +#if defined(__APPLE__) && !defined(__arm64__) # include // For __cpuid_count() #endif // clang-format on @@ -168,7 +168,7 @@ public: static int getcpu() { // Return current executing CPU #if defined(__linux) return sched_getcpu(); -#elif defined(__APPLE__) +#elif defined(__APPLE__) && !defined(__arm64__) vluint32_t info[4]; __cpuid_count(1, 0, info[0], info[1], info[2], info[3]); // info[1] is EBX, bits 24-31 are APIC ID diff --git a/include/verilated_trace.h b/include/verilated_trace.h index 6e7d6c59e..6caeb5d03 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -27,6 +27,8 @@ #include "verilated.h" #include "verilated_trace_defs.h" +#include +#include #include #include @@ -141,7 +143,9 @@ private: }; vluint32_t* m_sigs_oldvalp; // Old value store + EData* m_sigs_enabledp; // Bit vector of enabled codes (nullptr = all on) vluint64_t m_timeLastDump; // Last time we did a dump + std::vector m_sigs_enabledVec; // Staging for m_sigs_enabledp std::vector m_initCbs; // Routines to initialize traciong std::vector m_fullCbs; // Routines to perform full dump std::vector m_chgCbs; // Routines to perform incremental dump @@ -150,7 +154,8 @@ private: vluint32_t m_nextCode; // Next code number to assign vluint32_t m_numSignals; // Number of distinct signals vluint32_t m_maxBits; // Number of bits in the widest signal - std::string m_moduleName; // Name of module being trace initialized now + std::vector m_namePrefixStack{""}; // Path prefixes to add to signal names + std::vector> m_dumpvars; // dumpvar() entries char m_scopeEscape; double m_timeRes; // Time resolution (ns/ms etc) double m_timeUnit; // Time units (ns/ms etc) @@ -170,27 +175,22 @@ private: #ifdef VL_TRACE_THREADED // Number of total trace buffers that have been allocated vluint32_t m_numTraceBuffers; - // Size of trace buffers size_t m_traceBufferSize; - // Buffers handed to worker for processing VerilatedThreadQueue m_buffersToWorker; // Buffers returned from worker after processing VerilatedThreadQueue m_buffersFromWorker; + // Write pointer into current buffer + vluint32_t* m_traceBufferWritep; + // End of trace buffer + vluint32_t* m_traceBufferEndp; + // The worker thread itself + std::unique_ptr m_workerThread; // Get a new trace buffer that can be populated. May block if none available vluint32_t* getTraceBuffer(); - // Write pointer into current buffer - vluint32_t* m_traceBufferWritep; - - // End of trace buffer - vluint32_t* m_traceBufferEndp; - - // The worker thread itself - std::unique_ptr m_workerThread; - // The function executed by the worker thread void workerThreadMain(); @@ -213,7 +213,6 @@ protected: vluint32_t nextCode() const { return m_nextCode; } vluint32_t numSignals() const { return m_numSignals; } vluint32_t maxBits() const { return m_maxBits; } - const std::string& moduleName() const { return m_moduleName; } void fullDump(bool value) { m_fullDump = value; } vluint64_t timeLastDump() { return m_timeLastDump; } @@ -223,12 +222,15 @@ protected: void traceInit() VL_MT_UNSAFE; - void declCode(vluint32_t code, vluint32_t bits, bool tri); + // Declare new signal and return true if enabled + bool declCode(vluint32_t code, const char* namep, vluint32_t bits, bool tri); // Is this an escape? bool isScopeEscape(char c) { return std::isspace(c) || c == m_scopeEscape; } // Character that splits scopes. Note whitespace are ALWAYS escapes. char scopeEscape() { return m_scopeEscape; } + // Prefix to assume in signal declarations + const std::string& namePrefix() const { return m_namePrefixStack.back(); } void closeBase(); void flushBase(); @@ -257,6 +259,9 @@ public: // Set time resolution (s/ms, defaults to ns) void set_time_resolution(const char* unitp) VL_MT_SAFE; void set_time_resolution(const std::string& unit) VL_MT_SAFE; + // Set variables to dump, using $dumpvars format + // If level = 0, dump everything and hier is then ignored + void dumpvars(int level, const std::string& hier) VL_MT_SAFE; // Call void dump(vluint64_t timeui) VL_MT_SAFE_EXCLUDES(m_mutex); @@ -269,9 +274,11 @@ public: void addChgCb(dumpCb_t cb, void* userp) VL_MT_SAFE; void addCleanupCb(dumpCb_t cb, void* userp) VL_MT_SAFE; - void module(const std::string& name) VL_MT_UNSAFE; void scopeEscape(char flag) { m_scopeEscape = flag; } + void pushNamePrefix(const std::string&); + void popNamePrefix(unsigned count = 1); + //========================================================================= // Hot path internal interface to Verilator generated code diff --git a/include/verilated_trace_defs.h b/include/verilated_trace_defs.h index 69290c148..0ff900ee7 100644 --- a/include/verilated_trace_defs.h +++ b/include/verilated_trace_defs.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_trace_imp.cpp b/include/verilated_trace_imp.cpp index 84225ed98..26e0bf63a 100644 --- a/include/verilated_trace_imp.cpp +++ b/include/verilated_trace_imp.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -282,6 +282,7 @@ template <> void VerilatedTrace::onExit(void* selfp) { template <> VerilatedTrace::VerilatedTrace() : m_sigs_oldvalp{nullptr} + , m_sigs_enabledp{nullptr} , m_timeLastDump{0} , m_fullDump{true} , m_nextCode{0} @@ -302,6 +303,7 @@ VerilatedTrace::VerilatedTrace() template <> VerilatedTrace::~VerilatedTrace() { if (m_sigs_oldvalp) VL_DO_CLEAR(delete[] m_sigs_oldvalp, m_sigs_oldvalp = nullptr); + if (m_sigs_enabledp) VL_DO_CLEAR(delete[] m_sigs_enabledp, m_sigs_enabledp = nullptr); Verilated::removeFlushCb(VerilatedTrace::onFlush, this); Verilated::removeExitCb(VerilatedTrace::onExit, this); #ifdef VL_TRACE_THREADED @@ -320,9 +322,10 @@ template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { m_nextCode = 1; m_numSignals = 0; m_maxBits = 0; + m_sigs_enabledVec.clear(); // Call all initialize callbacks, which will: - // - Call decl* for each signal + // - Call decl* for each signal (these eventually call ::declCode) // - Store the base code for (vluint32_t i = 0; i < m_initCbs.size(); ++i) { const CallbackRecord& cbr = m_initCbs[i]; @@ -338,6 +341,23 @@ template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { // holding previous signal values. if (!m_sigs_oldvalp) m_sigs_oldvalp = new vluint32_t[nextCode()]; + // Apply enables + if (m_sigs_enabledp) VL_DO_CLEAR(delete[] m_sigs_enabledp, m_sigs_enabledp = nullptr); + if (!m_sigs_enabledVec.empty()) { + // Else if was empty, m_sigs_enabledp = nullptr to short circuit tests + // But it isn't, so alloc one bit for each code to indicate enablement + // We don't want to still use m_signs_enabledVec as std::vector is not + // guarenteed to be fast + m_sigs_enabledp = new vluint32_t[1 + VL_WORDS_I(nextCode())]{0}; + m_sigs_enabledVec.reserve(nextCode()); + for (size_t code = 0; code < nextCode(); ++code) { + if (m_sigs_enabledVec[code]) { + m_sigs_enabledp[VL_BITWORD_I(code)] |= 1U << VL_BITBIT_I(code); + } + } + m_sigs_enabledVec.clear(); + } + // Set callback so flush/abort will flush this file Verilated::addFlushCb(VerilatedTrace::onFlush, this); Verilated::addExitCb(VerilatedTrace::onExit, this); @@ -356,10 +376,38 @@ template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { } template <> -void VerilatedTrace::declCode(vluint32_t code, vluint32_t bits, bool tri) { +bool VerilatedTrace::declCode(vluint32_t code, const char* namep, vluint32_t bits, + bool tri) { if (VL_UNCOVERABLE(!code)) { VL_FATAL_MT(__FILE__, __LINE__, "", "Internal: internal trace problem, code 0 is illegal"); } + // To keep it simple, this is O(enables * signals), but we expect few enables + std::string declName = namePrefix() + namep; + bool enabled = false; + if (m_dumpvars.empty()) enabled = true; + for (const auto& item : m_dumpvars) { + const int dumpvarsLevel = item.first; + const char* dvp = item.second.c_str(); + const char* np = declName.c_str(); + while (*dvp && *dvp == *np) { + ++dvp; + ++np; + } + if (*dvp) continue; // Didn't match dumpvar item + if (*np && *np != ' ') continue; // e.g. "t" isn't a match for "top" + int levels = 0; + while (*np) { + if (*np++ == ' ') ++levels; + } + if (levels > dumpvarsLevel) continue; // Too deep + // We only need to set first code word if it's a multicode signal + // as that's all we'll check for later + if (m_sigs_enabledVec.size() <= code) m_sigs_enabledVec.resize((code + 1024) * 2); + m_sigs_enabledVec[code] = true; + enabled = true; + break; + } + // Note: The tri-state flag is not used by Verilator, but is here for // compatibility with some foreign code. int codesNeeded = VL_WORDS_I(bits); @@ -367,6 +415,7 @@ void VerilatedTrace::declCode(vluint32_t code, vluint32_t bits, bo m_nextCode = std::max(m_nextCode, code + codesNeeded); ++m_numSignals; m_maxBits = std::max(m_maxBits, bits); + return enabled; } //========================================================================= @@ -392,6 +441,19 @@ template <> void VerilatedTrace::set_time_resolution(const std::string& unit) VL_MT_SAFE { set_time_resolution(unit.c_str()); } +template <> +void VerilatedTrace::dumpvars(int level, const std::string& hier) VL_MT_SAFE { + if (level == 0) { + m_dumpvars.clear(); // empty = everything on + } else { + // Convert Verilog . separators to trace space separators + std::string hierSpaced = hier; + for (auto& i : hierSpaced) { + if (i == '.') i = ' '; + } + m_dumpvars.push_back(std::make_pair(level, hierSpaced)); + } +} template <> void VerilatedTrace::dump(vluint64_t timeui) VL_MT_SAFE_EXCLUDES(m_mutex) { @@ -400,8 +462,8 @@ void VerilatedTrace::dump(vluint64_t timeui) VL_MT_SAFE_EXCLUDES(m // chances are the data being dumped will have other problems const VerilatedLockGuard lock{m_mutex}; if (VL_UNCOVERABLE(m_timeLastDump && timeui <= m_timeLastDump)) { // LCOV_EXCL_START - VL_PRINTF_MT("%%Warning: previous dump at t=%" VL_PRI64 "u, requesting t=%" VL_PRI64 - "u, dump call ignored\n", + VL_PRINTF_MT("%%Warning: previous dump at t=%" PRIu64 ", requesting t=%" PRIu64 + ", dump call ignored\n", m_timeLastDump, timeui); return; } // LCOV_EXCL_STOP @@ -504,9 +566,14 @@ template <> void VerilatedTrace::addCleanupCb(dumpCb_t cb, void* u CallbackRecord cbr{cb, userp}; addCallbackRecord(m_cleanupCbs, cbr); } -template <> void VerilatedTrace::module(const std::string& name) VL_MT_UNSAFE { - // Called via callbacks way above in call stack, which already hold m_mutex - m_moduleName = name; + +template <> void VerilatedTrace::pushNamePrefix(const std::string& prefix) { + m_namePrefixStack.push_back(m_namePrefixStack.back() + prefix); +} + +template <> void VerilatedTrace::popNamePrefix(unsigned count) { + while (count--) m_namePrefixStack.pop_back(); + assert(!m_namePrefixStack.empty()); } //========================================================================= @@ -518,44 +585,58 @@ template <> void VerilatedTrace::module(const std::string& name) V // the emit* functions can be inlined for performance. template <> void VerilatedTrace::fullBit(vluint32_t* oldp, CData newval) { - *oldp = newval; - self()->emitBit(oldp - m_sigs_oldvalp, newval); + const uint32_t code = oldp - m_sigs_oldvalp; + *oldp = newval; // Still copy even if not tracing so chg doesn't call full + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + self()->emitBit(code, newval); } template <> void VerilatedTrace::fullCData(vluint32_t* oldp, CData newval, int bits) { - *oldp = newval; - self()->emitCData(oldp - m_sigs_oldvalp, newval, bits); + const uint32_t code = oldp - m_sigs_oldvalp; + *oldp = newval; // Still copy even if not tracing so chg doesn't call full + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + self()->emitCData(code, newval, bits); } template <> void VerilatedTrace::fullSData(vluint32_t* oldp, SData newval, int bits) { - *oldp = newval; - self()->emitSData(oldp - m_sigs_oldvalp, newval, bits); + const uint32_t code = oldp - m_sigs_oldvalp; + *oldp = newval; // Still copy even if not tracing so chg doesn't call full + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + self()->emitSData(code, newval, bits); } template <> void VerilatedTrace::fullIData(vluint32_t* oldp, IData newval, int bits) { - *oldp = newval; - self()->emitIData(oldp - m_sigs_oldvalp, newval, bits); + const uint32_t code = oldp - m_sigs_oldvalp; + *oldp = newval; // Still copy even if not tracing so chg doesn't call full + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + self()->emitIData(code, newval, bits); } template <> void VerilatedTrace::fullQData(vluint32_t* oldp, QData newval, int bits) { + const uint32_t code = oldp - m_sigs_oldvalp; *reinterpret_cast(oldp) = newval; - self()->emitQData(oldp - m_sigs_oldvalp, newval, bits); + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + self()->emitQData(code, newval, bits); } template <> void VerilatedTrace::fullWData(vluint32_t* oldp, const WData* newvalp, int bits) { + const uint32_t code = oldp - m_sigs_oldvalp; for (int i = 0; i < VL_WORDS_I(bits); ++i) oldp[i] = newvalp[i]; - self()->emitWData(oldp - m_sigs_oldvalp, newvalp, bits); + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + self()->emitWData(code, newvalp, bits); } template <> void VerilatedTrace::fullDouble(vluint32_t* oldp, double newval) { - // cppcheck-suppress invalidPointerCast + const uint32_t code = oldp - m_sigs_oldvalp; *reinterpret_cast(oldp) = newval; - self()->emitDouble(oldp - m_sigs_oldvalp, newval); + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + // cppcheck-suppress invalidPointerCast + self()->emitDouble(code, newval); } //========================================================================= @@ -655,7 +736,7 @@ static inline void cvtQDataToStr(char* dstp, QData value) { void verilated_trace_imp_selftest() { #define SELF_CHECK(got, exp) \ do { \ - if ((got) != (exp)) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: selftest\n"); \ + if ((got) != (exp)) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: selftest"); \ } while (0) #define SELF_CHECK_TS(scale) \ diff --git a/include/verilated_types.h b/include/verilated_types.h index 364378080..39592db96 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -28,6 +28,14 @@ #error "verilated_types.h should only be included by verilated.h" #endif +#include +#include +#include +#include +#include +#include +#include + //=================================================================== // String formatters (required by below containers) @@ -45,22 +53,22 @@ extern std::string VL_TO_STRING_W(int words, const WDataInP obj); #define VL_SIG16(name, msb, lsb) SData name ///< Declare signal, 9-16 bits #define VL_SIG64(name, msb, lsb) QData name ///< Declare signal, 33-64 bits #define VL_SIG(name, msb, lsb) IData name ///< Declare signal, 17-32 bits -#define VL_SIGW(name, msb, lsb, words) WData name[words] ///< Declare signal, 65+ bits +#define VL_SIGW(name, msb, lsb, words) VlWide name ///< Declare signal, 65+ bits #define VL_IN8(name, msb, lsb) CData name ///< Declare input signal, 1-8 bits #define VL_IN16(name, msb, lsb) SData name ///< Declare input signal, 9-16 bits #define VL_IN64(name, msb, lsb) QData name ///< Declare input signal, 33-64 bits #define VL_IN(name, msb, lsb) IData name ///< Declare input signal, 17-32 bits -#define VL_INW(name, msb, lsb, words) WData name[words] ///< Declare input signal, 65+ bits +#define VL_INW(name, msb, lsb, words) VlWide name ///< Declare input signal, 65+ bits #define VL_INOUT8(name, msb, lsb) CData name ///< Declare bidir signal, 1-8 bits #define VL_INOUT16(name, msb, lsb) SData name ///< Declare bidir signal, 9-16 bits #define VL_INOUT64(name, msb, lsb) QData name ///< Declare bidir signal, 33-64 bits #define VL_INOUT(name, msb, lsb) IData name ///< Declare bidir signal, 17-32 bits -#define VL_INOUTW(name, msb, lsb, words) WData name[words] ///< Declare bidir signal, 65+ bits +#define VL_INOUTW(name, msb, lsb, words) VlWide name ///< Declare bidir signal, 65+ bits #define VL_OUT8(name, msb, lsb) CData name ///< Declare output signal, 1-8 bits #define VL_OUT16(name, msb, lsb) SData name ///< Declare output signal, 9-16 bits #define VL_OUT64(name, msb, lsb) QData name ///< Declare output signal, 33-64bits #define VL_OUT(name, msb, lsb) IData name ///< Declare output signal, 17-32 bits -#define VL_OUTW(name, msb, lsb, words) WData name[words] ///< Declare output signal, 65+ bits +#define VL_OUTW(name, msb, lsb, words) VlWide name ///< Declare output signal, 65+ bits //=================================================================== // Shuffle RNG @@ -86,6 +94,7 @@ class VlReadMem final { FILE* m_fp; // File handle for filename QData m_addr; // Next address to read int m_linenum; // Line number last read from file + bool m_anyAddr = false; // Had address directive in the file public: VlReadMem(bool hex, int bits, const std::string& filename, QData start, QData end); ~VlReadMem(); @@ -848,8 +857,8 @@ template struct VlUnpacked final { WData* data() { return &m_storage[0]; } const WData* data() const { return &m_storage[0]; } - T_Value& operator[](size_t index) { return m_storage[index]; }; - const T_Value& operator[](size_t index) const { return m_storage[index]; }; + T_Value& operator[](size_t index) { return m_storage[index]; } + const T_Value& operator[](size_t index) const { return m_storage[index]; } // Dumping. Verilog: str = $sformatf("%p", assoc) std::string to_string() const { diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index 860c9de41..cba693d3b 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -273,7 +273,7 @@ void VerilatedVcd::printStr(const char* str) { void VerilatedVcd::printQuad(vluint64_t n) { constexpr size_t LEN_STR_QUAD = 40; char buf[LEN_STR_QUAD]; - VL_SNPRINTF(buf, LEN_STR_QUAD, "%" VL_PRI64 "u", n); + VL_SNPRINTF(buf, LEN_STR_QUAD, "%" PRIu64, n); printStr(buf); } @@ -426,8 +426,9 @@ void VerilatedVcd::dumpHeader() { case VLT_TRACE_SCOPE_UNION: printStr("union "); break; default: printStr("module "); } - } else + } else { printStr("module "); + } for (; *np && *np != ' ' && *np != '\t'; np++) { if (*np == '[') { @@ -462,7 +463,7 @@ void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep, int arraynum, bool tri, bool bussed, int msb, int lsb) { const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; - VerilatedTrace::declCode(code, bits, tri); + const bool enabled = VerilatedTrace::declCode(code, name, bits, tri); if (m_suffixes.size() <= nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE) { m_suffixes.resize(nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE * 2, 0); @@ -471,16 +472,15 @@ void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep, // Make sure write buffer is large enough (one character per bit), plus header bufferResize(bits + 1024); + if (!enabled) return; + // Split name into basename // Spaces and tabs aren't legal in VCD signal names, so: // Space separates each level of scope // Tab separates final scope from signal name // Tab sorts before spaces, so signals nicely will print before scopes // Note the hiername may be nothing, if so we'll add "\t{name}" - std::string nameasstr = name; - if (!moduleName().empty()) { - nameasstr = moduleName() + scopeEscape() + nameasstr; // Optional ->module prefix - } + std::string nameasstr = namePrefix() + name; std::string hiername; std::string basename; for (const char* cp = nameasstr.c_str(); *cp; cp++) { @@ -608,6 +608,7 @@ static inline void VerilatedVcdCCopyAndAppendNewLine(char* writep, const char* s void VerilatedVcd::finishLine(vluint32_t code, char* writep) { const char* const suffixp = m_suffixes.data() + code * VL_TRACE_SUFFIX_ENTRY_SIZE; + VL_DEBUG_IFDEF(assert(suffixp[0]);); VerilatedVcdCCopyAndAppendNewLine(writep, suffixp); // Now write back the write pointer incremented by the actual size of the @@ -830,16 +831,19 @@ float flo = 0.0f; void vcdInit(void*, VerilatedVcd* vcdp, vluint32_t) { vcdp->scopeEscape('.'); - vcdp->module("top"); + vcdp->pushNamePrefix("top."); /**/ vcdp->declBus(0x2, "v1", -1, 0, 5, 1); /**/ vcdp->declBus(0x3, "v2", -1, 0, 6, 1); - /**/ vcdp->module("top.sub1"); + /**/ vcdp->pushNamePrefix("sub1."); /***/ vcdp->declBit(0x4, "s1", -1, 0); /***/ vcdp->declBit(0x5, "ch", -1, 0); - /**/ vcdp->module("top.sub2"); + /**/ vcdp->popNamePrefix(); + /**/ vcdp->pushNamePrefix("sub2."); /***/ vcdp->declArray(0x6, "s2", -1, 0, 40, 3); + /**/ vcdp->popNamePrefix(); + vcdp->popNamePrefix(); // Note need to add 3 for next code. - vcdp->module("top2"); + vcdp->pushNamePrefix("top2."); /**/ vcdp->declBus(0x2, "t2v1", -1, 0, 4, 1); /**/ vcdp->declTriBit(0x10, "io1", -1, 0); /**/ vcdp->declTriBus(0x12, "io5", -1, 0, 4, 0); @@ -851,6 +855,7 @@ void vcdInit(void*, VerilatedVcd* vcdp, vluint32_t) { /**/ // Note need to add 4 for next code. /**/ vcdp->declTriQuad(0x24, "tq", -1, 0, 63, 0); /**/ // Note need to add 4 for next code. + vcdp->popNamePrefix(); } void vcdFull(void*, VerilatedVcd* vcdp) { diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 07b8fb0be..8595baba3 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -328,6 +328,7 @@ template <> void VerilatedTrace::set_time_unit(const char* unitp); template <> void VerilatedTrace::set_time_unit(const std::string& unit); template <> void VerilatedTrace::set_time_resolution(const char* unitp); template <> void VerilatedTrace::set_time_resolution(const std::string& unit); +template <> void VerilatedTrace::dumpvars(int level, const std::string& hier); #endif // DOXYGEN //============================================================================= @@ -346,7 +347,7 @@ public: explicit VerilatedVcdC(VerilatedVcdFile* filep = nullptr) : m_sptrace{filep} {} /// Destruct, flush, and close the dump - ~VerilatedVcdC() { close(); } + virtual ~VerilatedVcdC() { close(); } public: // METHODS - User called @@ -356,7 +357,7 @@ public: /// Open a new VCD file /// This includes a complete header dump each time it is called, /// just as if this object was deleted and reconstructed. - void open(const char* filename) VL_MT_SAFE { m_sptrace.open(filename); } + virtual void open(const char* filename) VL_MT_SAFE { m_sptrace.open(filename); } /// Continue a VCD dump by rotating to a new file name /// The header is only in the first file created, this allows /// "cat" to be used to combine the header plus any number of data files. @@ -392,6 +393,11 @@ public: void set_time_resolution(const std::string& unit) VL_MT_SAFE { m_sptrace.set_time_resolution(unit); } + // Set variables to dump, using $dumpvars format + // If level = 0, dump everything and hier is then ignored + void dumpvars(int level, const std::string& hier) VL_MT_SAFE { + m_sptrace.dumpvars(level, hier); + } // Internal class access inline VerilatedVcd* spTrace() { return &m_sptrace; } diff --git a/include/verilated_vcd_sc.cpp b/include/verilated_vcd_sc.cpp index ac0dc52c7..d03a85231 100644 --- a/include/verilated_vcd_sc.cpp +++ b/include/verilated_vcd_sc.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -27,6 +27,17 @@ //====================================================================== //====================================================================== +void VerilatedVcdSc::open(const char* filename) { + if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) { + vl_fatal(__FILE__, __LINE__, "VerilatedVcdSc", + ("%Error: VerilatedVcdSc::open(\"" + std::string(filename) + + "\") is called before sc_core::sc_start(). " + "Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before opening a wave file.") + .c_str()); + } + VerilatedVcdC::open(filename); +} + //-------------------------------------------------- // SystemC 2.1.v1 // cppcheck-suppress unusedFunction diff --git a/include/verilated_vcd_sc.h b/include/verilated_vcd_sc.h index a79a9c61a..beb153e98 100644 --- a/include/verilated_vcd_sc.h +++ b/include/verilated_vcd_sc.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// Copyright 2001-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2001-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -26,6 +26,8 @@ #include "verilated_sc.h" #include "verilated_vcd_c.h" +#include + //============================================================================= // VerilatedVcdSc /// @@ -60,6 +62,9 @@ public: if (!delta_cycle) this->dump(sc_time_stamp().to_double()); } + // Override VerilatedVcdC. Must be called after starting simulation. + virtual void open(const char* filename) /*override*/ VL_MT_SAFE; + private: // METHODS - Fake outs for linker diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 7316d1474..365d0e520 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,6 +33,10 @@ #include #include #include +#include +#include +#include +#include //====================================================================== // Internal constants @@ -534,7 +538,7 @@ public: if (VL_UNCOVERABLE(cb_data_p->reason >= CB_ENUM_MAX_VALUE)) { VL_FATAL_MT(__FILE__, __LINE__, "", "vpi bb reason too large"); } - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb reason=%d id=%" VL_PRI64 "d obj=%p\n", + VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb reason=%d id=%" PRId64 " obj=%p\n", cb_data_p->reason, id, cb_data_p->obj);); VerilatedVpioVar* varop = nullptr; if (cb_data_p->reason == cbValueChange) varop = VerilatedVpioVar::castp(cb_data_p->obj); @@ -542,8 +546,8 @@ public: } static void cbTimedAdd(vluint64_t id, const s_cb_data* cb_data_p, QData time) { // The passed cb_data_p was property of the user, so need to recreate - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb reason=%d id=%" VL_PRI64 - "d delay=%" VL_PRI64 "u\n", + VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb reason=%d id=%" PRId64 + " delay=%" PRIu64 "\n", cb_data_p->reason, id, time);); s().m_timedCbs.emplace(std::piecewise_construct, std::forward_as_tuple(std::make_pair(time, id)), @@ -573,7 +577,7 @@ public: ++it; if (VL_UNLIKELY(!ho.invalid())) { VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: timed_callback id=%" VL_PRI64 "d\n", ho.id());); + VL_DBG_MSGF("- vpi: timed_callback id=%" PRId64 "\n", ho.id());); ho.invalidate(); // Timed callbacks are one-shot (ho.cb_rtnp())(ho.cb_datap()); } @@ -602,7 +606,7 @@ public: continue; } VerilatedVpiCbHolder& ho = *it; - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: reason_callback reason=%d id=%" VL_PRI64 "d\n", + VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: reason_callback reason=%d id=%" PRId64 "\n", reason, ho.id());); (ho.cb_rtnp())(ho.cb_datap()); called = true; @@ -636,9 +640,9 @@ public: *(static_cast(prevDatap)), newDatap, prevDatap);); if (std::memcmp(prevDatap, newDatap, varop->entSize()) != 0) { - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: value_callback %" VL_PRI64 "d %s v[0]=%d\n", ho.id(), - varop->fullname(), *(static_cast(newDatap)));); + VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_callback %" PRId64 " %s v[0]=%d\n", + ho.id(), varop->fullname(), + *(static_cast(newDatap)));); update.insert(varop); vpi_get_value(ho.cb_datap()->obj, ho.cb_datap()->value); (ho.cb_rtnp())(ho.cb_datap()); @@ -1697,7 +1701,7 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep, // Maximum required size is for binary string, one byte per bit plus null termination static VL_THREAD_LOCAL char t_outStr[VL_VALUE_STRING_MAX_WORDS * VL_EDATASIZE + 1]; // cppcheck-suppress variableScope - const static VL_THREAD_LOCAL int t_outStrSz = sizeof(t_outStr) - 1; + static const VL_THREAD_LOCAL int t_outStrSz = sizeof(t_outStr) - 1; // We used to presume vpiValue.format = vpiIntVal or if single bit vpiScalarVal // This may cause backward compatibility issues with older code. if (valuep->format == vpiVectorVal) { diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index 9f8f8f90d..74bff7abf 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilatedos.h b/include/verilatedos.h index b6a837663..af7742388 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -92,7 +92,7 @@ # define VL_ATTR_NORETURN ///< Attribute that function does not ever return #endif #ifndef VL_ATTR_NO_SANITIZE_ALIGN -# define VL_ATTR_NO_SANITIZE_ALIGN ///< Attribute that the function contains intended unaligned access +# define VL_ATTR_NO_SANITIZE_ALIGN ///< Attribute that function contains intended unaligned access #endif #ifndef VL_ATTR_PRINTF # define VL_ATTR_PRINTF(fmtArgNum) ///< Attribute for function with printf format checking @@ -278,89 +278,55 @@ void __gcov_flush(); // gcc sources gcc/gcov-io.h has the prototype // to be declared in order to get the PRIxx macros used by fstapi.c #define __STDC_FORMAT_MACROS +// Now that C++ requires these standard types the vl types are deprecated +#include +#include + +using vluint8_t = uint8_t; ///< 8-bit unsigned type (backward compatibility) +using vluint16_t = uint16_t; ///< 16-bit unsigned type (backward compatibility) +using vluint32_t = uint32_t; ///< 32-bit unsigned type (backward compatibility) +using vluint64_t = uint64_t; ///< 64-bit unsigned type (backward compatibility) +using vlsint8_t = int8_t; ///< 8-bit signed type (backward compatibility) +using vlsint16_t = int16_t; ///< 16-bit signed type (backward compatibility) +using vlsint32_t = int32_t; ///< 32-bit signed type (backward compatibility) +using vlsint64_t = int64_t; ///< 64-bit signed type (backward compatibility) + #if defined(__CYGWIN__) -# include # include // __WORDSIZE # include // ssize_t -typedef unsigned char uint8_t; ///< 8-bit unsigned type (backward compatibility) -typedef unsigned short int uint16_t; ///< 16-bit unsigned type (backward compatibility) -typedef char vlsint8_t; ///< 8-bit signed type -typedef unsigned char vluint8_t; ///< 8-bit unsigned type -typedef short int vlsint16_t; ///< 16-bit signed type -typedef unsigned short int vluint16_t; ///< 16-bit unsigned type -# if defined(__uint32_t_defined) || defined(___int32_t_defined) // Newer Cygwin uint32_t in stdint.h as an unsigned int -typedef int32_t vlsint32_t; ///< 32-bit signed type -typedef uint32_t vluint32_t; ///< 32-bit unsigned type -# else // Older Cygwin has long==uint32_t -typedef unsigned long uint32_t; ///< 32-bit unsigned type (backward compatibility) -typedef long vlsint32_t; ///< 32-bit signed type -typedef unsigned long vluint32_t; ///< 32-bit unsigned type -# endif -# if defined(__WORDSIZE) && (__WORDSIZE == 64) -typedef long vlsint64_t; ///< 64-bit signed type -typedef unsigned long vluint64_t; ///< 64-bit unsigned type -# else -typedef long long vlsint64_t; ///< 64-bit signed type -typedef unsigned long long vluint64_t; ///< 64-bit unsigned type -# endif #elif defined(_WIN32) && defined(_MSC_VER) -typedef unsigned __int8 uint8_t; ///< 8-bit unsigned type (backward compatibility) -typedef unsigned __int16 uint16_t; ///< 16-bit unsigned type (backward compatibility) -typedef unsigned __int32 uint32_t; ///< 32-bit unsigned type (backward compatibility) -typedef signed __int8 vlsint8_t; ///< 8-bit signed type -typedef unsigned __int8 vluint8_t; ///< 8-bit unsigned type -typedef signed __int16 vlsint16_t; ///< 16-bit signed type -typedef unsigned __int16 vluint16_t; ///< 16-bit unsigned type -typedef signed __int32 vlsint32_t; ///< 32-bit signed type -typedef unsigned __int32 vluint32_t; ///< 32-bit unsigned type -typedef signed __int64 vlsint64_t; ///< 64-bit signed type -typedef unsigned __int64 vluint64_t; ///< 64-bit unsigned type - # ifndef _SSIZE_T_DEFINED # ifdef _WIN64 -typedef signed __int64 ssize_t; ///< signed size_t; returned from read() +using ssize_t = uint64_t; ///< signed size_t; returned from read() # else -typedef signed __int32 ssize_t; ///< signed size_t; returned from read() +using ssize_t = uint32_t; ///< signed size_t; returned from read() # endif # endif #else // Linux or compliant Unix flavors, -m64 # include // Solaris -# include // Linux and most flavors # include // __WORDSIZE # include // ssize_t -// Arm64 gcc 9.3.0 defaults to unsigned char, not signed char -typedef signed char vlsint8_t; ///< 8-bit signed type -typedef uint8_t vluint8_t; ///< 8-bit unsigned type -typedef short vlsint16_t; ///< 16-bit signed type -typedef uint16_t vluint16_t; ///< 16-bit unsigned type -typedef int vlsint32_t; ///< 32-bit signed type -typedef uint32_t vluint32_t; ///< 32-bit unsigned type -# if defined(__WORDSIZE) && (__WORDSIZE == 64) -typedef long vlsint64_t; ///< 64-bit signed type -typedef unsigned long vluint64_t; ///< 64-bit unsigned type -# else -typedef long long vlsint64_t; ///< 64-bit signed type -typedef unsigned long long vluint64_t; ///< 64-bit unsigned type -# endif #endif //========================================================================= // Printing printf/scanf formats -// Alas cinttypes isn't that standard yet // Use Microsoft-specific format specifiers for Microsoft Visual C++ only -#ifdef _MSC_VER -# define VL_PRI64 "I64" -#else // use standard C99 format specifiers -# if defined(__WORDSIZE) && (__WORDSIZE == 64) -# define VL_PRI64 "l" -# else -# define VL_PRI64 "ll" +// Deprecated, favor C++11's PRIx64, etc, instead +#ifndef VL_NO_LEGACY +# ifdef _MSC_VER +# define VL_PRI64 "I64" ///< print a vluint64_t (backward compatibility) +# else // use standard C99 format specifiers +# if defined(__WORDSIZE) && (__WORDSIZE == 64) +# define VL_PRI64 "l" ///< print a vluint64_t (backward compatibility) +# else +# define VL_PRI64 "ll" ///< print a vluint64_t (backward compatibility) +# endif # endif #endif @@ -448,6 +414,12 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type #define VL_BITBIT_Q(bit) ((bit) & VL_SIZEBITS_Q) ///< Bit number for a bit in a quad #define VL_BITBIT_E(bit) ((bit) & VL_SIZEBITS_E) ///< Bit number for a bit in a EData +// Return true if data[bit] set; not 0/1 return, but 0/non-zero return. +#define VL_BITISSET_I(data, bit) ((data) & (VL_UL(1) << VL_BITBIT_I(bit))) +#define VL_BITISSET_Q(data, bit) ((data) & (1ULL << VL_BITBIT_Q(bit))) +#define VL_BITISSET_E(data, bit) ((data) & (VL_EUL(1) << VL_BITBIT_E(bit))) +#define VL_BITISSET_W(data, bit) ((data)[VL_BITWORD_E(bit)] & (VL_EUL(1) << VL_BITBIT_E(bit))) + //========================================================================= // Floating point // #defines, to avoid requiring math.h on all compile runs @@ -533,7 +505,7 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type # ifdef __x86_64__ # define VL_X86_64 1 # endif -#endif // VL_PORTABLE_ONLY +#endif // VL_PORTABLE_ONLY // clang-format on //========================================================================= diff --git a/nodist/code_coverage b/nodist/code_coverage index ffddfa585..286397e91 100755 --- a/nodist/code_coverage +++ b/nodist/code_coverage @@ -346,7 +346,7 @@ files. Run as: cd $VERILATOR_ROOT nodist/code_coverage""", epilog= - """Copyright 2019-2021 by Wilson Snyder. This program is free software; you + """Copyright 2019-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/nodist/code_coverage.dat b/nodist/code_coverage.dat index 88c21b5f1..bff045d22 100644 --- a/nodist/code_coverage.dat +++ b/nodist/code_coverage.dat @@ -1,7 +1,7 @@ # -*- Python -*- # DESCRIPTION: Verilator: Internal C++ code lcov control file # -# Copyright 2019-2021 by Wilson Snyder. This program is free software; you +# Copyright 2019-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/nodist/dot_importer b/nodist/dot_importer index cc9520a27..29fe37fc2 100755 --- a/nodist/dot_importer +++ b/nodist/dot_importer @@ -87,7 +87,7 @@ parser = argparse.ArgumentParser( This x.cpp file is then manually included in V3GraphTest.cpp to verify various xsub-algorithms.""", epilog= - """Copyright 2005-2021 by Wilson Snyder. This program is free software; you + """Copyright 2005-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/nodist/install_test b/nodist/install_test index faa2cf1ac..7dcc2853a 100755 --- a/nodist/install_test +++ b/nodist/install_test @@ -118,7 +118,7 @@ parser = argparse.ArgumentParser( Verilator kit. It isn't part of the normal "make test" due to the number of builds required.""", epilog= - """Copyright 2009-2021 by Wilson Snyder. This program is free software; you + """Copyright 2009-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/.gdbinit b/src/.gdbinit index 76b0e3945..b09fa6539 100644 --- a/src/.gdbinit +++ b/src/.gdbinit @@ -1,6 +1,6 @@ # DESCRIPTION: Verilator: GDB startup file with useful defines # -# Copyright 2012-2021 by Wilson Snyder. This program is free software; you +# Copyright 2012-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/src/Makefile.in b/src/Makefile.in index 2d47f7fc3..ffd2eaf72 100644 --- a/src/Makefile.in +++ b/src/Makefile.in @@ -7,7 +7,7 @@ # #***************************************************************************** # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index c2e832bdc..140be6086 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -7,7 +7,7 @@ # #***************************************************************************** # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -75,7 +75,9 @@ VPATH += . $(bldsrc) $(srcdir) TGT = ../../verilator_bin$(EXEEXT) ################# -ifeq ($(VL_DEBUG),) +ifeq ($(VL_NOOPT),1) +CPPFLAGS += -O0 +else ifeq ($(VL_DEBUG),) # Optimize CPPFLAGS += -O2 else @@ -197,6 +199,7 @@ RAW_OBJS = \ V3Expand.o \ V3File.o \ V3FileLine.o \ + V3Force.o \ V3Gate.o \ V3GenClk.o \ V3Global.o \ @@ -271,6 +274,11 @@ NC_OBJS += \ VLCOV_OBJS = \ VlcMain.o \ +NON_STANDALONE_HEADERS = \ + V3AstInlines.h \ + V3AstNodes.h \ + V3WidthCommit.h \ + #### Linking ifeq ($(VL_VLCOV),) @@ -348,6 +356,15 @@ V3PreLex_pregen.yy.cpp: V3PreLex.l $(HEADERS) V3PreLex.yy.cpp: V3PreLex_pregen.yy.cpp $(FLEXFIX) $(PYTHON3) $(FLEXFIX) V3PreLex <$< >$@ +# For t_dist_header_cc +HEADER_CC_H := $(filter-out $(NON_STANDALONE_HEADERS), $(notdir $(wildcard $(srcdir)/*.h))) + +.PHONY: header_cc +header_cc: $(addsuffix __header_cc.o, $(basename $(HEADER_CC_H))) + +%__header_cc.cpp: %.h + $(PERL) $(srcdir)/../bin/verilator_includer $^ > $@ + .SUFFIXES: ###################################################################### diff --git a/src/V3Active.cpp b/src/V3Active.cpp index f50ecada3..043f05233 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,9 +32,7 @@ #include "V3Global.h" #include "V3Active.h" #include "V3Ast.h" -#include "V3EmitCBase.h" #include "V3Const.h" -#include "V3SenTree.h" // for SenTreeSet #include "V3Graph.h" #include @@ -163,9 +161,9 @@ public: LatchDetectGraphVertex* outVertexp; if (!nodep->varp()->user1p()) { // Not seen this output before outVertexp = addOutputVertex(nodep); - } else + } else { outVertexp = castVertexp(nodep->varp()->user1p()); - + } new V3GraphEdge(this, m_curVertexp, outVertexp, 1); } // Run latchCheckInternal on each variable assigned by the always block to see if all control @@ -199,7 +197,7 @@ public: //###################################################################### // Collect existing active names -class ActiveBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class ActiveBaseVisitor VL_NOT_FINAL : public VNVisitor { protected: VL_DEBUG_FUNC; // Declare debug() }; @@ -211,9 +209,8 @@ private: AstActive* m_iActivep = nullptr; // For current scope, the IActive we're building AstActive* m_cActivep = nullptr; // For current scope, the SActive(combo) we're building - SenTreeSet m_activeSens; // Sen lists for each active we've made - using ActiveMap = std::unordered_map; - ActiveMap m_activeMap; // Map sentree to active, for folding. + // Map from AstSenTree (equivalence) to the corresponding AstActive created. + std::unordered_map, AstActive*> m_activeMap; // METHODS void addActive(AstActive* nodep) { @@ -225,7 +222,6 @@ private: m_scopep = nodep; m_iActivep = nullptr; m_cActivep = nullptr; - m_activeSens.clear(); m_activeMap.clear(); iterateChildren(nodep); // Don't clear scopep, the namer persists beyond this visit @@ -259,29 +255,20 @@ public: } return m_iActivep; } + + // Return an AstActive that is sensitive to a SenTree equivalent to the given sentreep. AstActive* getActive(FileLine* fl, AstSenTree* sensesp) { - // Return a sentree in this scope that matches given sense list. - AstActive* activep = nullptr; - AstSenTree* const activeSenp = m_activeSens.find(sensesp); - if (activeSenp) { - const auto it = m_activeMap.find(activeSenp); - UASSERT(it != m_activeMap.end(), "Corrupt active map"); - activep = it->second; - } + auto it = m_activeMap.find(*sensesp); + // If found matching AstActive, return it + if (it != m_activeMap.end()) return it->second; - // Not found, form a new one - if (!activep) { - AstSenTree* const newsenp = sensesp->cloneTree(false); - activep = new AstActive(fl, "sequent", newsenp); - activep->sensesStorep(activep->sensesp()); - UINFO(8, " New ACTIVE " << activep << endl); - // Form the sensitivity list - addActive(activep); - m_activeMap[newsenp] = activep; - m_activeSens.add(newsenp); - // Note actives may have also been added above in the Active visitor - } + // No such AstActive yet, creat it, and add to map. + AstSenTree* const newsenp = sensesp->cloneTree(false); + AstActive* const activep = new AstActive(fl, "sequent", newsenp); + activep->sensesStorep(activep->sensesp()); + addActive(activep); + m_activeMap.emplace(*newsenp, activep); return activep; } @@ -299,7 +286,7 @@ private: // NODE STATE // Input: // AstVar::user1p // V2LatchGraphVertex* The vertex handling this node - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE LatchDetectGraph m_graph; // Graph used to detect latches in combo always // VISITORS @@ -476,7 +463,7 @@ private: m_scopeFinalp = new AstCFunc( nodep->fileline(), "_final_" + m_namer.scopep()->nameDotless(), m_namer.scopep()); m_scopeFinalp->dontCombine(true); - m_scopeFinalp->formCallTree(true); + m_scopeFinalp->isFinal(true); m_scopeFinalp->isStatic(false); m_scopeFinalp->isLoose(true); m_scopeFinalp->slow(true); diff --git a/src/V3Active.h b/src/V3Active.h index 31fca4e4f..84ee4cdb9 100644 --- a/src/V3Active.h +++ b/src/V3Active.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3ActiveTop.cpp b/src/V3ActiveTop.cpp index 04aa7f79e..f4f9782b1 100644 --- a/src/V3ActiveTop.cpp +++ b/src/V3ActiveTop.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -35,14 +35,14 @@ //###################################################################### // Active class functions -class ActiveTopVisitor final : public AstNVisitor { +class ActiveTopVisitor final : public VNVisitor { private: // NODE STATE // Entire netlist // AstNode::user() bool. True if processed // Each call to V3Const::constify // AstNode::user4() Used by V3Const::constify, called below - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE SenTreeFinder m_finder; // Find global sentree's / add them under the AstTopScope diff --git a/src/V3ActiveTop.h b/src/V3ActiveTop.h index b17427244..5a7f018db 100644 --- a/src/V3ActiveTop.h +++ b/src/V3ActiveTop.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index 59a675d0f..26b16ebd5 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -25,12 +25,12 @@ //###################################################################### // Assert class functions -class AssertVisitor final : public AstNVisitor { +class AssertVisitor final : public VNVisitor { private: // NODE STATE/TYPES // Cleared on netlist // AstNode::user() -> bool. True if processed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE AstNodeModule* m_modp = nullptr; // Last module @@ -52,7 +52,7 @@ private: + ((message != "") ? ": " : "") + message + "\n"); } void replaceDisplay(AstDisplay* nodep, const string& prefix) { - nodep->displayType(AstDisplayType::DT_WRITE); + nodep->displayType(VDisplayType::DT_WRITE); nodep->fmtp()->text(assertDisplayMessage(nodep, prefix, nodep->fmtp()->text())); // cppcheck-suppress nullPointer AstNode* const timenewp = new AstTime(nodep->fileline(), m_modp->timeunit()); @@ -67,8 +67,8 @@ private: } AstVarRef* newMonitorNumVarRefp(AstNode* nodep, VAccess access) { if (!m_monitorNumVarp) { - m_monitorNumVarp = new AstVar{nodep->fileline(), AstVarType::MODULETEMP, - "__VmonitorNum", nodep->findUInt64DType()}; + m_monitorNumVarp = new AstVar{nodep->fileline(), VVarType::MODULETEMP, "__VmonitorNum", + nodep->findUInt64DType()}; v3Global.rootp()->dollarUnitPkgAddp()->addStmtp(m_monitorNumVarp); } const auto varrefp = new AstVarRef(nodep->fileline(), m_monitorNumVarp, access); @@ -77,8 +77,8 @@ private: } AstVarRef* newMonitorOffVarRefp(AstNode* nodep, VAccess access) { if (!m_monitorOffVarp) { - m_monitorOffVarp = new AstVar{nodep->fileline(), AstVarType::MODULETEMP, - "__VmonitorOff", nodep->findBitDType()}; + m_monitorOffVarp = new AstVar{nodep->fileline(), VVarType::MODULETEMP, "__VmonitorOff", + nodep->findBitDType()}; v3Global.rootp()->dollarUnitPkgAddp()->addStmtp(m_monitorOffVarp); } const auto varrefp = new AstVarRef(nodep->fileline(), m_monitorOffVarp, access); @@ -105,8 +105,8 @@ private: AstNode* newFireAssertUnchecked(AstNode* nodep, const string& message) { // Like newFireAssert() but omits the asserts-on check - AstDisplay* const dispp = new AstDisplay(nodep->fileline(), AstDisplayType::DT_ERROR, - message, nullptr, nullptr); + AstDisplay* const dispp + = new AstDisplay(nodep->fileline(), VDisplayType::DT_ERROR, message, nullptr, nullptr); dispp->fmtp()->timeunit(m_modp->timeunit()); AstNode* const bodysp = dispp; replaceDisplay(dispp, "%%Error"); // Convert to standard DISPLAY format @@ -341,7 +341,7 @@ private: m_modp->addStmtp(alwaysp); for (uint32_t i = 0; i < ticks; ++i) { AstVar* const outvarp = new AstVar( - nodep->fileline(), AstVarType::MODULETEMP, + nodep->fileline(), VVarType::MODULETEMP, "_Vpast_" + cvtToStr(m_modPastNum++) + "_" + cvtToStr(i), inp->dtypep()); m_modp->addStmtp(outvarp); AstNode* const assp = new AstAssignDly( @@ -362,15 +362,15 @@ private: virtual void visit(AstDisplay* nodep) override { iterateChildren(nodep); // Replace the special types with standard text - if (nodep->displayType() == AstDisplayType::DT_INFO) { + if (nodep->displayType() == VDisplayType::DT_INFO) { replaceDisplay(nodep, "-Info"); - } else if (nodep->displayType() == AstDisplayType::DT_WARNING) { + } else if (nodep->displayType() == VDisplayType::DT_WARNING) { replaceDisplay(nodep, "%%Warning"); - } else if (nodep->displayType() == AstDisplayType::DT_ERROR - || nodep->displayType() == AstDisplayType::DT_FATAL) { + } else if (nodep->displayType() == VDisplayType::DT_ERROR + || nodep->displayType() == VDisplayType::DT_FATAL) { replaceDisplay(nodep, "%%Error"); - } else if (nodep->displayType() == AstDisplayType::DT_MONITOR) { - nodep->displayType(AstDisplayType::DT_DISPLAY); + } else if (nodep->displayType() == VDisplayType::DT_MONITOR) { + nodep->displayType(VDisplayType::DT_DISPLAY); const auto fl = nodep->fileline(); const auto monNum = ++m_monitorNum; // Where $monitor was we do "__VmonitorNum = N;" @@ -388,12 +388,12 @@ private: ifp->branchPred(VBranchPred::BP_UNLIKELY); AstNode* const newp = new AstAlwaysPostponed{fl, ifp}; m_modp->addStmtp(newp); - } else if (nodep->displayType() == AstDisplayType::DT_STROBE) { - nodep->displayType(AstDisplayType::DT_DISPLAY); + } else if (nodep->displayType() == VDisplayType::DT_STROBE) { + nodep->displayType(VDisplayType::DT_DISPLAY); // Need one-shot const auto fl = nodep->fileline(); const auto varp - = new AstVar{fl, AstVarType::MODULETEMP, "__Vstrobe" + cvtToStr(m_modStrobeNum++), + = new AstVar{fl, VVarType::MODULETEMP, "__Vstrobe" + cvtToStr(m_modStrobeNum++), nodep->findBitDType()}; m_modp->addStmtp(varp); // Where $strobe was we do "__Vstrobe = '1;" diff --git a/src/V3Assert.h b/src/V3Assert.h index 29a600628..3846ef589 100644 --- a/src/V3Assert.h +++ b/src/V3Assert.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index 758d0acf1..e091b9855 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -22,11 +22,12 @@ #include "V3Global.h" #include "V3AssertPre.h" +#include "V3Ast.h" //###################################################################### // Assert class functions -class AssertPreVisitor final : public AstNVisitor { +class AssertPreVisitor final : public VNVisitor { // Removes clocks and other pre-optimizations // Eventually inlines calls to sequences, properties, etc. // We're not parsing the tree, or anything more complicated. diff --git a/src/V3AssertPre.h b/src/V3AssertPre.h index 7c277d76e..30efc1f2d 100644 --- a/src/V3AssertPre.h +++ b/src/V3AssertPre.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 05d2f99cf..a711e9a27 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -21,6 +21,7 @@ #include "V3File.h" #include "V3Global.h" #include "V3Broken.h" +#include "V3EmitV.h" #include "V3String.h" #include @@ -36,58 +37,38 @@ vluint64_t AstNode::s_editCntGbl = 0; // Hot cache line // along with each userp, and thus by bumping this count we can make it look // as if we iterated across the entire tree to set all the userp's to null. int AstNode::s_cloneCntGbl = 0; -uint32_t AstUser1InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent -uint32_t AstUser2InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent -uint32_t AstUser3InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent -uint32_t AstUser4InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent -uint32_t AstUser5InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent +uint32_t VNUser1InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent +uint32_t VNUser2InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent +uint32_t VNUser3InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent +uint32_t VNUser4InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent +uint32_t VNUser5InUse::s_userCntGbl = 0; // Hot cache line, leave adjacent -bool AstUser1InUse::s_userBusy = false; -bool AstUser2InUse::s_userBusy = false; -bool AstUser3InUse::s_userBusy = false; -bool AstUser4InUse::s_userBusy = false; -bool AstUser5InUse::s_userBusy = false; +bool VNUser1InUse::s_userBusy = false; +bool VNUser2InUse::s_userBusy = false; +bool VNUser3InUse::s_userBusy = false; +bool VNUser4InUse::s_userBusy = false; +bool VNUser5InUse::s_userBusy = false; int AstNodeDType::s_uniqueNum = 0; //###################################################################### // V3AstType -std::ostream& operator<<(std::ostream& os, AstType rhs); +std::ostream& operator<<(std::ostream& os, VNType rhs); //###################################################################### // Creators -AstNode::AstNode(AstType t, FileLine* fl) +AstNode::AstNode(VNType t, FileLine* fl) : m_type{t} , m_fileline{fl} { - editCountInc(); - m_nextp = nullptr; - m_backp = nullptr; m_headtailp = this; // When made, we're a list of only a single element - m_op1p = nullptr; - m_op2p = nullptr; - m_op3p = nullptr; - m_op4p = nullptr; - m_iterpp = nullptr; - m_dtypep = nullptr; - m_clonep = nullptr; - m_cloneCnt = 0; // Attributes m_flags.didWidth = false; m_flags.doingWidth = false; m_flags.protect = true; m_flags.unused = 0; // Initializing this avoids a read-modify-write on construction - m_user1u = VNUser(0); - m_user1Cnt = 0; - m_user2u = VNUser(0); - m_user2Cnt = 0; - m_user3u = VNUser(0); - m_user3Cnt = 0; - m_user4u = VNUser(0); - m_user4Cnt = 0; - m_user5u = VNUser(0); - m_user5Cnt = 0; + editCountInc(); } AstNode* AstNode::abovep() const { @@ -438,12 +419,12 @@ void AstNode::addOp4p(AstNode* newp) { void AstNode::replaceWith(AstNode* newp) { // Replace oldp with this // Unlike a unlink/relink, children are changed to point to the new node. - AstNRelinker repHandle; + VNRelinker repHandle; this->unlinkFrBack(&repHandle); repHandle.relink(newp); } -void AstNRelinker::dump(std::ostream& str) const { +void VNRelinker::dump(std::ostream& str) const { str << " BK=" << reinterpret_cast(m_backp); str << " ITER=" << reinterpret_cast(m_iterpp); str << " CHG=" << (m_chg == RELINK_NEXT ? "[NEXT] " : ""); @@ -453,7 +434,7 @@ void AstNRelinker::dump(std::ostream& str) const { str << (m_chg == RELINK_OP4 ? "[OP4] " : ""); } -AstNode* AstNode::unlinkFrBackWithNext(AstNRelinker* linkerp) { +AstNode* AstNode::unlinkFrBackWithNext(VNRelinker* linkerp) { debugTreeChange(this, "-unlinkWNextThs: ", __LINE__, true); AstNode* const oldp = this; UASSERT(oldp->m_backp, "Node has no back, already unlinked?"); @@ -464,15 +445,15 @@ AstNode* AstNode::unlinkFrBackWithNext(AstNRelinker* linkerp) { linkerp->m_backp = backp; linkerp->m_iterpp = oldp->m_iterpp; if (backp->m_nextp == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_NEXT; + linkerp->m_chg = VNRelinker::RELINK_NEXT; } else if (backp->m_op1p == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_OP1; + linkerp->m_chg = VNRelinker::RELINK_OP1; } else if (backp->m_op2p == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_OP2; + linkerp->m_chg = VNRelinker::RELINK_OP2; } else if (backp->m_op3p == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_OP3; + linkerp->m_chg = VNRelinker::RELINK_OP3; } else if (backp->m_op4p == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_OP4; + linkerp->m_chg = VNRelinker::RELINK_OP4; } else { oldp->v3fatalSrc("Unlink of node with back not pointing to it."); } @@ -513,7 +494,7 @@ AstNode* AstNode::unlinkFrBackWithNext(AstNRelinker* linkerp) { return oldp; } -AstNode* AstNode::unlinkFrBack(AstNRelinker* linkerp) { +AstNode* AstNode::unlinkFrBack(VNRelinker* linkerp) { debugTreeChange(this, "-unlinkFrBkThs: ", __LINE__, true); AstNode* const oldp = this; UASSERT(oldp->m_backp, "Node has no back, already unlinked?"); @@ -524,15 +505,15 @@ AstNode* AstNode::unlinkFrBack(AstNRelinker* linkerp) { linkerp->m_backp = backp; linkerp->m_iterpp = oldp->m_iterpp; if (backp->m_nextp == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_NEXT; + linkerp->m_chg = VNRelinker::RELINK_NEXT; } else if (backp->m_op1p == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_OP1; + linkerp->m_chg = VNRelinker::RELINK_OP1; } else if (backp->m_op2p == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_OP2; + linkerp->m_chg = VNRelinker::RELINK_OP2; } else if (backp->m_op3p == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_OP3; + linkerp->m_chg = VNRelinker::RELINK_OP3; } else if (backp->m_op4p == oldp) { - linkerp->m_chg = AstNRelinker::RELINK_OP4; + linkerp->m_chg = VNRelinker::RELINK_OP4; } else { this->v3fatalSrc("Unlink of node with back not pointing to it."); } @@ -577,7 +558,7 @@ AstNode* AstNode::unlinkFrBack(AstNRelinker* linkerp) { return oldp; } -void AstNode::relink(AstNRelinker* linkerp) { +void AstNode::relink(VNRelinker* linkerp) { if (debug() > 8) { UINFO(0, " EDIT: relink: "); dumpPtrs(); @@ -597,11 +578,11 @@ void AstNode::relink(AstNRelinker* linkerp) { debugTreeChange(backp, "-relinkTre: ", __LINE__, true); switch (linkerp->m_chg) { - case AstNRelinker::RELINK_NEXT: backp->addNextHere(newp); break; - case AstNRelinker::RELINK_OP1: relinkOneLink(backp->m_op1p /*ref*/, newp); break; - case AstNRelinker::RELINK_OP2: relinkOneLink(backp->m_op2p /*ref*/, newp); break; - case AstNRelinker::RELINK_OP3: relinkOneLink(backp->m_op3p /*ref*/, newp); break; - case AstNRelinker::RELINK_OP4: relinkOneLink(backp->m_op4p /*ref*/, newp); break; + case VNRelinker::RELINK_NEXT: backp->addNextHere(newp); break; + case VNRelinker::RELINK_OP1: relinkOneLink(backp->m_op1p /*ref*/, newp); break; + case VNRelinker::RELINK_OP2: relinkOneLink(backp->m_op2p /*ref*/, newp); break; + case VNRelinker::RELINK_OP3: relinkOneLink(backp->m_op3p /*ref*/, newp); break; + case VNRelinker::RELINK_OP4: relinkOneLink(backp->m_op4p /*ref*/, newp); break; default: this->v3fatalSrc("Relink of node without any link to change."); break; } // Relink @@ -651,15 +632,15 @@ void AstNode::relinkOneLink(AstNode*& pointpr, // Ref to pointer that gets set void AstNode::addHereThisAsNext(AstNode* newp) { // {old}->this->{next} becomes {old}->new->this->{next} - AstNRelinker handle; + VNRelinker handle; this->unlinkFrBackWithNext(&handle); newp->addNext(this); handle.relink(newp); } void AstNode::swapWith(AstNode* bp) { - AstNRelinker aHandle; - AstNRelinker bHandle; + VNRelinker aHandle; + VNRelinker bHandle; this->unlinkFrBack(&aHandle); bp->unlinkFrBack(&bHandle); aHandle.relink(bp); @@ -793,7 +774,7 @@ void AstNode::operator delete(void* objp, size_t size) { //====================================================================== // Iterators -void AstNode::iterateChildren(AstNVisitor& v) { +void AstNode::iterateChildren(VNVisitor& v) { // This is a very hot function // Optimization note: Grabbing m_op#p->m_nextp is a net loss ASTNODE_PREFETCH(m_op1p); @@ -806,7 +787,7 @@ void AstNode::iterateChildren(AstNVisitor& v) { if (m_op4p) m_op4p->iterateAndNext(v); } -void AstNode::iterateChildrenConst(AstNVisitor& v) { +void AstNode::iterateChildrenConst(VNVisitor& v) { // This is a very hot function ASTNODE_PREFETCH(m_op1p); ASTNODE_PREFETCH(m_op2p); @@ -818,7 +799,7 @@ void AstNode::iterateChildrenConst(AstNVisitor& v) { if (m_op4p) m_op4p->iterateAndNextConst(v); } -void AstNode::iterateAndNext(AstNVisitor& v) { +void AstNode::iterateAndNext(VNVisitor& v) { // This is a very hot function // IMPORTANT: If you replace a node that's the target of this iterator, // then the NEW node will be iterated on next, it isn't skipped! @@ -852,7 +833,7 @@ void AstNode::iterateAndNext(AstNVisitor& v) { } } -void AstNode::iterateListBackwards(AstNVisitor& v) { +void AstNode::iterateListBackwards(VNVisitor& v) { AstNode* nodep = this; while (nodep->m_nextp) nodep = nodep->m_nextp; while (nodep) { @@ -866,14 +847,14 @@ void AstNode::iterateListBackwards(AstNVisitor& v) { } } -void AstNode::iterateChildrenBackwards(AstNVisitor& v) { +void AstNode::iterateChildrenBackwards(VNVisitor& v) { if (m_op1p) m_op1p->iterateListBackwards(v); if (m_op2p) m_op2p->iterateListBackwards(v); if (m_op3p) m_op3p->iterateListBackwards(v); if (m_op4p) m_op4p->iterateListBackwards(v); } -void AstNode::iterateAndNextConst(AstNVisitor& v) { +void AstNode::iterateAndNextConst(VNVisitor& v) { // Keep following the current list even if edits change it AstNode* nodep = this; do { @@ -884,7 +865,7 @@ void AstNode::iterateAndNextConst(AstNVisitor& v) { } while (nodep); } -AstNode* AstNode::iterateSubtreeReturnEdits(AstNVisitor& v) { +AstNode* AstNode::iterateSubtreeReturnEdits(VNVisitor& v) { // Some visitors perform tree edits (such as V3Const), and may even // replace/delete the exact nodep that the visitor is called with. If // this happens, the parent will lose the handle to the node that was @@ -1138,6 +1119,7 @@ void AstNode::dumpTreeFile(const string& filename, bool append, bool doDump, boo } } } + if (doDump && v3Global.opt.debugEmitV()) V3EmitV::debugEmitV(filename + ".v"); if (doCheck && (v3Global.opt.debugCheck() || v3Global.opt.dumpTree())) { // Error check checkTree(); @@ -1239,27 +1221,27 @@ void AstNode::dtypeChgWidthSigned(int width, int widthMin, VSigning numeric) { } } -AstNodeDType* AstNode::findBasicDType(AstBasicDTypeKwd kwd) const { +AstNodeDType* AstNode::findBasicDType(VBasicDTypeKwd kwd) const { // For 'simple' types we use the global directory. These are all unsized. // More advanced types land under the module/task/etc return v3Global.rootp()->typeTablep()->findBasicDType(fileline(), kwd); } AstNodeDType* AstNode::findBitDType(int width, int widthMin, VSigning numeric) const { - return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), AstBasicDTypeKwd::BIT, + return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), VBasicDTypeKwd::BIT, width, widthMin, numeric); } AstNodeDType* AstNode::findLogicDType(int width, int widthMin, VSigning numeric) const { - return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), AstBasicDTypeKwd::LOGIC, + return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), VBasicDTypeKwd::LOGIC, width, widthMin, numeric); } AstNodeDType* AstNode::findLogicRangeDType(const VNumRange& range, int widthMin, VSigning numeric) const { - return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), AstBasicDTypeKwd::LOGIC, + return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), VBasicDTypeKwd::LOGIC, range, widthMin, numeric); } AstNodeDType* AstNode::findBitRangeDType(const VNumRange& range, int widthMin, VSigning numeric) const { - return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), AstBasicDTypeKwd::BIT, + return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), VBasicDTypeKwd::BIT, range, widthMin, numeric); } AstBasicDType* AstNode::findInsertSameDType(AstBasicDType* nodep) { @@ -1276,9 +1258,9 @@ AstNodeDType* AstNode::findVoidDType() const { } //###################################################################### -// AstNDeleter +// VNDeleter -void AstNDeleter::doDeletes() { +void VNDeleter::doDeletes() { for (AstNode* const nodep : m_deleteps) nodep->deleteTree(); m_deleteps.clear(); } diff --git a/src/V3Ast.h b/src/V3Ast.h index 52429b154..5667b5db2 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -27,8 +27,13 @@ #include "V3Broken.h" #include +#include +#include +#include #include #include +#include +#include #include "V3Ast__gen_classes.h" // From ./astgen // Things like: @@ -82,7 +87,7 @@ using MTaskIdSet = std::set; // Set of mtaskIds for Var sorting //###################################################################### -class AstType final { +class VNType final { public: #include "V3Ast__gen_types.h" // From ./astgen // Above include has: @@ -90,18 +95,18 @@ public: // const char* ascii() const {...}; enum en m_e; // cppcheck-suppress uninitVar // responsibility of each subclass - inline AstType() {} + inline VNType() {} // cppcheck-suppress noExplicitConstructor - inline AstType(en _e) + inline VNType(en _e) : m_e{_e} {} - explicit inline AstType(int _e) + explicit inline VNType(int _e) : m_e(static_cast(_e)) {} // Need () or GCC 4.8 false warning operator en() const { return m_e; } }; -inline bool operator==(const AstType& lhs, const AstType& rhs) { return lhs.m_e == rhs.m_e; } -inline bool operator==(const AstType& lhs, AstType::en rhs) { return lhs.m_e == rhs; } -inline bool operator==(AstType::en lhs, const AstType& rhs) { return lhs == rhs.m_e; } -inline std::ostream& operator<<(std::ostream& os, const AstType& rhs) { return os << rhs.ascii(); } +inline bool operator==(const VNType& lhs, const VNType& rhs) { return lhs.m_e == rhs.m_e; } +inline bool operator==(const VNType& lhs, VNType::en rhs) { return lhs.m_e == rhs; } +inline bool operator==(VNType::en lhs, const VNType& rhs) { return lhs == rhs.m_e; } +inline std::ostream& operator<<(std::ostream& os, const VNType& rhs) { return os << rhs.ascii(); } //###################################################################### @@ -215,7 +220,7 @@ inline std::ostream& operator<<(std::ostream& os, const VSigning& rhs) { //###################################################################### -class AstPragmaType final { +class VPragmaType final { public: enum en : uint8_t { ILLEGAL, @@ -231,20 +236,20 @@ public: ENUM_SIZE }; enum en m_e; - inline AstPragmaType() + inline VPragmaType() : m_e{ILLEGAL} {} // cppcheck-suppress noExplicitConstructor - inline AstPragmaType(en _e) + inline VPragmaType(en _e) : m_e{_e} {} - explicit inline AstPragmaType(int _e) + explicit inline VPragmaType(int _e) : m_e(static_cast(_e)) {} // Need () or GCC 4.8 false warning operator en() const { return m_e; } }; -inline bool operator==(const AstPragmaType& lhs, const AstPragmaType& rhs) { +inline bool operator==(const VPragmaType& lhs, const VPragmaType& rhs) { return lhs.m_e == rhs.m_e; } -inline bool operator==(const AstPragmaType& lhs, AstPragmaType::en rhs) { return lhs.m_e == rhs; } -inline bool operator==(AstPragmaType::en lhs, const AstPragmaType& rhs) { return lhs == rhs.m_e; } +inline bool operator==(const VPragmaType& lhs, VPragmaType::en rhs) { return lhs.m_e == rhs; } +inline bool operator==(VPragmaType::en lhs, const VPragmaType& rhs) { return lhs == rhs.m_e; } //###################################################################### @@ -334,7 +339,7 @@ inline bool operator==(VEdgeType::en lhs, const VEdgeType& rhs) { return lhs == //###################################################################### -class AstAttrType final { +class VAttrType final { public: // clang-format off enum en: uint8_t { @@ -367,6 +372,7 @@ public: // VAR_BASE, // V3LinkResolve creates for AstPreSel, V3LinkParam removes VAR_CLOCK_ENABLE, // V3LinkParse moves to AstVar::attrClockEn + VAR_FORCEABLE, // V3LinkParse moves to AstVar::isForceable VAR_PUBLIC, // V3LinkParse moves to AstVar::sigPublic VAR_PUBLIC_FLAT, // V3LinkParse moves to AstVar::sigPublic VAR_PUBLIC_FLAT_RD, // V3LinkParse moves to AstVar::sigPublic @@ -391,7 +397,7 @@ public: "ENUM_NEXT", "ENUM_PREV", "ENUM_NAME", "ENUM_VALID", "MEMBER_BASE", "TYPENAME", - "VAR_BASE", "VAR_CLOCK_ENABLE", "VAR_PUBLIC", + "VAR_BASE", "VAR_CLOCK_ENABLE", "VAR_FORCEABLE", "VAR_PUBLIC", "VAR_PUBLIC_FLAT", "VAR_PUBLIC_FLAT_RD", "VAR_PUBLIC_FLAT_RW", "VAR_ISOLATE_ASSIGNMENTS", "VAR_SC_BV", "VAR_SFORMAT", "VAR_CLOCKER", "VAR_NO_CLOCKER", "VAR_SPLIT_VAR" @@ -399,24 +405,22 @@ public: // clang-format on return names[m_e]; } - inline AstAttrType() + inline VAttrType() : m_e{ILLEGAL} {} // cppcheck-suppress noExplicitConstructor - inline AstAttrType(en _e) + inline VAttrType(en _e) : m_e{_e} {} - explicit inline AstAttrType(int _e) + explicit inline VAttrType(int _e) : m_e(static_cast(_e)) {} // Need () or GCC 4.8 false warning operator en() const { return m_e; } }; -inline bool operator==(const AstAttrType& lhs, const AstAttrType& rhs) { - return lhs.m_e == rhs.m_e; -} -inline bool operator==(const AstAttrType& lhs, AstAttrType::en rhs) { return lhs.m_e == rhs; } -inline bool operator==(AstAttrType::en lhs, const AstAttrType& rhs) { return lhs == rhs.m_e; } +inline bool operator==(const VAttrType& lhs, const VAttrType& rhs) { return lhs.m_e == rhs.m_e; } +inline bool operator==(const VAttrType& lhs, VAttrType::en rhs) { return lhs.m_e == rhs; } +inline bool operator==(VAttrType::en lhs, const VAttrType& rhs) { return lhs == rhs.m_e; } //###################################################################### -class AstBasicDTypeKwd final { +class VBasicDTypeKwd final { public: enum en : uint8_t { UNKNOWN, @@ -463,17 +467,16 @@ public: return names[m_e]; } static void selfTest() { - UASSERT(0 == strcmp(AstBasicDTypeKwd(_ENUM_MAX).ascii(), " MAX"), - "SelfTest: Enum mismatch"); - UASSERT(0 == strcmp(AstBasicDTypeKwd(_ENUM_MAX).dpiType(), " MAX"), + UASSERT(0 == strcmp(VBasicDTypeKwd(_ENUM_MAX).ascii(), " MAX"), "SelfTest: Enum mismatch"); + UASSERT(0 == strcmp(VBasicDTypeKwd(_ENUM_MAX).dpiType(), " MAX"), "SelfTest: Enum mismatch"); } - inline AstBasicDTypeKwd() + inline VBasicDTypeKwd() : m_e{UNKNOWN} {} // cppcheck-suppress noExplicitConstructor - inline AstBasicDTypeKwd(en _e) + inline VBasicDTypeKwd(en _e) : m_e{_e} {} - explicit inline AstBasicDTypeKwd(int _e) + explicit inline VBasicDTypeKwd(int _e) : m_e(static_cast(_e)) {} // Need () or GCC 4.8 false warning operator en() const { return m_e; } int width() const { @@ -556,13 +559,13 @@ public: } } }; -inline bool operator==(const AstBasicDTypeKwd& lhs, const AstBasicDTypeKwd& rhs) { +inline bool operator==(const VBasicDTypeKwd& lhs, const VBasicDTypeKwd& rhs) { return lhs.m_e == rhs.m_e; } -inline bool operator==(const AstBasicDTypeKwd& lhs, AstBasicDTypeKwd::en rhs) { +inline bool operator==(const VBasicDTypeKwd& lhs, VBasicDTypeKwd::en rhs) { return lhs.m_e == rhs; } -inline bool operator==(AstBasicDTypeKwd::en lhs, const AstBasicDTypeKwd& rhs) { +inline bool operator==(VBasicDTypeKwd::en lhs, const VBasicDTypeKwd& rhs) { return lhs == rhs.m_e; } @@ -685,7 +688,7 @@ inline std::ostream& operator<<(std::ostream& os, const VJoinType& rhs) { //###################################################################### -class AstVarType final { +class VVarType final { public: enum en : uint8_t { UNKNOWN, @@ -710,12 +713,12 @@ public: MEMBER }; enum en m_e; - inline AstVarType() + inline VVarType() : m_e{UNKNOWN} {} // cppcheck-suppress noExplicitConstructor - inline AstVarType(en _e) + inline VVarType(en _e) : m_e{_e} {} - explicit inline AstVarType(int _e) + explicit inline VVarType(int _e) : m_e(static_cast(_e)) {} // Need () or GCC 4.8 false warning operator en() const { return m_e; } const char* ascii() const { @@ -744,10 +747,10 @@ public: return (m_e == BLOCKTEMP || m_e == MODULETEMP || m_e == STMTTEMP || m_e == XTEMP); } }; -inline bool operator==(const AstVarType& lhs, const AstVarType& rhs) { return lhs.m_e == rhs.m_e; } -inline bool operator==(const AstVarType& lhs, AstVarType::en rhs) { return lhs.m_e == rhs; } -inline bool operator==(AstVarType::en lhs, const AstVarType& rhs) { return lhs == rhs.m_e; } -inline std::ostream& operator<<(std::ostream& os, const AstVarType& rhs) { +inline bool operator==(const VVarType& lhs, const VVarType& rhs) { return lhs.m_e == rhs.m_e; } +inline bool operator==(const VVarType& lhs, VVarType::en rhs) { return lhs.m_e == rhs; } +inline bool operator==(VVarType::en lhs, const VVarType& rhs) { return lhs == rhs.m_e; } +inline std::ostream& operator<<(std::ostream& os, const VVarType& rhs) { return os << rhs.ascii(); } @@ -879,7 +882,7 @@ inline bool operator==(VCaseType::en lhs, const VCaseType& rhs) { return lhs == //###################################################################### -class AstDisplayType final { +class VDisplayType final { public: enum en : uint8_t { DT_DISPLAY, @@ -892,12 +895,12 @@ public: DT_FATAL }; enum en m_e; - AstDisplayType() + VDisplayType() : m_e{DT_DISPLAY} {} // cppcheck-suppress noExplicitConstructor - AstDisplayType(en _e) + VDisplayType(en _e) : m_e{_e} {} - explicit inline AstDisplayType(int _e) + explicit inline VDisplayType(int _e) : m_e(static_cast(_e)) {} // Need () or GCC 4.8 false warning operator en() const { return m_e; } bool addNewline() const { return m_e != DT_WRITE; } @@ -908,15 +911,11 @@ public: return names[m_e]; } }; -inline bool operator==(const AstDisplayType& lhs, const AstDisplayType& rhs) { +inline bool operator==(const VDisplayType& lhs, const VDisplayType& rhs) { return lhs.m_e == rhs.m_e; } -inline bool operator==(const AstDisplayType& lhs, AstDisplayType::en rhs) { - return lhs.m_e == rhs; -} -inline bool operator==(AstDisplayType::en lhs, const AstDisplayType& rhs) { - return lhs == rhs.m_e; -} +inline bool operator==(const VDisplayType& lhs, VDisplayType::en rhs) { return lhs.m_e == rhs; } +inline bool operator==(VDisplayType::en lhs, const VDisplayType& rhs) { return lhs == rhs.m_e; } //###################################################################### @@ -1080,7 +1079,7 @@ public: const int m_width; // From AstNodeDType: Bit width of operation const int m_widthMin; // From AstNodeDType: If unsized, bitwidth of minimum implementation const VSigning m_numeric; // From AstNodeDType: Node is signed - const AstBasicDTypeKwd m_keyword; // From AstBasicDType: What keyword created basic type + const VBasicDTypeKwd m_keyword; // From AstBasicDType: What keyword created basic type const VNumRange m_nrange; // From AstBasicDType: Numeric msb/lsb (if non-opaque keyword) bool operator==(const VBasicTypeKey& rhs) const { return m_width == rhs.m_width && m_widthMin == rhs.m_widthMin && m_numeric == rhs.m_numeric @@ -1099,7 +1098,7 @@ public: if (!(m_nrange == rhs.m_nrange)) return false; // lhs > rhs return false; } - VBasicTypeKey(int width, int widthMin, VSigning numeric, AstBasicDTypeKwd kwd, + VBasicTypeKey(int width, int widthMin, VSigning numeric, VBasicDTypeKwd kwd, const VNumRange& nrange) : m_width{width} , m_widthMin{widthMin} @@ -1151,13 +1150,13 @@ public: // // Where AstNode->user2() is going to be used, for example, you write: // -// AstUser2InUse m_userres; +// VNUser2InUse m_userres; // // This will clear the tree, and prevent another visitor from clobbering // user2. When the member goes out of scope it will be automagically // freed up. -class AstUserInUseBase VL_NOT_FINAL { +class VNUserInUseBase VL_NOT_FINAL { protected: static void allocate(int id, uint32_t& cntGblRef, bool& userBusyRef) { // Perhaps there's still a AstUserInUse in scope for this? @@ -1188,58 +1187,58 @@ protected: // We let AstNode peek into here, because when under low optimization even // an accessor would be way too slow. // clang-format off -class AstUser1InUse final : AstUserInUseBase { +class VNUser1InUse final : VNUserInUseBase { protected: friend class AstNode; static uint32_t s_userCntGbl; // Count of which usage of userp() this is static bool s_userBusy; // Count is in use public: - AstUser1InUse() { allocate(1, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } - ~AstUser1InUse() { free (1, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + VNUser1InUse() { allocate(1, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + ~VNUser1InUse() { free (1, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void clear() { clearcnt(1, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void check() { checkcnt(1, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } }; -class AstUser2InUse final : AstUserInUseBase { +class VNUser2InUse final : VNUserInUseBase { protected: friend class AstNode; static uint32_t s_userCntGbl; // Count of which usage of userp() this is static bool s_userBusy; // Count is in use public: - AstUser2InUse() { allocate(2, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } - ~AstUser2InUse() { free (2, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + VNUser2InUse() { allocate(2, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + ~VNUser2InUse() { free (2, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void clear() { clearcnt(2, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void check() { checkcnt(2, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } }; -class AstUser3InUse final : AstUserInUseBase { +class VNUser3InUse final : VNUserInUseBase { protected: friend class AstNode; static uint32_t s_userCntGbl; // Count of which usage of userp() this is static bool s_userBusy; // Count is in use public: - AstUser3InUse() { allocate(3, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } - ~AstUser3InUse() { free (3, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + VNUser3InUse() { allocate(3, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + ~VNUser3InUse() { free (3, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void clear() { clearcnt(3, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void check() { checkcnt(3, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } }; -class AstUser4InUse final : AstUserInUseBase { +class VNUser4InUse final : VNUserInUseBase { protected: friend class AstNode; static uint32_t s_userCntGbl; // Count of which usage of userp() this is static bool s_userBusy; // Count is in use public: - AstUser4InUse() { allocate(4, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } - ~AstUser4InUse() { free (4, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + VNUser4InUse() { allocate(4, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + ~VNUser4InUse() { free (4, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void clear() { clearcnt(4, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void check() { checkcnt(4, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } }; -class AstUser5InUse final : AstUserInUseBase { +class VNUser5InUse final : VNUserInUseBase { protected: friend class AstNode; static uint32_t s_userCntGbl; // Count of which usage of userp() this is static bool s_userBusy; // Count is in use public: - AstUser5InUse() { allocate(5, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } - ~AstUser5InUse() { free (5, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + VNUser5InUse() { allocate(5, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } + ~VNUser5InUse() { free (5, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void clear() { clearcnt(5, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } static void check() { checkcnt(5, s_userCntGbl/*ref*/, s_userBusy/*ref*/); } }; @@ -1251,7 +1250,7 @@ public: // nodes needs to be deferred to a later time, because pointers to the // removed nodes might still exist. -class AstNDeleter VL_NOT_FINAL { +class VNDeleter VL_NOT_FINAL { // MEMBERS std::vector m_deleteps; // Nodes to delete @@ -1268,14 +1267,14 @@ public: void doDeletes(); // Do the deletions on destruction - virtual ~AstNDeleter() { doDeletes(); } + virtual ~VNDeleter() { doDeletes(); } }; //###################################################################### -// AstNVisitor -- Allows new functions to be called on each node +// VNVisitor -- Allows new functions to be called on each node // type without changing the base classes. See "Modern C++ Design". -class AstNVisitor VL_NOT_FINAL : public AstNDeleter { +class VNVisitor VL_NOT_FINAL : public VNDeleter { friend class AstNode; public: @@ -1293,6 +1292,8 @@ public: void iterateAndNextNull(AstNode* nodep); /// Call visit()s on const nodep (maybe nullptr) and nodep's nextp() list void iterateAndNextConstNull(AstNode* nodep); + /// Call visit()s on const nodep (maybe nullptr) and nodep's nextp() list, in reverse order + void iterateAndNextConstNullBackwards(AstNode* nodep); /// Return edited nodep; see comments in V3Ast.cpp AstNode* iterateSubtreeReturnEdits(AstNode* nodep); @@ -1303,10 +1304,10 @@ public: }; //###################################################################### -// AstNRelinker -- Holds the state of a unlink so a new node can be +// VNRelinker -- Holds the state of a unlink so a new node can be // added at the same point. -class AstNRelinker final { +class VNRelinker final { protected: friend class AstNode; enum RelinkWhatEn : uint8_t { @@ -1323,12 +1324,12 @@ protected: AstNode** m_iterpp = nullptr; public: - AstNRelinker() = default; + VNRelinker() = default; void relink(AstNode* newp); AstNode* oldp() const { return m_oldp; } void dump(std::ostream& str = std::cout) const; }; -inline std::ostream& operator<<(std::ostream& os, const AstNRelinker& rhs) { +inline std::ostream& operator<<(std::ostream& os, const VNRelinker& rhs) { rhs.dump(os); return os; } @@ -1356,17 +1357,18 @@ public: class AstNode VL_NOT_FINAL { // v ASTNODE_PREFETCH depends on below ordering of members - AstNode* m_nextp; // Next peer in the parent's list - AstNode* m_backp; // Node that points to this one (via next/op1/op2/...) - AstNode* m_op1p; // Generic pointer 1 - AstNode* m_op2p; // Generic pointer 2 - AstNode* m_op3p; // Generic pointer 3 - AstNode* m_op4p; // Generic pointer 4 - AstNode** m_iterpp; // Pointer to node iterating on, change it if we replace this node. - const AstType m_type; // Node sub-type identifier + AstNode* m_nextp = nullptr; // Next peer in the parent's list + AstNode* m_backp = nullptr; // Node that points to this one (via next/op1/op2/...) + AstNode* m_op1p = nullptr; // Generic pointer 1 + AstNode* m_op2p = nullptr; // Generic pointer 2 + AstNode* m_op3p = nullptr; // Generic pointer 3 + AstNode* m_op4p = nullptr; // Generic pointer 4 + AstNode** m_iterpp + = nullptr; // Pointer to node iterating on, change it if we replace this node. + const VNType m_type; // Node sub-type identifier // ^ ASTNODE_PREFETCH depends on above ordering of members - // AstType is 2 bytes, so we can stick another 6 bytes after it to utilize what would + // VNType is 2 bytes, so we can stick another 6 bytes after it to utilize what would // otherwise be padding (on a 64-bit system). We stick the attribute flags, broken state, // and the clone count here. @@ -1384,7 +1386,7 @@ class AstNode VL_NOT_FINAL { // field masking resulting in unnecessary read-modify-write ops. uint8_t m_brokenState = 0; - int m_cloneCnt; // Sequence number for when last clone was made + int m_cloneCnt = 0; // Sequence number for when last clone was made #if defined(__x86_64__) && defined(__gnu_linux__) // Only assert this on known platforms, as it only affects performance, not correctness @@ -1393,7 +1395,7 @@ class AstNode VL_NOT_FINAL { "packing requires padding"); #endif - AstNodeDType* m_dtypep; // Data type of output or assignment (etc) + AstNodeDType* m_dtypep = nullptr; // Data type of output or assignment (etc) AstNode* m_headtailp; // When at begin/end of list, the opposite end of the list FileLine* m_fileline; // Where it was declared vluint64_t m_editCount; // When it was last edited @@ -1401,20 +1403,21 @@ class AstNode VL_NOT_FINAL { // Global edit counter, last value for printing * near node #s static vluint64_t s_editCntLast; - AstNode* m_clonep; // Pointer to clone of/ source of this module (for *LAST* cloneTree() ONLY) + AstNode* m_clonep + = nullptr; // Pointer to clone of/ source of this module (for *LAST* cloneTree() ONLY) static int s_cloneCntGbl; // Count of which userp is set // This member ordering both allows 64 bit alignment and puts associated data together - VNUser m_user1u; // Contains any information the user iteration routine wants - uint32_t m_user1Cnt; // Mark of when userp was set - uint32_t m_user2Cnt; // Mark of when userp was set - VNUser m_user2u; // Contains any information the user iteration routine wants - VNUser m_user3u; // Contains any information the user iteration routine wants - uint32_t m_user3Cnt; // Mark of when userp was set - uint32_t m_user4Cnt; // Mark of when userp was set - VNUser m_user4u; // Contains any information the user iteration routine wants - VNUser m_user5u; // Contains any information the user iteration routine wants - uint32_t m_user5Cnt; // Mark of when userp was set + VNUser m_user1u = VNUser{0}; // Contains any information the user iteration routine wants + uint32_t m_user1Cnt = 0; // Mark of when userp was set + uint32_t m_user2Cnt = 0; // Mark of when userp was set + VNUser m_user2u = VNUser{0}; // Contains any information the user iteration routine wants + VNUser m_user3u = VNUser{0}; // Contains any information the user iteration routine wants + uint32_t m_user3Cnt = 0; // Mark of when userp was set + uint32_t m_user4Cnt = 0; // Mark of when userp was set + VNUser m_user4u = VNUser{0}; // Contains any information the user iteration routine wants + VNUser m_user5u = VNUser{0}; // Contains any information the user iteration routine wants + uint32_t m_user5Cnt = 0; // Mark of when userp was set // METHODS void op1p(AstNode* nodep) { @@ -1453,7 +1456,7 @@ public: protected: // CONSTRUCTORS - AstNode(AstType t, FileLine* fl); + AstNode(VNType t, FileLine* fl); virtual AstNode* clone() = 0; // Generally, cloneTree is what you want instead virtual void cloneRelink() {} void cloneRelinkTree(); @@ -1492,7 +1495,7 @@ protected: public: // ACCESSORS - inline AstType type() const { return m_type; } + inline VNType type() const { return m_type; } const char* typeName() const { return type().ascii(); } // See also prettyTypeName AstNode* nextp() const { return m_nextp; } AstNode* backp() const { return m_backp; } @@ -1594,73 +1597,73 @@ public: // clang-format off VNUser user1u() const { // Slows things down measurably, so disabled by default - //UASSERT_STATIC(AstUser1InUse::s_userBusy, "userp set w/o busy"); - return ((m_user1Cnt==AstUser1InUse::s_userCntGbl) ? m_user1u : VNUser(0)); + //UASSERT_STATIC(VNUser1InUse::s_userBusy, "userp set w/o busy"); + return ((m_user1Cnt==VNUser1InUse::s_userCntGbl) ? m_user1u : VNUser(0)); } AstNode* user1p() const { return user1u().toNodep(); } - void user1u(const VNUser& user) { m_user1u=user; m_user1Cnt=AstUser1InUse::s_userCntGbl; } + void user1u(const VNUser& user) { m_user1u=user; m_user1Cnt=VNUser1InUse::s_userCntGbl; } void user1p(void* userp) { user1u(VNUser(userp)); } int user1() const { return user1u().toInt(); } void user1(int val) { user1u(VNUser(val)); } int user1Inc(int val=1) { int v=user1(); user1(v+val); return v; } int user1SetOnce() { int v=user1(); if (!v) user1(1); return v; } // Better for cache than user1Inc() - static void user1ClearTree() { AstUser1InUse::clear(); } // Clear userp()'s across the entire tree + static void user1ClearTree() { VNUser1InUse::clear(); } // Clear userp()'s across the entire tree VNUser user2u() const { // Slows things down measurably, so disabled by default - //UASSERT_STATIC(AstUser2InUse::s_userBusy, "userp set w/o busy"); - return ((m_user2Cnt==AstUser2InUse::s_userCntGbl) ? m_user2u : VNUser(0)); + //UASSERT_STATIC(VNUser2InUse::s_userBusy, "userp set w/o busy"); + return ((m_user2Cnt==VNUser2InUse::s_userCntGbl) ? m_user2u : VNUser(0)); } AstNode* user2p() const { return user2u().toNodep(); } - void user2u(const VNUser& user) { m_user2u=user; m_user2Cnt=AstUser2InUse::s_userCntGbl; } + void user2u(const VNUser& user) { m_user2u=user; m_user2Cnt=VNUser2InUse::s_userCntGbl; } void user2p(void* userp) { user2u(VNUser(userp)); } int user2() const { return user2u().toInt(); } void user2(int val) { user2u(VNUser(val)); } int user2Inc(int val=1) { int v=user2(); user2(v+val); return v; } int user2SetOnce() { int v=user2(); if (!v) user2(1); return v; } // Better for cache than user2Inc() - static void user2ClearTree() { AstUser2InUse::clear(); } // Clear userp()'s across the entire tree + static void user2ClearTree() { VNUser2InUse::clear(); } // Clear userp()'s across the entire tree VNUser user3u() const { // Slows things down measurably, so disabled by default - //UASSERT_STATIC(AstUser3InUse::s_userBusy, "userp set w/o busy"); - return ((m_user3Cnt==AstUser3InUse::s_userCntGbl) ? m_user3u : VNUser(0)); + //UASSERT_STATIC(VNUser3InUse::s_userBusy, "userp set w/o busy"); + return ((m_user3Cnt==VNUser3InUse::s_userCntGbl) ? m_user3u : VNUser(0)); } AstNode* user3p() const { return user3u().toNodep(); } - void user3u(const VNUser& user) { m_user3u=user; m_user3Cnt=AstUser3InUse::s_userCntGbl; } + void user3u(const VNUser& user) { m_user3u=user; m_user3Cnt=VNUser3InUse::s_userCntGbl; } void user3p(void* userp) { user3u(VNUser(userp)); } int user3() const { return user3u().toInt(); } void user3(int val) { user3u(VNUser(val)); } int user3Inc(int val=1) { int v=user3(); user3(v+val); return v; } int user3SetOnce() { int v=user3(); if (!v) user3(1); return v; } // Better for cache than user3Inc() - static void user3ClearTree() { AstUser3InUse::clear(); } // Clear userp()'s across the entire tree + static void user3ClearTree() { VNUser3InUse::clear(); } // Clear userp()'s across the entire tree VNUser user4u() const { // Slows things down measurably, so disabled by default - //UASSERT_STATIC(AstUser4InUse::s_userBusy, "userp set w/o busy"); - return ((m_user4Cnt==AstUser4InUse::s_userCntGbl) ? m_user4u : VNUser(0)); + //UASSERT_STATIC(VNUser4InUse::s_userBusy, "userp set w/o busy"); + return ((m_user4Cnt==VNUser4InUse::s_userCntGbl) ? m_user4u : VNUser(0)); } AstNode* user4p() const { return user4u().toNodep(); } - void user4u(const VNUser& user) { m_user4u=user; m_user4Cnt=AstUser4InUse::s_userCntGbl; } + void user4u(const VNUser& user) { m_user4u=user; m_user4Cnt=VNUser4InUse::s_userCntGbl; } void user4p(void* userp) { user4u(VNUser(userp)); } int user4() const { return user4u().toInt(); } void user4(int val) { user4u(VNUser(val)); } int user4Inc(int val=1) { int v=user4(); user4(v+val); return v; } int user4SetOnce() { int v=user4(); if (!v) user4(1); return v; } // Better for cache than user4Inc() - static void user4ClearTree() { AstUser4InUse::clear(); } // Clear userp()'s across the entire tree + static void user4ClearTree() { VNUser4InUse::clear(); } // Clear userp()'s across the entire tree VNUser user5u() const { // Slows things down measurably, so disabled by default - //UASSERT_STATIC(AstUser5InUse::s_userBusy, "userp set w/o busy"); - return ((m_user5Cnt==AstUser5InUse::s_userCntGbl) ? m_user5u : VNUser(0)); + //UASSERT_STATIC(VNUser5InUse::s_userBusy, "userp set w/o busy"); + return ((m_user5Cnt==VNUser5InUse::s_userCntGbl) ? m_user5u : VNUser(0)); } AstNode* user5p() const { return user5u().toNodep(); } - void user5u(const VNUser& user) { m_user5u=user; m_user5Cnt=AstUser5InUse::s_userCntGbl; } + void user5u(const VNUser& user) { m_user5u=user; m_user5Cnt=VNUser5InUse::s_userCntGbl; } void user5p(void* userp) { user5u(VNUser(userp)); } int user5() const { return user5u().toInt(); } void user5(int val) { user5u(VNUser(val)); } int user5Inc(int val=1) { int v=user5(); user5(v+val); return v; } int user5SetOnce() { int v=user5(); if (!v) user5(1); return v; } // Better for cache than user5Inc() - static void user5ClearTree() { AstUser5InUse::clear(); } // Clear userp()'s across the entire tree + static void user5ClearTree() { VNUser5InUse::clear(); } // Clear userp()'s across the entire tree // clang-format on vluint64_t editCount() const { return m_editCount; } @@ -1686,7 +1689,7 @@ public: editCountInc(); } } - void dtypeFrom(AstNode* fromp) { + void dtypeFrom(const AstNode* fromp) { if (fromp) dtypep(fromp->dtypep()); } void dtypeChgSigned(bool flag = true); @@ -1714,13 +1717,13 @@ public: void dtypeSetVoid() { dtypep(findVoidDType()); } // Data type locators - AstNodeDType* findBitDType() { return findBasicDType(AstBasicDTypeKwd::LOGIC); } - AstNodeDType* findDoubleDType() { return findBasicDType(AstBasicDTypeKwd::DOUBLE); } - AstNodeDType* findStringDType() { return findBasicDType(AstBasicDTypeKwd::STRING); } - AstNodeDType* findSigned32DType() { return findBasicDType(AstBasicDTypeKwd::INTEGER); } - AstNodeDType* findUInt32DType() { return findBasicDType(AstBasicDTypeKwd::UINT32); } - AstNodeDType* findUInt64DType() { return findBasicDType(AstBasicDTypeKwd::UINT64); } - AstNodeDType* findCHandleDType() { return findBasicDType(AstBasicDTypeKwd::CHANDLE); } + AstNodeDType* findBitDType() { return findBasicDType(VBasicDTypeKwd::LOGIC); } + AstNodeDType* findDoubleDType() { return findBasicDType(VBasicDTypeKwd::DOUBLE); } + AstNodeDType* findStringDType() { return findBasicDType(VBasicDTypeKwd::STRING); } + AstNodeDType* findSigned32DType() { return findBasicDType(VBasicDTypeKwd::INTEGER); } + AstNodeDType* findUInt32DType() { return findBasicDType(VBasicDTypeKwd::UINT32); } + AstNodeDType* findUInt64DType() { return findBasicDType(VBasicDTypeKwd::UINT64); } + AstNodeDType* findCHandleDType() { return findBasicDType(VBasicDTypeKwd::CHANDLE); } AstNodeDType* findEmptyQueueDType() const; AstNodeDType* findVoidDType() const; AstNodeDType* findQueueIndexDType() const; @@ -1729,7 +1732,7 @@ public: AstNodeDType* findLogicRangeDType(const VNumRange& range, int widthMin, VSigning numeric) const; AstNodeDType* findBitRangeDType(const VNumRange& range, int widthMin, VSigning numeric) const; - AstNodeDType* findBasicDType(AstBasicDTypeKwd kwd) const; + AstNodeDType* findBasicDType(VBasicDTypeKwd kwd) const; static AstBasicDType* findInsertSameDType(AstBasicDType* nodep); // METHODS - dump and error @@ -1758,12 +1761,12 @@ public: } void addHereThisAsNext(AstNode* newp); // Adds at old place of this, this becomes next void replaceWith(AstNode* newp); // Replace current node in tree with new node - AstNode* unlinkFrBack(AstNRelinker* linkerp + AstNode* unlinkFrBack(VNRelinker* linkerp = nullptr); // Unlink this from whoever points to it. // Unlink this from whoever points to it, keep entire next list with unlinked node - AstNode* unlinkFrBackWithNext(AstNRelinker* linkerp = nullptr); + AstNode* unlinkFrBackWithNext(VNRelinker* linkerp = nullptr); void swapWith(AstNode* bp); - void relink(AstNRelinker* linkerp); // Generally use linker->relink() instead + void relink(VNRelinker* linkerp); // Generally use linker->relink() instead void cloneRelinkNode() { cloneRelink(); } // Iterate and insert - assumes tree format virtual void addNextStmt(AstNode* newp, @@ -1826,33 +1829,44 @@ public: virtual AstNodeDType* getChild2DTypep() const { return nullptr; } // Another AstNode* may have a pointer into this node, other then normal front/back/etc. virtual bool maybePointedTo() const { return false; } + // Don't reclaim this node in V3Dead + virtual bool undead() const { return false; } + // Check if node is consistent, return nullptr if ok, else reason string virtual const char* broken() const { return nullptr; } // INVOKERS - virtual void accept(AstNVisitor& v) = 0; + virtual void accept(VNVisitor& v) = 0; protected: - // All AstNVisitor related functions are called as methods off the visitor - friend class AstNVisitor; - // Use instead AstNVisitor::iterateChildren - void iterateChildren(AstNVisitor& v); - // Use instead AstNVisitor::iterateChildrenBackwards - void iterateChildrenBackwards(AstNVisitor& v); - // Use instead AstNVisitor::iterateChildrenConst - void iterateChildrenConst(AstNVisitor& v); - // Use instead AstNVisitor::iterateAndNextNull - void iterateAndNext(AstNVisitor& v); - // Use instead AstNVisitor::iterateAndNextConstNull - void iterateAndNextConst(AstNVisitor& v); - // Use instead AstNVisitor::iterateSubtreeReturnEdits - AstNode* iterateSubtreeReturnEdits(AstNVisitor& v); + // All VNVisitor related functions are called as methods off the visitor + friend class VNVisitor; + // Use instead VNVisitor::iterateChildren + void iterateChildren(VNVisitor& v); + // Use instead VNVisitor::iterateChildrenBackwards + void iterateChildrenBackwards(VNVisitor& v); + // Use instead VNVisitor::iterateChildrenConst + void iterateChildrenConst(VNVisitor& v); + // Use instead VNVisitor::iterateAndNextNull + void iterateAndNext(VNVisitor& v); + // Use instead VNVisitor::iterateAndNextConstNull + void iterateAndNextConst(VNVisitor& v); + // Use instead VNVisitor::iterateSubtreeReturnEdits + AstNode* iterateSubtreeReturnEdits(VNVisitor& v); private: - void iterateListBackwards(AstNVisitor& v); + void iterateListBackwards(VNVisitor& v); // For internal use only. + // Note: specializations for particular node types are provided by 'astgen' template inline static bool privateTypeTest(const AstNode* nodep); + // For internal use only. + // Note: specializations for particular node types are provided below + template inline static bool privateMayBeUnder(const AstNode* nodep) { + return true; + } + + // For internal use only. template constexpr static bool uselessCast() { using NonRef = typename std::remove_reference::type; using NonPtr = typename std::remove_pointer::type; @@ -1860,6 +1874,7 @@ private: return std::is_base_of::value; } + // For internal use only. template constexpr static bool impossibleCast() { using NonRef = typename std::remove_reference::type; using NonPtr = typename std::remove_pointer::type; @@ -1906,11 +1921,120 @@ public: << "'"); return reinterpret_cast(nodep); } + + // Predicate that returns true if the given 'nodep' might have a descendant of type 'T_Node'. + // This is conservative and is used to speed up traversals. + template inline static bool mayBeUnder(const AstNode* nodep) { + static_assert(!std::is_const::value, + "Type parameter 'T_Node' should not be const qualified"); + static_assert(std::is_base_of::value, + "Type parameter 'T_Node' must be a subtype of AstNode"); + return privateMayBeUnder(nodep); + } + +private: + template + static void foreachImpl( + // Using std::conditional for const correctness in the public 'foreach' functions + typename std::conditional::value, const AstNode*, AstNode*>::type + nodep, + std::function f) { + + // Note: Using a loop to iterate the nextp() chain, instead of tail recursion, because + // debug builds don't eliminate tail calls, causing stack overflow on long lists of nodes. + do { + // Prefetch children and next + ASTNODE_PREFETCH(nodep->op1p()); + ASTNODE_PREFETCH(nodep->op2p()); + ASTNODE_PREFETCH(nodep->op3p()); + ASTNODE_PREFETCH(nodep->op4p()); + if /* TODO: 'constexpr' in C++17 */ (VisitNext) ASTNODE_PREFETCH(nodep->nextp()); + + // Apply function in pre-order + if (privateTypeTest::type>(nodep)) { + f(static_cast(nodep)); + } + + // Traverse children (including their 'nextp()' chains), unless futile + if (mayBeUnder::type>(nodep)) { + if (AstNode* const op1p = nodep->op1p()) foreachImpl(op1p, f); + if (AstNode* const op2p = nodep->op2p()) foreachImpl(op2p, f); + if (AstNode* const op3p = nodep->op3p()) foreachImpl(op3p, f); + if (AstNode* const op4p = nodep->op4p()) foreachImpl(op4p, f); + } + + // Traverse 'nextp()' chain if requested + if /* TODO: 'constexpr' in C++17 */ (VisitNext) { + nodep = nodep->nextp(); + } else { + break; + } + } while (nodep); + } + +public: + // Traverse subtree and call given function 'f' in pre-order on each node that has type 'T'. + // Prefer 'foreach' over simple VNVisitor that only needs to handle a single (or a few) node + // types, as it's easier to write, but more importantly, the dispatch to the operation function + // in 'foreach' should be completely predictable by branch target caches in modern CPUs, + // while it is basically unpredictable for VNVisitor. + template void foreach (std::function f) { + static_assert(!std::is_const::value, + "Type parameter 'T_Node' should not be const qualified"); + static_assert(std::is_base_of::value, + "Type parameter 'T_Node' must be a subtype of AstNode"); + foreachImpl(this, f); + } + + // Same as above, but for 'const' nodes + template void foreach (std::function f) const { + static_assert(!std::is_const::value, + "Type parameter 'T_Node' should not be const qualified"); + static_assert(std::is_base_of::value, + "Type parameter 'T_Node' must be a subtype of AstNode"); + foreachImpl(this, f); + } + + // Same as 'foreach' but also follows 'this->nextp()' + template void foreachAndNext(std::function f) { + static_assert(!std::is_const::value, + "Type parameter 'T_Node' should not be const qualified"); + static_assert(std::is_base_of::value, + "Type parameter 'T_Node' must be a subtype of AstNode"); + foreachImpl(this, f); + } + + // Same as 'foreach' but also follows 'this->nextp()' + template void foreachAndNext(std::function f) const { + static_assert(!std::is_const::value, + "Type parameter 'T_Node' should not be const qualified"); + static_assert(std::is_base_of::value, + "Type parameter 'T_Node' must be a subtype of AstNode"); + foreachImpl(this, f); + } + + int nodeCount() const { + // TODO: this should really return size_t, but need to fix use sites + int count = 0; + this->foreach([&count](const AstNode*) { ++count; }); + return count; + } }; -// Specialisations of privateIs/privateCast +// Specialisations of privateTypeTest #include "V3Ast__gen_impl.h" // From ./astgen +// Specializations of privateMayBeUnder +template <> inline bool AstNode::privateMayBeUnder(const AstNode* nodep) { + return !VN_IS(nodep, NodeStmt) && !VN_IS(nodep, NodeMath); +} +template <> inline bool AstNode::privateMayBeUnder(const AstNode* nodep) { + return !VN_IS(nodep, NodeMath); +} +template <> inline bool AstNode::privateMayBeUnder(const AstNode* nodep) { + return !VN_IS(nodep, NodeStmt) && !VN_IS(nodep, NodeMath); +} + inline std::ostream& operator<<(std::ostream& os, const AstNode* rhs) { if (!rhs) { os << "nullptr"; @@ -1919,9 +2043,50 @@ inline std::ostream& operator<<(std::ostream& os, const AstNode* rhs) { } return os; } -inline void AstNRelinker::relink(AstNode* newp) { newp->AstNode::relink(this); } +inline void VNRelinker::relink(AstNode* newp) { newp->AstNode::relink(this); } //###################################################################### + +// VNRef is std::reference_wrapper that can only hold AstNode subtypes +template // +class VNRef final : public std::reference_wrapper { + static_assert(std::is_base_of::value, + "Type parameter 'T_Node' must be a subtype of AstNode"); + +public: + template + VNRef(U&& x) + : std::reference_wrapper{x} {} + + VNRef(const VNRef& other) noexcept + : std::reference_wrapper{other} {} +}; + +static_assert(sizeof(VNRef) == sizeof(std::reference_wrapper), + "VNRef should not contain extra members"); + +// Specializations of std::hash and std::equal_to for VNRef. This in turn +// enables us to use for example std::unordered_set> for +// sets using equality (AstNode::sameTree) rather than identity comparisons, +// without having to copy nodes into the collections. + +// Forward declaration to avoid including V3Hasher.h which needs V3Ast.h (this file). +size_t V3HasherUncachedHash(AstNode&); + +// Specialization of std::hash for VNRef +template // +struct std::hash> final { + size_t operator()(VNRef r) const { return V3HasherUncachedHash(r); } +}; + +// Specialization of std::equal_to for VNRef +template // +struct std::equal_to> final { + size_t operator()(VNRef ra, VNRef rb) const { + return ra.get().sameTree(&(rb.get())); + } +}; + //###################################################################### //=== AstNode* : Derived generic node types @@ -1938,7 +2103,7 @@ inline void AstNRelinker::relink(AstNode* newp) { newp->AstNode::relink(this); } class AstNodeMath VL_NOT_FINAL : public AstNode { // Math -- anything that's part of an expression tree protected: - AstNodeMath(AstType t, FileLine* fl) + AstNodeMath(VNType t, FileLine* fl) : AstNode{t, fl} {} public: @@ -1960,7 +2125,7 @@ public: class AstNodeTermop VL_NOT_FINAL : public AstNodeMath { // Terminal operator -- a operator with no "inputs" protected: - AstNodeTermop(AstType t, FileLine* fl) + AstNodeTermop(VNType t, FileLine* fl) : AstNodeMath{t, fl} {} public: @@ -1968,14 +2133,14 @@ public: // Know no children, and hot function, so skip iterator for speed // See checkTreeIter also that asserts no children // cppcheck-suppress functionConst - void iterateChildren(AstNVisitor& v) {} + void iterateChildren(VNVisitor& v) {} virtual void dump(std::ostream& str) const override; }; class AstNodeUniop VL_NOT_FINAL : public AstNodeMath { // Unary math protected: - AstNodeUniop(AstType t, FileLine* fl, AstNode* lhsp) + AstNodeUniop(VNType t, FileLine* fl, AstNode* lhsp) : AstNodeMath{t, fl} { dtypeFrom(lhsp); setOp1p(lhsp); @@ -2002,7 +2167,7 @@ public: class AstNodeBiop VL_NOT_FINAL : public AstNodeMath { // Binary math protected: - AstNodeBiop(AstType t, FileLine* fl, AstNode* lhs, AstNode* rhs) + AstNodeBiop(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs) : AstNodeMath{t, fl} { setOp1p(lhs); setOp2p(rhs); @@ -2035,7 +2200,7 @@ public: class AstNodeTriop VL_NOT_FINAL : public AstNodeMath { // Trinary math protected: - AstNodeTriop(AstType t, FileLine* fl, AstNode* lhs, AstNode* rhs, AstNode* ths) + AstNodeTriop(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs, AstNode* ths) : AstNodeMath{t, fl} { setOp1p(lhs); setOp2p(rhs); @@ -2069,7 +2234,7 @@ public: class AstNodeQuadop VL_NOT_FINAL : public AstNodeMath { // Quaternary math protected: - AstNodeQuadop(AstType t, FileLine* fl, AstNode* lhs, AstNode* rhs, AstNode* ths, AstNode* fhs) + AstNodeQuadop(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs, AstNode* ths, AstNode* fhs) : AstNodeMath{t, fl} { setOp1p(lhs); setOp2p(rhs); @@ -2107,7 +2272,7 @@ public: class AstNodeBiCom VL_NOT_FINAL : public AstNodeBiop { // Binary math with commutative properties protected: - AstNodeBiCom(AstType t, FileLine* fl, AstNode* lhs, AstNode* rhs) + AstNodeBiCom(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs) : AstNodeBiop{t, fl, lhs, rhs} {} public: @@ -2117,7 +2282,7 @@ public: class AstNodeBiComAsv VL_NOT_FINAL : public AstNodeBiCom { // Binary math with commutative & associative properties protected: - AstNodeBiComAsv(AstType t, FileLine* fl, AstNode* lhs, AstNode* rhs) + AstNodeBiComAsv(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs) : AstNodeBiCom{t, fl, lhs, rhs} {} public: @@ -2126,7 +2291,7 @@ public: class AstNodeCond VL_NOT_FINAL : public AstNodeTriop { protected: - AstNodeCond(AstType t, FileLine* fl, AstNode* condp, AstNode* expr1p, AstNode* expr2p) + AstNodeCond(VNType t, FileLine* fl, AstNode* condp, AstNode* expr1p, AstNode* expr2p) : AstNodeTriop{t, fl, condp, expr1p, expr2p} { if (expr1p) { dtypeFrom(expr1p); @@ -2163,7 +2328,7 @@ private: string m_name; // Name of block bool m_unnamed; // Originally unnamed (name change does not affect this) protected: - AstNodeBlock(AstType t, FileLine* fl, const string& name, AstNode* stmtsp) + AstNodeBlock(VNType t, FileLine* fl, const string& name, AstNode* stmtsp) : AstNode{t, fl} , m_name{name} { addNOp1p(stmtsp); @@ -2184,7 +2349,7 @@ public: class AstNodePreSel VL_NOT_FINAL : public AstNode { // Something that becomes an AstSel protected: - AstNodePreSel(AstType t, FileLine* fl, AstNode* fromp, AstNode* rhs, AstNode* ths) + AstNodePreSel(VNType t, FileLine* fl, AstNode* fromp, AstNode* rhs, AstNode* ths) : AstNode{t, fl} { setOp1p(fromp); setOp2p(rhs); @@ -2208,7 +2373,7 @@ public: class AstNodeProcedure VL_NOT_FINAL : public AstNode { // IEEE procedure: initial, final, always protected: - AstNodeProcedure(AstType t, FileLine* fl, AstNode* bodysp) + AstNodeProcedure(VNType t, FileLine* fl, AstNode* bodysp) : AstNode{t, fl} { addNOp2p(bodysp); } @@ -2226,7 +2391,7 @@ class AstNodeStmt VL_NOT_FINAL : public AstNode { // Statement -- anything that's directly under a function bool m_statement; // Really a statement (e.g. not a function with return) protected: - AstNodeStmt(AstType t, FileLine* fl, bool statement = true) + AstNodeStmt(VNType t, FileLine* fl, bool statement = true) : AstNode{t, fl} , m_statement{statement} {} @@ -2244,7 +2409,7 @@ public: class AstNodeAssign VL_NOT_FINAL : public AstNodeStmt { protected: - AstNodeAssign(AstType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp) + AstNodeAssign(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeStmt{t, fl} { setOp1p(rhsp); setOp2p(lhsp); @@ -2270,7 +2435,7 @@ public: class AstNodeFor VL_NOT_FINAL : public AstNodeStmt { protected: - AstNodeFor(AstType t, FileLine* fl, AstNode* initsp, AstNode* condp, AstNode* incsp, + AstNodeFor(VNType t, FileLine* fl, AstNode* initsp, AstNode* condp, AstNode* incsp, AstNode* bodysp) : AstNodeStmt{t, fl} { addNOp1p(initsp); @@ -2295,7 +2460,7 @@ private: VBranchPred m_branchPred; // Branch prediction as taken/untaken? bool m_isBoundsCheck; // True if this if node was inserted for array bounds checking protected: - AstNodeIf(AstType t, FileLine* fl, AstNode* condp, AstNode* ifsp, AstNode* elsesp) + AstNodeIf(VNType t, FileLine* fl, AstNode* condp, AstNode* ifsp, AstNode* elsesp) : AstNodeStmt{t, fl} { setOp1p(condp); addNOp2p(ifsp); @@ -2323,7 +2488,7 @@ public: class AstNodeCase VL_NOT_FINAL : public AstNodeStmt { protected: - AstNodeCase(AstType t, FileLine* fl, AstNode* exprp, AstNode* casesp) + AstNodeCase(VNType t, FileLine* fl, AstNode* exprp, AstNode* casesp) : AstNodeStmt{t, fl} { setOp1p(exprp); addNOp2p(casesp); @@ -2352,13 +2517,13 @@ private: string m_selfPointer; // Output code object pointer (e.g.: 'this') protected: - AstNodeVarRef(AstType t, FileLine* fl, const string& name, const VAccess& access) + AstNodeVarRef(VNType t, FileLine* fl, const string& name, const VAccess& access) : AstNodeMath{t, fl} , m_access{access} , m_name{name} { this->varp(nullptr); } - AstNodeVarRef(AstType t, FileLine* fl, const string& name, AstVar* varp, const VAccess& access) + AstNodeVarRef(VNType t, FileLine* fl, const string& name, AstVar* varp, const VAccess& access) : AstNodeMath{t, fl} , m_access{access} , m_name{name} { @@ -2389,7 +2554,7 @@ public: // Know no children, and hot function, so skip iterator for speed // See checkTreeIter also that asserts no children // cppcheck-suppress functionConst - void iterateChildren(AstNVisitor& v) {} + void iterateChildren(VNVisitor& v) {} }; class AstNodeText VL_NOT_FINAL : public AstNode { @@ -2398,7 +2563,7 @@ private: protected: // Node that simply puts text into the output stream - AstNodeText(AstType t, FileLine* fl, const string& textp) + AstNodeText(VNType t, FileLine* fl, const string& textp) : AstNode{t, fl} { m_text = textp; // Copy it } @@ -2428,7 +2593,7 @@ private: protected: // CONSTRUCTORS - AstNodeDType(AstType t, FileLine* fl) + AstNodeDType(VNType t, FileLine* fl) : AstNode{t, fl} { m_width = 0; m_widthMin = 0; @@ -2530,7 +2695,7 @@ private: const int m_uniqueNum; protected: - AstNodeUOrStructDType(AstType t, FileLine* fl, VSigning numericUnpack) + AstNodeUOrStructDType(VNType t, FileLine* fl, VSigning numericUnpack) : AstNodeDType{t, fl} , m_uniqueNum{uniqueNumInc()} { // VSigning::NOSIGN overloaded to indicate not packed @@ -2594,7 +2759,7 @@ private: AstNodeDType* m_refDTypep = nullptr; // Elements of this type (after widthing) AstNode* rangenp() const { return op2p(); } // op2 = Array(s) of variable protected: - AstNodeArrayDType(AstType t, FileLine* fl) + AstNodeArrayDType(VNType t, FileLine* fl) : AstNodeDType{t, fl} {} public: @@ -2653,7 +2818,7 @@ public: class AstNodeSel VL_NOT_FINAL : public AstNodeBiop { // Single bit range extraction, perhaps with non-constant selection or array selection protected: - AstNodeSel(AstType t, FileLine* fl, AstNode* fromp, AstNode* bitp) + AstNodeSel(VNType t, FileLine* fl, AstNode* fromp, AstNode* bitp) : AstNodeBiop{t, fl, fromp, bitp} {} public: @@ -2671,7 +2836,7 @@ public: class AstNodeStream VL_NOT_FINAL : public AstNodeBiop { // Verilog {rhs{lhs}} - Note rhsp() is the slice size, not the lhsp() protected: - AstNodeStream(AstType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp) + AstNodeStream(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop{t, fl, lhsp, rhsp} { if (lhsp->dtypep()) dtypeSetLogicSized(lhsp->dtypep()->width(), VSigning::UNSIGNED); } @@ -2690,7 +2855,7 @@ class AstNodeCCall VL_NOT_FINAL : public AstNodeStmt { string m_argTypes; protected: - AstNodeCCall(AstType t, FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr) + AstNodeCCall(VNType t, FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr) : AstNodeStmt{t, fl, true} , m_funcp{funcp} { addNOp2p(argsp); @@ -2712,6 +2877,7 @@ public: virtual bool isPure() const override; virtual bool isOutputter() const override { return !isPure(); } AstCFunc* funcp() const { return m_funcp; } + void funcp(AstCFunc* funcp) { m_funcp = funcp; } void argTypes(const string& str) { m_argTypes = str; } string argTypes() const { return m_argTypes; } // op1p reserved for AstCMethodCall @@ -2741,11 +2907,12 @@ private: bool m_isHideProtected : 1; // Verilog protected bool m_pure : 1; // DPI import pure (vs. virtual pure) bool m_pureVirtual : 1; // Pure virtual + bool m_recursive : 1; // Recusive or part of recursion bool m_underGenerate : 1; // Under generate (for warning) bool m_virtual : 1; // Virtual method in class VLifetime m_lifetime; // Lifetime protected: - AstNodeFTask(AstType t, FileLine* fl, const string& name, AstNode* stmtsp) + AstNodeFTask(VNType t, FileLine* fl, const string& name, AstNode* stmtsp) : AstNode{t, fl} , m_name{name} , m_taskPublic{false} @@ -2765,6 +2932,7 @@ protected: , m_isHideProtected{false} , m_pure{false} , m_pureVirtual{false} + , m_recursive{false} , m_underGenerate{false} , m_virtual{false} { addNOp3p(stmtsp); @@ -2834,6 +3002,8 @@ public: bool pure() const { return m_pure; } void pureVirtual(bool flag) { m_pureVirtual = flag; } bool pureVirtual() const { return m_pureVirtual; } + void recursive(bool flag) { m_recursive = flag; } + bool recursive() const { return m_recursive; } void underGenerate(bool flag) { m_underGenerate = flag; } bool underGenerate() const { return m_underGenerate; } void isVirtual(bool flag) { m_virtual = flag; } @@ -2853,12 +3023,12 @@ private: string m_inlinedDots; // Dotted hierarchy flattened out bool m_pli = false; // Pli system call ($name) protected: - AstNodeFTaskRef(AstType t, FileLine* fl, bool statement, AstNode* namep, AstNode* pinsp) + AstNodeFTaskRef(VNType t, FileLine* fl, bool statement, AstNode* namep, AstNode* pinsp) : AstNodeStmt{t, fl, statement} { setOp1p(namep); addNOp3p(pinsp); } - AstNodeFTaskRef(AstType t, FileLine* fl, bool statement, const string& name, AstNode* pinsp) + AstNodeFTaskRef(VNType t, FileLine* fl, bool statement, const string& name, AstNode* pinsp) : AstNodeStmt{t, fl, statement} , m_name{name} { addNOp3p(pinsp); @@ -2867,9 +3037,7 @@ protected: public: ASTNODE_BASE_FUNCS(NodeFTaskRef) virtual const char* broken() const override; - virtual void cloneRelink() override { - if (m_taskp && m_taskp->clonep()) m_taskp = m_taskp->clonep(); - } + virtual void cloneRelink() override; virtual void dump(std::ostream& str = std::cout) const override; virtual string name() const override { return m_name; } // * = Var name virtual bool isGateOptimizable() const override { @@ -2918,7 +3086,7 @@ private: VTimescale m_timeunit; // Global time unit VOptionBool m_unconnectedDrive; // State of `unconnected_drive protected: - AstNodeModule(AstType t, FileLine* fl, const string& name) + AstNodeModule(VNType t, FileLine* fl, const string& name) : AstNode{t, fl} , m_name{name} , m_origName{name} @@ -2978,7 +3146,7 @@ public: class AstNodeRange VL_NOT_FINAL : public AstNode { // A range, sized or unsized protected: - AstNodeRange(AstType t, FileLine* fl) + AstNodeRange(VNType t, FileLine* fl) : AstNode{t, fl} {} public: @@ -2987,26 +3155,27 @@ public: }; //###################################################################### -// Inline AstNVisitor METHODS +// Inline VNVisitor METHODS -inline void AstNVisitor::iterate(AstNode* nodep) { nodep->accept(*this); } -inline void AstNVisitor::iterateNull(AstNode* nodep) { +inline void VNVisitor::iterate(AstNode* nodep) { nodep->accept(*this); } +inline void VNVisitor::iterateNull(AstNode* nodep) { if (VL_LIKELY(nodep)) nodep->accept(*this); } -inline void AstNVisitor::iterateChildren(AstNode* nodep) { nodep->iterateChildren(*this); } -inline void AstNVisitor::iterateChildrenBackwards(AstNode* nodep) { +inline void VNVisitor::iterateChildren(AstNode* nodep) { nodep->iterateChildren(*this); } +inline void VNVisitor::iterateChildrenBackwards(AstNode* nodep) { nodep->iterateChildrenBackwards(*this); } -inline void AstNVisitor::iterateChildrenConst(AstNode* nodep) { - nodep->iterateChildrenConst(*this); -} -inline void AstNVisitor::iterateAndNextNull(AstNode* nodep) { +inline void VNVisitor::iterateChildrenConst(AstNode* nodep) { nodep->iterateChildrenConst(*this); } +inline void VNVisitor::iterateAndNextNull(AstNode* nodep) { if (VL_LIKELY(nodep)) nodep->iterateAndNext(*this); } -inline void AstNVisitor::iterateAndNextConstNull(AstNode* nodep) { +inline void VNVisitor::iterateAndNextConstNullBackwards(AstNode* nodep) { + if (VL_LIKELY(nodep)) nodep->iterateListBackwards(*this); +} +inline void VNVisitor::iterateAndNextConstNull(AstNode* nodep) { if (VL_LIKELY(nodep)) nodep->iterateAndNextConst(*this); } -inline AstNode* AstNVisitor::iterateSubtreeReturnEdits(AstNode* nodep) { +inline AstNode* VNVisitor::iterateSubtreeReturnEdits(AstNode* nodep) { return nodep->iterateSubtreeReturnEdits(*this); } diff --git a/src/V3AstConstOnly.h b/src/V3AstConstOnly.h index 58def6b0a..223143a68 100644 --- a/src/V3AstConstOnly.h +++ b/src/V3AstConstOnly.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3AstInlines.h b/src/V3AstInlines.h index 6058da776..6d8e93b35 100644 --- a/src/V3AstInlines.h +++ b/src/V3AstInlines.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -78,12 +78,6 @@ inline int AstNodeArrayDType::lo() const { return rangep()->loConst(); } inline int AstNodeArrayDType::elementsConst() const { return rangep()->elementsConst(); } inline VNumRange AstNodeArrayDType::declRange() const { return VNumRange{left(), right()}; } -inline const char* AstNodeFTaskRef::broken() const { - BROKEN_RTN(m_taskp && !m_taskp->brokeExists()); - BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); - return nullptr; -} - inline void AstIfaceRefDType::cloneRelink() { if (m_cellp && m_cellp->clonep()) m_cellp = m_cellp->clonep(); if (m_ifacep && m_ifacep->clonep()) m_ifacep = m_ifacep->clonep(); diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index a1f2ad2d0..4b90ed159 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -47,14 +47,32 @@ AstIface* AstIfaceRefDType::ifaceViaCellp() const { return ((m_cellp && m_cellp->modp()) ? VN_AS(m_cellp->modp(), Iface) : m_ifacep); } +const char* AstNodeFTaskRef::broken() const { + BROKEN_RTN(m_taskp && !m_taskp->brokeExists()); + BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); + return nullptr; +} + +void AstNodeFTaskRef::cloneRelink() { + if (m_taskp && m_taskp->clonep()) m_taskp = m_taskp->clonep(); + if (m_classOrPackagep && m_classOrPackagep->clonep()) { + m_classOrPackagep = m_classOrPackagep->clonep(); + } +} + const char* AstNodeVarRef::broken() const { - BROKEN_RTN(m_varScopep && !m_varScopep->brokeExists()); BROKEN_RTN(m_varp && !m_varp->brokeExists()); + BROKEN_RTN(m_varScopep && !m_varScopep->brokeExists()); + BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); return nullptr; } void AstNodeVarRef::cloneRelink() { if (m_varp && m_varp->clonep()) m_varp = m_varp->clonep(); + if (m_varScopep && m_varScopep->clonep()) m_varScopep = m_varScopep->clonep(); + if (m_classOrPackagep && m_classOrPackagep->clonep()) { + m_classOrPackagep = m_classOrPackagep->clonep(); + } } string AstNodeVarRef::selfPointerProtect(bool useSelfForThis) const { @@ -285,17 +303,17 @@ bool AstVar::isScBigUint() const { && !isScBv()); } -void AstVar::combineType(AstVarType type) { +void AstVar::combineType(VVarType type) { // These flags get combined with the existing settings of the flags. // We don't test varType for certain types, instead set flags since // when we combine wires cross-hierarchy we need a union of all characteristics. m_varType = type; // These flags get combined with the existing settings of the flags. - if (type == AstVarType::TRIWIRE || type == AstVarType::TRI0 || type == AstVarType::TRI1) { + if (type == VVarType::TRIWIRE || type == VVarType::TRI0 || type == VVarType::TRI1) { m_tristate = true; } - if (type == AstVarType::TRI0) m_isPulldown = true; - if (type == AstVarType::TRI1) m_isPullup = true; + if (type == VVarType::TRI0) m_isPulldown = true; + if (type == VVarType::TRI1) m_isPullup = true; } string AstVar::verilogKwd() const { @@ -303,11 +321,11 @@ string AstVar::verilogKwd() const { return direction().verilogKwd(); } else if (isTristate()) { return "tri"; - } else if (varType() == AstVarType::WIRE) { + } else if (varType() == VVarType::WIRE) { return "wire"; - } else if (varType() == AstVarType::WREAL) { + } else if (varType() == VVarType::WREAL) { return "wreal"; - } else if (varType() == AstVarType::IFACEREF) { + } else if (varType() == VVarType::IFACEREF) { return "ifaceref"; } else { return dtypep()->name(); @@ -337,10 +355,10 @@ string AstVar::vlArgType(bool named, bool forReturn, bool forFunc, const string& string AstVar::vlEnumType() const { string arg; const AstBasicDType* const bdtypep = basicp(); - const bool strtype = bdtypep && bdtypep->keyword() == AstBasicDTypeKwd::STRING; - if (bdtypep && bdtypep->keyword() == AstBasicDTypeKwd::CHARPTR) { + const bool strtype = bdtypep && bdtypep->keyword() == VBasicDTypeKwd::STRING; + if (bdtypep && bdtypep->keyword() == VBasicDTypeKwd::CHARPTR) { return "VLVT_PTR"; - } else if (bdtypep && bdtypep->keyword() == AstBasicDTypeKwd::SCOPEPTR) { + } else if (bdtypep && bdtypep->keyword() == VBasicDTypeKwd::SCOPEPTR) { return "VLVT_PTR"; } else if (strtype) { arg += "VLVT_STRING"; @@ -436,25 +454,33 @@ string AstVar::cPubArgType(bool named, bool forReturn) const { if (forReturn) named = false; string arg; if (isWide() && isReadOnly()) arg += "const "; - if (widthMin() == 1) { - arg += "bool"; - } else if (widthMin() <= VL_IDATASIZE) { - arg += "uint32_t"; - } else if (widthMin() <= VL_QUADSIZE) { - arg += "vluint64_t"; - } else { - arg += "uint32_t"; // []'s added later - } - if (isWide()) { - if (forReturn) { - v3warn(E_UNSUPPORTED, "Unsupported: Public functions with >64 bit outputs; " - "make an output of a public task instead"); + const bool isRef = !forReturn && (isWritable() || direction().isRefOrConstRef()); + if (VN_IS(dtypeSkipRefp(), BasicDType) && !dtypeSkipRefp()->isDouble() + && !dtypeSkipRefp()->isString()) { + // Backward compatible type declaration + if (widthMin() == 1) { + arg += "bool"; + } else if (widthMin() <= VL_IDATASIZE) { + arg += "uint32_t"; + } else if (widthMin() <= VL_QUADSIZE) { + arg += "vluint64_t"; + } else { + arg += "uint32_t"; // []'s added later + } + if (isWide()) { + if (forReturn) { + v3warn(E_UNSUPPORTED, "Unsupported: Public functions with >64 bit outputs; " + "make an output of a public task instead"); + } + arg += " (& " + name(); + arg += ")[" + cvtToStr(widthWords()) + "]"; + } else { + if (isRef) arg += "&"; + if (named) arg += " " + name(); } - arg += " (& " + name(); - arg += ")[" + cvtToStr(widthWords()) + "]"; } else { - if (!forReturn && (isWritable() || direction().isRefOrConstRef())) arg += "&"; - if (named) arg += " " + name(); + // Newer internal-compatible types + arg += dtypep()->cType((named ? name() : string{}), true, isRef); } return arg; } @@ -467,7 +493,7 @@ public: } virtual string primitive(const AstVar* varp) const { string type; - const AstBasicDTypeKwd keyword = varp->basicp()->keyword(); + const VBasicDTypeKwd keyword = varp->basicp()->keyword(); if (keyword.isDpiUnsignable() && !varp->basicp()->isSigned()) type = "unsigned "; type += keyword.dpiType(); return type; @@ -499,8 +525,7 @@ string AstVar::dpiArgType(bool named, bool forReturn) const { virtual string primitive(const AstVar* varp) const override { string type = dpiTypesToStringConverter::primitive(varp); if (varp->isWritable() || VN_IS(varp->dtypep()->skipRefp(), UnpackArrayDType)) { - if (!varp->isWritable() - && varp->basicp()->keyword() != AstBasicDTypeKwd::STRING) + if (!varp->isWritable() && varp->basicp()->keyword() != VBasicDTypeKwd::STRING) type = "const " + type; type += "*"; } @@ -541,7 +566,7 @@ string AstVar::dpiTmpVarType(const string& varName) const { virtual string primitive(const AstVar* varp) const override { string type = dpiTypesToStringConverter::primitive(varp); if (varp->isWritable() || VN_IS(varp->dtypep()->skipRefp(), UnpackArrayDType)) { - if (!varp->isWritable() && varp->basicp()->keyword() == AstBasicDTypeKwd::CHANDLE) + if (!varp->isWritable() && varp->basicp()->keyword() == VBasicDTypeKwd::CHANDLE) type = "const " + type; } type += ' ' + m_name + arraySuffix(varp, 0); @@ -670,9 +695,9 @@ AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound) const { const string bitvec = (!bdtypep->isOpaque() && !v3Global.opt.protectIds()) ? "/*" + cvtToStr(dtypep->width() - 1) + ":0*/" : ""; - if (bdtypep->keyword() == AstBasicDTypeKwd::CHARPTR) { + if (bdtypep->keyword() == VBasicDTypeKwd::CHARPTR) { info.m_type = "const char*"; - } else if (bdtypep->keyword() == AstBasicDTypeKwd::SCOPEPTR) { + } else if (bdtypep->keyword() == VBasicDTypeKwd::SCOPEPTR) { info.m_type = "const VerilatedScope*"; } else if (bdtypep->keyword().isDouble()) { info.m_type = "double"; @@ -781,7 +806,7 @@ AstNode* AstArraySel::baseFromp(AstNode* nodep, bool overMembers) { continue; } // AstNodeSelPre stashes the associated variable under an ATTROF - // of AstAttrType::VAR_BASE/MEMBER_BASE so it isn't constified + // of VAttrType::VAR_BASE/MEMBER_BASE so it isn't constified else if (VN_IS(nodep, AttrOf)) { nodep = VN_AS(nodep, AttrOf)->fromp(); continue; @@ -884,7 +909,7 @@ bool AstSenTree::hasCombo() const { AstTypeTable::AstTypeTable(FileLine* fl) : ASTGEN_SUPER_TypeTable(fl) { - for (int i = 0; i < AstBasicDTypeKwd::_ENUM_MAX; ++i) m_basicps[i] = nullptr; + for (int i = 0; i < VBasicDTypeKwd::_ENUM_MAX; ++i) m_basicps[i] = nullptr; } void AstTypeTable::clearCache() { @@ -935,7 +960,7 @@ AstQueueDType* AstTypeTable::findQueueIndexDType(FileLine* fl) { return m_queueIndexp; } -AstBasicDType* AstTypeTable::findBasicDType(FileLine* fl, AstBasicDTypeKwd kwd) { +AstBasicDType* AstTypeTable::findBasicDType(FileLine* fl, VBasicDTypeKwd kwd) { if (m_basicps[kwd]) return m_basicps[kwd]; // AstBasicDType* const new1p = new AstBasicDType(fl, kwd); @@ -953,7 +978,7 @@ AstBasicDType* AstTypeTable::findBasicDType(FileLine* fl, AstBasicDTypeKwd kwd) return newp; } -AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kwd, int width, +AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, int width, int widthMin, VSigning numeric) { AstBasicDType* const new1p = new AstBasicDType(fl, kwd, numeric, width, widthMin); AstBasicDType* const newp = findInsertSameDType(new1p); @@ -965,7 +990,7 @@ AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kw return newp; } -AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kwd, +AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, const VNumRange& range, int widthMin, VSigning numeric) { AstBasicDType* const new1p = new AstBasicDType(fl, kwd, numeric, range, widthMin); @@ -1000,7 +1025,7 @@ AstConstPool::AstConstPool(FileLine* fl) AstVarScope* AstConstPool::createNewEntry(const string& name, AstNode* initp) { FileLine* const fl = initp->fileline(); - AstVar* const varp = new AstVar(fl, AstVarType::MODULETEMP, name, initp->dtypep()); + AstVar* const varp = new AstVar(fl, VVarType::MODULETEMP, name, initp->dtypep()); varp->isConst(true); varp->isStatic(true); varp->valuep(initp->cloneTree(false)); @@ -1017,21 +1042,41 @@ static bool sameInit(const AstInitArray* ap, const AstInitArray* bp) { // - the default/inititem children might be in different order yet still yield the same table // See note in AstInitArray::same about the same. This function instead compares by initializer // value, rather than by tree structure. - const AstUnpackArrayDType* const aDTypep = VN_AS(ap->dtypep(), UnpackArrayDType); - const AstUnpackArrayDType* const bDTypep = VN_AS(bp->dtypep(), UnpackArrayDType); - if (!aDTypep->subDTypep()->sameTree(bDTypep->subDTypep())) { // Element types differ - return false; - } - if (!aDTypep->rangep()->sameTree(bDTypep->rangep())) { // Ranges differ - return false; - } - // Compare initializer arrays by value. Note this is only called when they hash the same, - // so they likely run at most once per call to 'AstConstPool::findTable'. - const uint32_t size = aDTypep->elementsConst(); - for (uint32_t n = 0; n < size; ++n) { - const AstNode* const valAp = ap->getIndexDefaultedValuep(n); - const AstNode* const valBp = bp->getIndexDefaultedValuep(n); - if (!valAp->sameTree(valBp)) { return false; } + if (const AstAssocArrayDType* const aDTypep = VN_CAST(ap->dtypep(), AssocArrayDType)) { + const AstAssocArrayDType* const bDTypep = VN_CAST(bp->dtypep(), AssocArrayDType); + if (!bDTypep) return false; + if (!aDTypep->subDTypep()->sameTree(bDTypep->subDTypep())) return false; + if (!aDTypep->keyDTypep()->sameTree(bDTypep->keyDTypep())) return false; + UASSERT_OBJ(ap->defaultp(), ap, "Assoc InitArray should have a default"); + UASSERT_OBJ(bp->defaultp(), bp, "Assoc InitArray should have a default"); + if (!ap->defaultp()->sameTree(bp->defaultp())) return false; + // Compare initializer arrays by value. Note this is only called when they hash the same, + // so they likely run at most once per call to 'AstConstPool::findTable'. + // This assumes that the defaults are used in the same way. + // TODO when buinding the AstInitArray, remove any values matching the default + const auto& amapr = ap->map(); + const auto& bmapr = bp->map(); + const auto ait = amapr.cbegin(); + const auto bit = bmapr.cbegin(); + while (ait != amapr.cend() || bit != bmapr.cend()) { + if (ait == amapr.cend() || bit == bmapr.cend()) return false; // Different size + if (ait->first != bit->first) return false; // Different key + if (ait->second->sameTree(bit->second)) return false; // Different value + } + } else if (const AstUnpackArrayDType* const aDTypep + = VN_CAST(ap->dtypep(), UnpackArrayDType)) { + const AstUnpackArrayDType* const bDTypep = VN_CAST(bp->dtypep(), UnpackArrayDType); + if (!bDTypep) return false; + if (!aDTypep->subDTypep()->sameTree(bDTypep->subDTypep())) return false; + if (!aDTypep->rangep()->sameTree(bDTypep->rangep())) return false; + // Compare initializer arrays by value. Note this is only called when they hash the same, + // so they likely run at most once per call to 'AstConstPool::findTable'. + const vluint64_t size = aDTypep->elementsConst(); + for (vluint64_t n = 0; n < size; ++n) { + const AstNode* const valAp = ap->getIndexDefaultedValuep(n); + const AstNode* const valBp = bp->getIndexDefaultedValuep(n); + if (!valAp->sameTree(valBp)) return false; + } } return true; } @@ -1039,8 +1084,9 @@ static bool sameInit(const AstInitArray* ap, const AstInitArray* bp) { AstVarScope* AstConstPool::findTable(AstInitArray* initp) { const AstNode* const defaultp = initp->defaultp(); // Verify initializer is well formed - UASSERT_OBJ(VN_IS(initp->dtypep(), UnpackArrayDType), initp, - "Const pool table must have AstUnpackArrayDType dtype"); + UASSERT_OBJ(VN_IS(initp->dtypep(), AssocArrayDType) + || VN_IS(initp->dtypep(), UnpackArrayDType), + initp, "Const pool table must have array dtype"); UASSERT_OBJ(!defaultp || VN_IS(defaultp, Const), initp, "Const pool table default must be Const"); for (AstNode* nodep = initp->initsp(); nodep; nodep = nodep->nextp()) { @@ -1257,6 +1303,9 @@ const char* AstClassPackage::broken() const { BROKEN_RTN(m_classp && !m_classp->brokeExists()); return nullptr; } +void AstClassPackage::cloneRelink() { + if (m_classp && m_classp->clonep()) m_classp = m_classp->clonep(); +} void AstClass::insertCache(AstNode* nodep) { const bool doit = (VN_IS(nodep, Var) || VN_IS(nodep, EnumItemRef) || (VN_IS(nodep, NodeFTask) && !VN_AS(nodep, NodeFTask)->isExternProto())); @@ -1280,7 +1329,7 @@ bool AstClass::isClassExtendedFrom(const AstClass* refClassp, const AstClass* ba return isClassExtendedFrom(refClassp->extendsp()->classp(), baseClassp); } void AstClass::dump(std::ostream& str) const { - this->AstNode::dump(str); + this->AstNodeModule::dump(str); if (isExtended()) str << " [EXT]"; if (isVirtual()) str << " [VIRT]"; } @@ -1294,6 +1343,7 @@ AstClass* AstClassExtends::classp() const { } void AstClassRefDType::dump(std::ostream& str) const { this->AstNode::dump(str); + if (classOrPackagep()) str << " cpkg=" << nodeAddr(classOrPackagep()); if (classp()) { str << " -> "; classp()->dump(str); @@ -1344,7 +1394,7 @@ void AstIfaceRefDType::dumpSmall(std::ostream& str) const { void AstInitArray::dump(std::ostream& str) const { this->AstNode::dump(str); int n = 0; - const AstInitArray::KeyItemMap& mapr = map(); + const auto& mapr = map(); for (const auto& itr : mapr) { if (n++ > 5) { str << " ..."; @@ -1371,6 +1421,10 @@ void AstJumpLabel::dump(std::ostream& str) const { str << "%Error:UNLINKED"; } } +void AstLogOr::dump(std::ostream& str) const { + this->AstNode::dump(str); + if (sideEffect()) str << " [SIDE]"; +} void AstMemberSel::dump(std::ostream& str) const { this->AstNodeMath::dump(str); str << " -> "; @@ -1580,10 +1634,10 @@ void AstMTaskBody::dump(std::ostream& str) const { } void AstTypeTable::dump(std::ostream& str) const { this->AstNode::dump(str); - for (int i = 0; i < static_cast(AstBasicDTypeKwd::_ENUM_MAX); ++i) { + for (int i = 0; i < static_cast(VBasicDTypeKwd::_ENUM_MAX); ++i) { if (AstBasicDType* const subnodep = m_basicps[i]) { str << '\n'; // Newline from caller, so newline first - str << "\t\t" << std::setw(8) << AstBasicDTypeKwd(i).ascii(); + str << "\t\t" << std::setw(8) << VBasicDTypeKwd(i).ascii(); str << " -> "; subnodep->dump(str); } @@ -1635,6 +1689,8 @@ void AstVoidDType::dumpSmall(std::ostream& str) const { void AstVarScope::dump(std::ostream& str) const { this->AstNode::dump(str); if (isCircular()) str << " [CIRC]"; + if (isTrace()) str << " [T]"; + if (scopep()) str << " [scopep=" << reinterpret_cast(scopep()) << "]"; if (varp()) { str << " -> "; varp()->dump(str); @@ -1754,12 +1810,13 @@ void AstNodeFTaskRef::dump(std::ostream& str) const { void AstNodeFTask::dump(std::ostream& str) const { this->AstNode::dump(str); if (classMethod()) str << " [METHOD]"; - if (taskPublic()) str << " [PUBLIC]"; - if (prototype()) str << " [PROTOTYPE]"; - if (dpiImport()) str << " [DPII]"; if (dpiExport()) str << " [DPIX]"; + if (dpiImport()) str << " [DPII]"; if (dpiOpenChild()) str << " [DPIOPENCHILD]"; if (dpiOpenParent()) str << " [DPIOPENPARENT]"; + if (prototype()) str << " [PROTOTYPE]"; + if (recursive()) str << " [RECURSIVE]"; + if (taskPublic()) str << " [PUBLIC]"; if ((dpiImport() || dpiExport()) && cname() != name()) str << " [c=" << cname() << "]"; } void AstNodeBlock::dump(std::ostream& str) const { diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index fb598bfaf..984fcb112 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -26,7 +26,7 @@ // Standard defines for all AstNode final classes #define ASTNODE_NODE_FUNCS_NO_DTOR(name) \ - virtual void accept(AstNVisitor& v) override { v.visit(this); } \ + virtual void accept(VNVisitor& v) override { v.visit(this); } \ virtual AstNode* clone() override { return new Ast##name(*this); } \ static Ast##name* cloneTreeNull(Ast##name* nodep, bool cloneNextLink) { \ return nodep ? nodep->cloneTree(cloneNextLink) : nullptr; \ @@ -183,6 +183,15 @@ public: static AstConst* parseParamLiteral(FileLine* fl, const string& literal); }; +class AstEmpty final : public AstNode { + // Represents something missing, e.g. a missing argument in FOREACH +public: + AstEmpty(FileLine* fl) + : ASTGEN_SUPER_Empty(fl) {} + ASTNODE_NODE_FUNCS(Empty) + virtual bool same(const AstNode* samep) const override { return true; } +}; + class AstEmptyQueue final : public AstNodeMath { public: AstEmptyQueue(FileLine* fl) @@ -296,8 +305,9 @@ public: AstClassPackage(FileLine* fl, const string& name) : ASTGEN_SUPER_ClassPackage(fl, name) {} ASTNODE_NODE_FUNCS(ClassPackage) - virtual string verilogKwd() const override { return "/*class*/package"; } + virtual string verilogKwd() const override { return "classpackage"; } virtual const char* broken() const override; + virtual void cloneRelink() override; virtual bool timescaleMatters() const override { return false; } AstClass* classp() const { return m_classp; } void classp(AstClass* classp) { m_classp = classp; } @@ -325,6 +335,12 @@ public: BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); return nullptr; } + virtual void cloneRelink() override { + AstNodeModule::cloneRelink(); + if (m_classOrPackagep && m_classOrPackagep->clonep()) { + m_classOrPackagep = m_classOrPackagep->clonep(); + } + } virtual bool timescaleMatters() const override { return false; } // op1/op2/op3 in AstNodeModule AstClassPackage* classOrPackagep() const { return m_classOrPackagep; } @@ -375,10 +391,10 @@ class AstParamTypeDType final : public AstNodeDType { // Parents: MODULE // A parameter type statement; much like a var or typedef private: - const AstVarType m_varType; // Type of variable (for localparam vs. param) + const VVarType m_varType; // Type of variable (for localparam vs. param) string m_name; // Name of variable public: - AstParamTypeDType(FileLine* fl, AstVarType type, const string& name, VFlagChildDType, + AstParamTypeDType(FileLine* fl, VVarType type, const string& name, VFlagChildDType, AstNodeDType* dtp) : ASTGEN_SUPER_ParamTypeDType(fl) , m_varType{type} @@ -412,9 +428,9 @@ public: virtual bool maybePointedTo() const override { return true; } virtual bool hasDType() const override { return true; } virtual void name(const string& flag) override { m_name = flag; } - AstVarType varType() const { return m_varType; } // * = Type of variable + VVarType varType() const { return m_varType; } // * = Type of variable bool isParam() const { return true; } - bool isGParam() const { return (varType() == AstVarType::GPARAM); } + bool isGParam() const { return (varType() == VVarType::GPARAM); } virtual bool isCompound() const override { v3fatalSrc("call isCompound on subdata type, not reference"); return false; @@ -538,6 +554,12 @@ public: keyDTypep(nullptr); dtypep(nullptr); // V3Width will resolve } + AstAssocArrayDType(FileLine* fl, AstNodeDType* dtp, AstNodeDType* keyDtp) + : ASTGEN_SUPER_AssocArrayDType(fl) { + refDTypep(dtp); + keyDTypep(keyDtp); + dtypep(dtp); + } ASTNODE_NODE_FUNCS(AssocArrayDType) virtual const char* broken() const override { BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) @@ -802,7 +824,7 @@ class AstBasicDType final : public AstNodeDType { // Children: RANGE (converted to constant in V3Width) private: struct Members { - AstBasicDTypeKwd m_keyword; // (also in VBasicTypeKey) What keyword created basic type + VBasicDTypeKwd m_keyword; // (also in VBasicTypeKey) What keyword created basic type VNumRange m_nrange; // (also in VBasicTypeKey) Numeric msb/lsb (if non-opaque keyword) bool operator==(const Members& rhs) const { return rhs.m_keyword == m_keyword && rhs.m_nrange == m_nrange; @@ -810,31 +832,30 @@ private: } m; // See also in AstNodeDType: m_width, m_widthMin, m_numeric(issigned) public: - AstBasicDType(FileLine* fl, AstBasicDTypeKwd kwd, const VSigning& signst = VSigning::NOSIGN) + AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, const VSigning& signst = VSigning::NOSIGN) : ASTGEN_SUPER_BasicDType(fl) { init(kwd, signst, 0, -1, nullptr); } AstBasicDType(FileLine* fl, VFlagLogicPacked, int wantwidth) : ASTGEN_SUPER_BasicDType(fl) { - init(AstBasicDTypeKwd::LOGIC, VSigning::NOSIGN, wantwidth, -1, nullptr); + init(VBasicDTypeKwd::LOGIC, VSigning::NOSIGN, wantwidth, -1, nullptr); } AstBasicDType(FileLine* fl, VFlagBitPacked, int wantwidth) : ASTGEN_SUPER_BasicDType(fl) { - init(AstBasicDTypeKwd::BIT, VSigning::NOSIGN, wantwidth, -1, nullptr); + init(VBasicDTypeKwd::BIT, VSigning::NOSIGN, wantwidth, -1, nullptr); } - AstBasicDType(FileLine* fl, AstBasicDTypeKwd kwd, VSigning numer, int wantwidth, int widthmin) + AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, VSigning numer, int wantwidth, int widthmin) : ASTGEN_SUPER_BasicDType(fl) { init(kwd, numer, wantwidth, widthmin, nullptr); } - AstBasicDType(FileLine* fl, AstBasicDTypeKwd kwd, VSigning numer, VNumRange range, - int widthmin) + AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, VSigning numer, VNumRange range, int widthmin) : ASTGEN_SUPER_BasicDType(fl) { init(kwd, numer, range.elements(), widthmin, nullptr); m.m_nrange = range; // as init() presumes lsb==0, but range.lsb() might not be } // See also addRange in verilog.y private: - void init(AstBasicDTypeKwd kwd, VSigning numer, int wantwidth, int wantwidthmin, + void init(VBasicDTypeKwd kwd, VSigning numer, int wantwidth, int wantwidthmin, AstRange* rangep) { // wantwidth=0 means figure it out, but if a widthmin is >=0 // we allow width 0 so that {{0{x}},y} works properly @@ -842,8 +863,8 @@ private: m.m_keyword = kwd; // Implicitness: // "parameter X" is implicit and sized from initial // value, "parameter reg x" not - if (keyword() == AstBasicDTypeKwd::LOGIC_IMPLICIT) { - if (rangep || wantwidth) m.m_keyword = AstBasicDTypeKwd::LOGIC; + if (keyword() == VBasicDTypeKwd::LOGIC_IMPLICIT) { + if (rangep || wantwidth) m.m_keyword = VBasicDTypeKwd::LOGIC; } if (numer == VSigning::NOSIGN) { if (keyword().isSigned()) { @@ -908,7 +929,7 @@ public: // (Slow) recurses - Width in bytes rounding up 1,2,4,8,12,... virtual int widthTotalBytes() const override; virtual bool isFourstate() const override { return keyword().isFourstate(); } - AstBasicDTypeKwd keyword() const { // Avoid using - use isSomething accessors instead + VBasicDTypeKwd keyword() const { // Avoid using - use isSomething accessors instead return m.m_keyword; } bool isBitLogic() const { return keyword().isBitLogic(); } @@ -919,10 +940,10 @@ public: bool isZeroInit() const { return keyword().isZeroInit(); } bool isRanged() const { return rangep() || m.m_nrange.ranged(); } bool isDpiBitVec() const { // DPI uses svBitVecVal - return keyword() == AstBasicDTypeKwd::BIT && isRanged(); + return keyword() == VBasicDTypeKwd::BIT && isRanged(); } bool isDpiLogicVec() const { // DPI uses svLogicVecVal - return keyword().isFourstate() && !(keyword() == AstBasicDTypeKwd::LOGIC && !isRanged()); + return keyword().isFourstate() && !(keyword() == VBasicDTypeKwd::LOGIC && !isRanged()); } bool isDpiPrimitive() const { // DPI uses a primitive type return !isDpiBitVec() && !isDpiLogicVec(); @@ -937,7 +958,7 @@ public: bool littleEndian() const { return (rangep() ? rangep()->littleEndian() : m.m_nrange.littleEndian()); } - bool implicit() const { return keyword() == AstBasicDTypeKwd::LOGIC_IMPLICIT; } + bool implicit() const { return keyword() == VBasicDTypeKwd::LOGIC_IMPLICIT; } VNumRange declRange() const { return isRanged() ? VNumRange{left(), right()} : VNumRange{}; } void cvtRangeConst() { // Convert to smaller representation if (rangep() && VN_IS(rangep()->leftp(), Const) && VN_IS(rangep()->rightp(), Const)) { @@ -1019,10 +1040,14 @@ public: // METHODS virtual const char* broken() const override { BROKEN_RTN(m_classp && !m_classp->brokeExists()); + BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); return nullptr; } virtual void cloneRelink() override { if (m_classp && m_classp->clonep()) m_classp = m_classp->clonep(); + if (m_classOrPackagep && m_classOrPackagep->clonep()) { + m_classOrPackagep = m_classOrPackagep->clonep(); + } } virtual bool same(const AstNode* samep) const override { const AstClassRefDType* const asamep = static_cast(samep); @@ -1203,11 +1228,15 @@ public: virtual const char* broken() const override { BROKEN_RTN(m_typedefp && !m_typedefp->brokeExists()); BROKEN_RTN(m_refDTypep && !m_refDTypep->brokeExists()); + BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); return nullptr; } virtual void cloneRelink() override { if (m_typedefp && m_typedefp->clonep()) m_typedefp = m_typedefp->clonep(); if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); + if (m_classOrPackagep && m_classOrPackagep->clonep()) { + m_classOrPackagep = m_classOrPackagep->clonep(); + } } virtual bool same(const AstNode* samep) const override { const AstRefDType* const asamep = static_cast(samep); @@ -1324,6 +1353,13 @@ public: virtual string name() const override { return m_name; } // * = Var name virtual bool hasDType() const override { return true; } virtual bool maybePointedTo() const override { return true; } + virtual const char* broken() const override { + BROKEN_RTN(m_refDTypep && !m_refDTypep->brokeExists()); + return nullptr; + } + virtual void cloneRelink() override { + if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); + } virtual AstNodeDType* getChildDTypep() const override { return childDTypep(); } // op1 = Range of variable AstNodeDType* childDTypep() const { return VN_AS(op1p(), NodeDType); } @@ -1373,6 +1409,7 @@ public: virtual void dumpSmall(std::ostream& str) const override; virtual bool hasDType() const override { return true; } virtual bool maybePointedTo() const override { return true; } + virtual bool undead() const override { return true; } virtual AstNodeDType* subDTypep() const override { return nullptr; } virtual AstNodeDType* virtRefDTypep() const override { return nullptr; } virtual void virtRefDTypep(AstNodeDType* nodep) override {} @@ -1400,6 +1437,7 @@ public: virtual void dumpSmall(std::ostream& str) const override; virtual bool hasDType() const override { return true; } virtual bool maybePointedTo() const override { return true; } + virtual bool undead() const override { return true; } virtual AstNodeDType* subDTypep() const override { return nullptr; } virtual AstNodeDType* virtRefDTypep() const override { return nullptr; } virtual void virtRefDTypep(AstNodeDType* nodep) override {} @@ -1454,6 +1492,11 @@ public: virtual void dump(std::ostream& str) const override; virtual string name() const override { return itemp()->name(); } virtual int instrCount() const override { return 0; } + virtual const char* broken() const override { + BROKEN_RTN(m_itemp && !m_itemp->brokeExists()); + BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); + return nullptr; + } virtual void cloneRelink() override { if (m_itemp->clonep()) m_itemp = m_itemp->clonep(); } @@ -1682,6 +1725,7 @@ public: virtual bool same(const AstNode* samep) const override { return true; } virtual bool maybePointedTo() const override { return false; } AstNode* fromp() const { return op1p(); } + void fromp(AstNode* nodep) { setOp1p(nodep); } AstNode* elementsp() const { return op2p(); } }; @@ -1911,10 +1955,10 @@ private: string m_name; // Name of variable string m_origName; // Original name before dot addition string m_tag; // Holds the string of the verilator tag -- used in XML output. - AstVarType m_varType; // Type of variable + VVarType m_varType; // Type of variable VDirection m_direction; // Direction input/output etc VDirection m_declDirection; // Declared direction input/output etc - AstBasicDTypeKwd m_declKwd; // Keyword at declaration time + VBasicDTypeKwd m_declKwd; // Keyword at declaration time VLifetime m_lifetime; // Lifetime VVarAttrClocker m_attrClocker; MTaskIdSet m_mtaskIds; // MTaskID's that read or write this var @@ -1943,6 +1987,7 @@ private: bool m_fileDescr : 1; // File descriptor bool m_isRand : 1; // Random variable bool m_isConst : 1; // Table contains constant data + bool m_isContinuously : 1; // Ever assigned continuously (for force/release) bool m_isStatic : 1; // Static C variable (for Verilog see instead isAutomatic) bool m_isPulldown : 1; // Tri0 bool m_isPullup : 1; // Tri1 @@ -1955,6 +2000,7 @@ private: bool m_overridenParam : 1; // Overridden parameter by #(...) or defparam bool m_trace : 1; // Trace this variable bool m_isLatched : 1; // Not assigned in all control paths of combo always + bool m_isForceable : 1; // May be forced/released externally from user C code void init() { m_ansi = false; @@ -1981,6 +2027,7 @@ private: m_fileDescr = false; m_isRand = false; m_isConst = false; + m_isContinuously = false; m_isStatic = false; m_isPulldown = false; m_isPullup = false; @@ -1993,11 +2040,12 @@ private: m_overridenParam = false; m_trace = false; m_isLatched = false; + m_isForceable = false; m_attrClocker = VVarAttrClocker::CLOCKER_UNKNOWN; } public: - AstVar(FileLine* fl, AstVarType type, const string& name, VFlagChildDType, AstNodeDType* dtp) + AstVar(FileLine* fl, VVarType type, const string& name, VFlagChildDType, AstNodeDType* dtp) : ASTGEN_SUPER_Var(fl) , m_name{name} , m_origName{name} { @@ -2008,10 +2056,10 @@ public: if (dtp->basicp()) { m_declKwd = dtp->basicp()->keyword(); } else { - m_declKwd = AstBasicDTypeKwd::LOGIC; + m_declKwd = VBasicDTypeKwd::LOGIC; } } - AstVar(FileLine* fl, AstVarType type, const string& name, AstNodeDType* dtp) + AstVar(FileLine* fl, VVarType type, const string& name, AstNodeDType* dtp) : ASTGEN_SUPER_Var(fl) , m_name{name} , m_origName{name} { @@ -2022,28 +2070,28 @@ public: if (dtp->basicp()) { m_declKwd = dtp->basicp()->keyword(); } else { - m_declKwd = AstBasicDTypeKwd::LOGIC; + m_declKwd = VBasicDTypeKwd::LOGIC; } } - AstVar(FileLine* fl, AstVarType type, const string& name, VFlagLogicPacked, int wantwidth) + AstVar(FileLine* fl, VVarType type, const string& name, VFlagLogicPacked, int wantwidth) : ASTGEN_SUPER_Var(fl) , m_name{name} , m_origName{name} { init(); combineType(type); dtypeSetLogicSized(wantwidth, VSigning::UNSIGNED); - m_declKwd = AstBasicDTypeKwd::LOGIC; + m_declKwd = VBasicDTypeKwd::LOGIC; } - AstVar(FileLine* fl, AstVarType type, const string& name, VFlagBitPacked, int wantwidth) + AstVar(FileLine* fl, VVarType type, const string& name, VFlagBitPacked, int wantwidth) : ASTGEN_SUPER_Var(fl) , m_name{name} , m_origName{name} { init(); combineType(type); dtypeSetBitSized(wantwidth, VSigning::UNSIGNED); - m_declKwd = AstBasicDTypeKwd::BIT; + m_declKwd = VBasicDTypeKwd::BIT; } - AstVar(FileLine* fl, AstVarType type, const string& name, AstVar* examplep) + AstVar(FileLine* fl, VVarType type, const string& name, AstVar* examplep) : ASTGEN_SUPER_Var(fl) , m_name{name} , m_origName{name} { @@ -2060,7 +2108,7 @@ public: virtual bool maybePointedTo() const override { return true; } virtual string origName() const override { return m_origName; } // * = Original name void origName(const string& name) { m_origName = name; } - AstVarType varType() const { return m_varType; } // * = Type of variable + VVarType varType() const { return m_varType; } // * = Type of variable void direction(const VDirection& flag) { m_direction = flag; if (m_direction == VDirection::INOUT) m_tristate = true; @@ -2069,7 +2117,7 @@ public: bool isIO() const { return m_direction != VDirection::NONE; } void declDirection(const VDirection& flag) { m_declDirection = flag; } VDirection declDirection() const { return m_declDirection; } - void varType(AstVarType type) { m_varType = type; } + void varType(VVarType type) { m_varType = type; } void varType2Out() { m_tristate = false; m_direction = VDirection::OUTPUT; @@ -2078,7 +2126,7 @@ public: m_tristate = false; m_direction = VDirection::INPUT; } - AstBasicDTypeKwd declKwd() const { return m_declKwd; } + VBasicDTypeKwd declKwd() const { return m_declKwd; } string scType() const; // Return SysC type: bool, uint32_t, uint64_t, sc_bv // Return C /*public*/ type for argument: bool, uint32_t, uint64_t, etc. string cPubArgType(bool named, bool forReturn) const; @@ -2090,7 +2138,7 @@ public: string vlEnumType() const; // Return VerilatorVarType: VLVT_UINT32, etc string vlEnumDir() const; // Return VerilatorVarDir: VLVD_INOUT, etc string vlPropDecl(const string& propName) const; // Return VerilatorVarProps declaration - void combineType(AstVarType type); + void combineType(VVarType type); virtual AstNodeDType* getChildDTypep() const override { return childDTypep(); } // op1 = Range of variable AstNodeDType* childDTypep() const { return VN_AS(op1p(), NodeDType); } @@ -2135,6 +2183,7 @@ public: void primaryIO(bool flag) { m_primaryIO = flag; } void isRand(bool flag) { m_isRand = flag; } void isConst(bool flag) { m_isConst = flag; } + void isContinuously(bool flag) { m_isContinuously = flag; } void isStatic(bool flag) { m_isStatic = flag; } void isIfaceParent(bool flag) { m_isIfaceParent = flag; } void funcLocal(bool flag) { m_funcLocal = flag; } @@ -2153,11 +2202,14 @@ public: bool overriddenParam() const { return m_overridenParam; } void trace(bool flag) { m_trace = flag; } void isLatched(bool flag) { m_isLatched = flag; } + bool isForceable() const { return m_isForceable; } + void setForceable() { m_isForceable = true; } // METHODS virtual void name(const string& name) override { m_name = name; } virtual void tag(const string& text) override { m_tag = text; } virtual string tag() const override { return m_tag; } bool isAnsi() const { return m_ansi; } + bool isContinuously() const { return m_isContinuously; } bool isDeclTyped() const { return m_declTyped; } bool isInoutish() const { return m_direction.isInoutish(); } bool isNonOutput() const { return m_direction.isNonOutput(); } @@ -2166,7 +2218,7 @@ public: bool isTristate() const { return m_tristate; } bool isPrimaryIO() const { return m_primaryIO; } bool isPrimaryInish() const { return isPrimaryIO() && isNonOutput(); } - bool isIfaceRef() const { return (varType() == AstVarType::IFACEREF); } + bool isIfaceRef() const { return (varType() == VVarType::IFACEREF); } bool isIfaceParent() const { return m_isIfaceParent; } bool isSignal() const { return varType().isSignal(); } bool isTemp() const { return varType().isTemp(); } @@ -2176,14 +2228,14 @@ public: // Wrapper would otherwise duplicate wrapped module's coverage && !isSc() && !isPrimaryIO() && !isConst() && !isDouble() && !isString()); } - bool isClassMember() const { return varType() == AstVarType::MEMBER; } - bool isStatementTemp() const { return (varType() == AstVarType::STMTTEMP); } - bool isXTemp() const { return (varType() == AstVarType::XTEMP); } + bool isClassMember() const { return varType() == VVarType::MEMBER; } + bool isStatementTemp() const { return (varType() == VVarType::STMTTEMP); } + bool isXTemp() const { return (varType() == VVarType::XTEMP); } bool isParam() const { - return (varType() == AstVarType::LPARAM || varType() == AstVarType::GPARAM); + return (varType() == VVarType::LPARAM || varType() == VVarType::GPARAM); } - bool isGParam() const { return (varType() == AstVarType::GPARAM); } - bool isGenVar() const { return (varType() == AstVarType::GENVAR); } + bool isGParam() const { return (varType() == VVarType::GPARAM); } + bool isGenVar() const { return (varType() == VVarType::GENVAR); } bool isBitLogic() const { AstBasicDType* bdtypep = basicp(); return bdtypep && bdtypep->isBitLogic(); @@ -2227,6 +2279,7 @@ public: if (fromp->attrClockEn()) attrClockEn(true); if (fromp->attrFileDescr()) attrFileDescr(true); if (fromp->attrIsolateAssign()) attrIsolateAssign(true); + if (fromp->isContinuously()) isContinuously(true); } bool gateMultiInputOptimizable() const { // Ok to gate optimize; must return false if propagateAttrFrom would do anything @@ -2244,8 +2297,8 @@ public: if (typevarp->attrScClocked()) attrScClocked(true); } void inlineAttrReset(const string& name) { - if (direction() == VDirection::INOUT && varType() == AstVarType::WIRE) { - m_varType = AstVarType::TRIWIRE; + if (direction() == VDirection::INOUT && varType() == VVarType::WIRE) { + m_varType = VVarType::TRIWIRE; } m_direction = VDirection::NONE; m_name = name; @@ -2390,6 +2443,7 @@ public: virtual bool hasDType() const override { return true; } AstVar* varp() const { return m_varp; } // [After Link] Pointer to variable AstScope* scopep() const { return m_scopep; } // Pointer to scope it's under + void scopep(AstScope* nodep) { m_scopep = nodep; } // op1 = Calculation of value of variable, nullptr=complicated AstNode* valuep() const { return op1p(); } void valuep(AstNode* valuep) { addOp1p(valuep); } @@ -2680,6 +2734,7 @@ public: ASTNODE_NODE_FUNCS(Iface) // Interfaces have `timescale applicability but lots of code seems to // get false warnings if we enable this + virtual string verilogKwd() const override { return "interface"; } virtual bool timescaleMatters() const override { return false; } }; @@ -3068,8 +3123,14 @@ public: virtual string name() const override { return m_name; } // * = Var name AstNode* classOrPackageNodep() const { return m_classOrPackageNodep; } void classOrPackageNodep(AstNode* nodep) { m_classOrPackageNodep = nodep; } - AstNodeModule* classOrPackagep() const { return VN_AS(m_classOrPackageNodep, NodeModule); } - AstPackage* packagep() const { return VN_AS(classOrPackageNodep(), Package); } + AstNodeModule* classOrPackagep() const { + AstNode* foundp = m_classOrPackageNodep; + while (auto* const anodep = VN_CAST(foundp, Typedef)) foundp = anodep->subDTypep(); + while (auto* const anodep = VN_CAST(foundp, ClassRefDType)) + foundp = anodep->classOrPackagep(); + return VN_CAST(foundp, NodeModule); + } + AstPackage* packagep() const { return VN_CAST(classOrPackageNodep(), Package); } void classOrPackagep(AstNodeModule* nodep) { m_classOrPackageNodep = nodep; } AstPin* paramsp() const { return VN_AS(op4p(), Pin); } }; @@ -3093,6 +3154,7 @@ public: } virtual void dump(std::ostream& str) const override; AstNode* lhsp() const { return op1p(); } + void rhsp(AstNode* nodep) { setOp2p(nodep); } AstNode* rhsp() const { return op2p(); } bool colon() const { return m_colon; } }; @@ -3344,6 +3406,15 @@ public: ASTNODE_NODE_FUNCS(Initial) }; +class AstInitialAutomatic final : public AstNodeProcedure { + // initial for automatic variables + // That is, it runs every function start, or class construction +public: + AstInitialAutomatic(FileLine* fl, AstNode* bodysp) + : ASTGEN_SUPER_InitialAutomatic(fl, bodysp) {} + ASTNODE_NODE_FUNCS(InitialAutomatic) +}; + class AstAlways final : public AstNodeProcedure { const VAlwaysKwd m_keyword; @@ -3491,6 +3562,29 @@ public: uint32_t direction() const { return (uint32_t)m_direction; } }; +class AstAssignForce final : public AstNodeAssign { + // Procedural 'force' statement +public: + AstAssignForce(FileLine* fl, AstNode* lhsp, AstNode* rhsp) + : ASTGEN_SUPER_AssignForce(fl, lhsp, rhsp) {} + ASTNODE_NODE_FUNCS(AssignForce) + virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override { + return new AstAssignForce{this->fileline(), lhsp, rhsp}; + } + virtual bool brokeLhsMustBeLvalue() const override { return true; } +}; + +class AstRelease final : public AstNodeStmt { + // Procedural 'release' statement +public: + AstRelease(FileLine* fl, AstNode* lhsp) + : ASTGEN_SUPER_Release(fl) { + setOp1p(lhsp); + } + ASTNODE_NODE_FUNCS(Release); + AstNode* lhsp() const { return op1p(); } +}; + class AstAssignPre final : public AstNodeAssign { // Like Assign, but predelayed assignment requiring special order handling public: @@ -3858,17 +3952,17 @@ class AstDisplay final : public AstNodeStmt { // Children: file which must be a varref // Children: SFORMATF to generate print string private: - AstDisplayType m_displayType; + VDisplayType m_displayType; public: - AstDisplay(FileLine* fl, AstDisplayType dispType, const string& text, AstNode* filep, + AstDisplay(FileLine* fl, VDisplayType dispType, const string& text, AstNode* filep, AstNode* exprsp, char missingArgChar = 'd') : ASTGEN_SUPER_Display(fl) { setOp1p(new AstSFormatF(fl, text, true, exprsp, missingArgChar)); setNOp3p(filep); m_displayType = dispType; } - AstDisplay(FileLine* fl, AstDisplayType dispType, AstNode* filep, AstNode* exprsp, + AstDisplay(FileLine* fl, VDisplayType dispType, AstNode* filep, AstNode* exprsp, char missingArgChar = 'd') : ASTGEN_SUPER_Display(fl) { setOp1p(new AstSFormatF(fl, AstSFormatF::NoFormat(), exprsp, missingArgChar)); @@ -3896,8 +3990,8 @@ public: return displayType() == static_cast(samep)->displayType(); } virtual int instrCount() const override { return INSTR_COUNT_PLI; } - AstDisplayType displayType() const { return m_displayType; } - void displayType(AstDisplayType type) { m_displayType = type; } + VDisplayType displayType() const { return m_displayType; } + void displayType(VDisplayType type) { m_displayType = type; } // * = Add a newline for $display bool addNewline() const { return displayType().addNewline(); } void fmtp(AstSFormatF* nodep) { addOp1p(nodep); } // op1 = To-String formatter @@ -3933,10 +4027,10 @@ class AstElabDisplay final : public AstNode { // Parents: stmtlist // Children: SFORMATF to generate print string private: - AstDisplayType m_displayType; + VDisplayType m_displayType; public: - AstElabDisplay(FileLine* fl, AstDisplayType dispType, AstNode* exprsp) + AstElabDisplay(FileLine* fl, VDisplayType dispType, AstNode* exprsp) : ASTGEN_SUPER_ElabDisplay(fl) { setOp1p(new AstSFormatF(fl, AstSFormatF::NoFormat(), exprsp)); m_displayType = dispType; @@ -3960,8 +4054,8 @@ public: return displayType() == static_cast(samep)->displayType(); } virtual int instrCount() const override { return INSTR_COUNT_PLI; } - AstDisplayType displayType() const { return m_displayType; } - void displayType(AstDisplayType type) { m_displayType = type; } + VDisplayType displayType() const { return m_displayType; } + void displayType(VDisplayType type) { m_displayType = type; } void fmtp(AstSFormatF* nodep) { addOp1p(nodep); } // op1 = To-String formatter AstSFormatF* fmtp() const { return VN_AS(op1p(), SFormatF); } }; @@ -4309,7 +4403,7 @@ class AstNodeReadWriteMem VL_NOT_FINAL : public AstNodeStmt { private: const bool m_isHex; // readmemh, not readmemb public: - AstNodeReadWriteMem(AstType t, FileLine* fl, bool hex, AstNode* filenamep, AstNode* memp, + AstNodeReadWriteMem(VNType t, FileLine* fl, bool hex, AstNode* filenamep, AstNode* memp, AstNode* lsbp, AstNode* msbp) : AstNodeStmt(t, fl) , m_isHex(hex) { @@ -4724,34 +4818,6 @@ public: AstJumpLabel* labelp() const { return m_labelp; } }; -class AstChangeXor final : public AstNodeBiComAsv { - // A comparison to determine change detection, common & must be fast. - // Returns 32-bit or 64-bit value where 0 indicates no change. - // Parents: OR or LOGOR - // Children: VARREF -public: - AstChangeXor(FileLine* fl, AstNode* lhsp, AstNode* rhsp) - : ASTGEN_SUPER_ChangeXor(fl, lhsp, rhsp) { - dtypeSetUInt32(); // Always used on, and returns word entities - } - ASTNODE_NODE_FUNCS(ChangeXor) - virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override { - return new AstChangeXor(this->fileline(), lhsp, rhsp); - } - virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { - out.opChangeXor(lhs, rhs); - } - virtual string emitVerilog() override { return "%k(%l %f^ %r)"; } - virtual string emitC() override { return "VL_CHANGEXOR_%li(%lw, %P, %li, %ri)"; } - virtual string emitSimpleOperator() override { return "^"; } - virtual bool cleanOut() const override { return false; } // Lclean && Rclean - virtual bool cleanLhs() const override { return true; } - virtual bool cleanRhs() const override { return true; } - virtual bool sizeMattersLhs() const override { return false; } - virtual bool sizeMattersRhs() const override { return false; } - virtual int instrCount() const override { return widthInstrs(); } -}; - class AstChangeDet final : public AstNodeStmt { // A comparison to determine change detection, common & must be fast. public: @@ -4953,12 +5019,12 @@ class AstInitArray final : public AstNode { // Parents: ASTVAR::init() // Children: AstInitItem public: - using KeyItemMap = std::map; + using KeyItemMap = std::map; private: KeyItemMap m_map; // Node value for each array index public: - AstInitArray(FileLine* fl, AstNodeArrayDType* newDTypep, AstNode* defaultp) + AstInitArray(FileLine* fl, AstNodeDType* newDTypep, AstNode* defaultp) : ASTGEN_SUPER_InitArray(fl) { dtypep(newDTypep); addNOp1p(defaultp); @@ -4988,7 +5054,7 @@ public: AstNode* initsp() const { return op2p(); } // op2 = Initial value expressions void addValuep(AstNode* newp) { addIndexValuep(m_map.size(), newp); } const KeyItemMap& map() const { return m_map; } - AstNode* addIndexValuep(uint32_t index, AstNode* newp) { + AstNode* addIndexValuep(vluint64_t index, AstNode* newp) { // Returns old value, caller must garbage collect AstNode* oldp = nullptr; const auto it = m_map.find(index); @@ -5002,7 +5068,7 @@ public: } return oldp; } - AstNode* getIndexValuep(uint32_t index) const { + AstNode* getIndexValuep(vluint64_t index) const { const auto it = m_map.find(index); if (it == m_map.end()) { return nullptr; @@ -5010,7 +5076,7 @@ public: return it->second->valuep(); } } - AstNode* getIndexDefaultedValuep(uint32_t index) const { + AstNode* getIndexDefaultedValuep(vluint64_t index) const { AstNode* valuep = getIndexValuep(index); if (!valuep) valuep = defaultp(); return valuep; @@ -5074,15 +5140,15 @@ public: class AstPragma final : public AstNode { private: - const AstPragmaType m_pragType; // Type of pragma + const VPragmaType m_pragType; // Type of pragma public: // Pragmas don't result in any output code, they're just flags that affect // other processing in verilator. - AstPragma(FileLine* fl, AstPragmaType pragType) + AstPragma(FileLine* fl, VPragmaType pragType) : ASTGEN_SUPER_Pragma(fl) , m_pragType{pragType} {} ASTNODE_NODE_FUNCS(Pragma) - AstPragmaType pragType() const { return m_pragType; } // *=type of the pragma + VPragmaType pragType() const { return m_pragType; } // *=type of the pragma virtual bool isPredictOptimizable() const override { return false; } virtual bool same(const AstNode* samep) const override { return pragType() == static_cast(samep)->pragType(); @@ -5211,6 +5277,28 @@ public: AstNode* widthp() const { return op4p(); } }; +class AstTracePushNamePrefix final : public AstNodeStmt { + const string m_prefix; // Prefix to add to signal names +public: + AstTracePushNamePrefix(FileLine* fl, const string& prefix) + : ASTGEN_SUPER_TracePushNamePrefix(fl) + , m_prefix{prefix} {} + ASTNODE_NODE_FUNCS(TracePushNamePrefix) + virtual bool same(const AstNode* samep) const override { return false; } + string prefix() const { return m_prefix; } +}; + +class AstTracePopNamePrefix final : public AstNodeStmt { + const unsigned m_count; // How many levels to pop +public: + AstTracePopNamePrefix(FileLine* fl, unsigned count) + : ASTGEN_SUPER_TracePopNamePrefix(fl) + , m_count{count} {} + ASTNODE_NODE_FUNCS(TracePopNamePrefix) + virtual bool same(const AstNode* samep) const override { return false; } + unsigned count() const { return m_count; } +}; + class AstTraceDecl final : public AstNodeStmt { // Trace point declaration // Separate from AstTraceInc; as a declaration can't be deleted @@ -5222,15 +5310,13 @@ private: const VNumRange m_bitRange; // Property of var the trace details const VNumRange m_arrayRange; // Property of var the trace details const uint32_t m_codeInc; // Code increment - const AstVarType m_varType; // Type of variable (for localparam vs. param) - const AstBasicDTypeKwd m_declKwd; // Keyword at declaration time + const VVarType m_varType; // Type of variable (for localparam vs. param) + const VBasicDTypeKwd m_declKwd; // Keyword at declaration time const VDirection m_declDirection; // Declared direction input/output etc - const bool m_isScoped; // Uses run-time scope (for interfaces) public: AstTraceDecl(FileLine* fl, const string& showname, AstVar* varp, // For input/output state etc - AstNode* valuep, const VNumRange& bitRange, const VNumRange& arrayRange, - bool isScoped) + AstNode* valuep, const VNumRange& bitRange, const VNumRange& arrayRange) : ASTGEN_SUPER_TraceDecl(fl) , m_showname{showname} , m_bitRange{bitRange} @@ -5240,8 +5326,7 @@ public: * (VL_EDATASIZE / 32))) // A code is always 32-bits , m_varType{varp->varType()} , m_declKwd{varp->declKwd()} - , m_declDirection{varp->declDirection()} - , m_isScoped{isScoped} { + , m_declDirection{varp->declDirection()} { dtypeFrom(valuep); addNOp1p(valuep); } @@ -5258,10 +5343,9 @@ public: uint32_t codeInc() const { return m_codeInc; } const VNumRange& bitRange() const { return m_bitRange; } const VNumRange& arrayRange() const { return m_arrayRange; } - AstVarType varType() const { return m_varType; } - AstBasicDTypeKwd declKwd() const { return m_declKwd; } + VVarType varType() const { return m_varType; } + VBasicDTypeKwd declKwd() const { return m_declKwd; } VDirection declDirection() const { return m_declDirection; } - bool isScoped() const { return m_isScoped; } AstNode* valuep() const { return op1p(); } }; @@ -5358,10 +5442,9 @@ public: class AstAttrOf final : public AstNode { private: // Return a value of a attribute, for example a LSB or array LSB of a signal - AstAttrType m_attrType; // What sort of extraction + VAttrType m_attrType; // What sort of extraction public: - AstAttrOf(FileLine* fl, AstAttrType attrtype, AstNode* fromp = nullptr, - AstNode* dimp = nullptr) + AstAttrOf(FileLine* fl, VAttrType attrtype, AstNode* fromp = nullptr, AstNode* dimp = nullptr) : ASTGEN_SUPER_AttrOf(fl) { setNOp1p(fromp); setNOp2p(dimp); @@ -5370,7 +5453,7 @@ public: ASTNODE_NODE_FUNCS(AttrOf) AstNode* fromp() const { return op1p(); } AstNode* dimp() const { return op2p(); } - AstAttrType attrType() const { return m_attrType; } + VAttrType attrType() const { return m_attrType; } virtual void dump(std::ostream& str = std::cout) const override; }; @@ -5471,8 +5554,9 @@ public: : (m_urandom ? "%f$urandom()" : "%f$random()"); } virtual string emitC() override { - return m_reset ? "VL_RAND_RESET_%nq(%nw, %P)" - : seedp() ? "VL_RANDOM_SEEDED_%nq%lq(%li)" + return m_reset ? "VL_RAND_RESET_%nq(%nw, %P)" + : seedp() + ? (urandom() ? "VL_URANDOM_SEEDED_%nq%lq(%li)" : "VL_RANDOM_SEEDED_%nq%lq(%li)") : isWide() ? "VL_RANDOM_%nq(%nw, %P)" // : "VL_RANDOM_%nq()"; } @@ -6258,7 +6342,7 @@ public: class AstNodeSystemUniop VL_NOT_FINAL : public AstNodeUniop { public: - AstNodeSystemUniop(AstType t, FileLine* fl, AstNode* lhsp) + AstNodeSystemUniop(VNType t, FileLine* fl, AstNode* lhsp) : AstNodeUniop(t, fl, lhsp) { dtypeSetDouble(); } @@ -6584,6 +6668,11 @@ public: // Binary ops class AstLogOr final : public AstNodeBiop { + // LOGOR with optional side effects + // Side effects currently used in some V3Width code + // TBD if this concept is generally adopted for side-effect tracking + // versus V3Const tracking it itself + bool m_sideEffect = false; // Has side effect, relies on short-circuiting public: AstLogOr(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : ASTGEN_SUPER_LogOr(fl, lhsp, rhsp) { @@ -6596,6 +6685,11 @@ public: virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { out.opLogOr(lhs, rhs); } + virtual bool same(const AstNode* samep) const override { + const AstLogOr* const sp = static_cast(samep); + return m_sideEffect == sp->m_sideEffect; + } + virtual void dump(std::ostream& str = std::cout) const override; virtual string emitVerilog() override { return "%k(%l %f|| %r)"; } virtual string emitC() override { return "VL_LOGOR_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } virtual string emitSimpleOperator() override { return "||"; } @@ -6605,6 +6699,9 @@ public: virtual bool sizeMattersLhs() const override { return false; } virtual bool sizeMattersRhs() const override { return false; } virtual int instrCount() const override { return widthInstrs() + INSTR_COUNT_BRANCH; } + virtual bool isPure() const override { return !m_sideEffect; } + void sideEffect(bool flag) { m_sideEffect = flag; } + bool sideEffect() const { return m_sideEffect; } }; class AstLogAnd final : public AstNodeBiop { public: @@ -8124,7 +8221,7 @@ public: class AstNodeSystemBiop VL_NOT_FINAL : public AstNodeBiop { public: - AstNodeSystemBiop(AstType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp) + AstNodeSystemBiop(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(t, fl, lhsp, rhsp) { dtypeSetDouble(); } @@ -8528,7 +8625,7 @@ private: const bool m_immediate; // Immediate assertion/cover string m_name; // Name to report public: - AstNodeCoverOrAssert(AstType t, FileLine* fl, AstNode* propp, AstNode* passsp, bool immediate, + AstNodeCoverOrAssert(VNType t, FileLine* fl, AstNode* propp, AstNode* passsp, bool immediate, const string& name = "") : AstNodeStmt{t, fl} , m_immediate{immediate} @@ -8596,7 +8693,7 @@ class AstNodeSimpleText VL_NOT_FINAL : public AstNodeText { private: bool m_tracking; // When emit, it's ok to parse the string to do indentation public: - AstNodeSimpleText(AstType t, FileLine* fl, const string& textp, bool tracking = false) + AstNodeSimpleText(VNType t, FileLine* fl, const string& textp, bool tracking = false) : AstNodeText(t, fl, textp) , m_tracking(tracking) {} ASTNODE_BASE_FUNCS(NodeSimpleText) @@ -8709,7 +8806,7 @@ class AstNodeFile VL_NOT_FINAL : public AstNode { private: string m_name; ///< Filename public: - AstNodeFile(AstType t, FileLine* fl, const string& name) + AstNodeFile(VNType t, FileLine* fl, const string& name) : AstNode(t, fl) { m_name = name; } @@ -8777,7 +8874,7 @@ private: bool m_isTrace : 1; // Function is related to tracing bool m_dontCombine : 1; // V3Combine shouldn't compare this func tree, it's special bool m_declPrivate : 1; // Declare it private - bool m_formCallTree : 1; // Make a global function to call entire tree of functions + bool m_isFinal : 1; // This is a function corresponding to a SystemVerilog 'final' block bool m_slow : 1; // Slow routine, called once or just at init time bool m_funcPublic : 1; // From user public task/function bool m_isConstructor : 1; // Is C class constructor @@ -8806,7 +8903,7 @@ public: m_isTrace = false; m_dontCombine = false; m_declPrivate = false; - m_formCallTree = false; + m_isFinal = false; m_slow = false; m_funcPublic = false; m_isConstructor = false; @@ -8830,6 +8927,9 @@ public: BROKEN_RTN((m_scopep && !m_scopep->brokeExists())); return nullptr; } + virtual void cloneRelink() override { + if (m_scopep && m_scopep->clonep()) m_scopep = m_scopep->clonep(); + } virtual bool maybePointedTo() const override { return true; } virtual void dump(std::ostream& str = std::cout) const override; virtual bool same(const AstNode* samep) const override { @@ -8856,13 +8956,13 @@ public: AstScope* scopep() const { return m_scopep; } void scopep(AstScope* nodep) { m_scopep = nodep; } string rtnTypeVoid() const { return ((m_rtnType == "") ? "void" : m_rtnType); } - bool dontCombine() const { return m_dontCombine || isTrace(); } + bool dontCombine() const { return m_dontCombine || isTrace() || entryPoint(); } void dontCombine(bool flag) { m_dontCombine = flag; } bool dontInline() const { return dontCombine() || slow() || funcPublic(); } bool declPrivate() const { return m_declPrivate; } void declPrivate(bool flag) { m_declPrivate = flag; } - bool formCallTree() const { return m_formCallTree; } - void formCallTree(bool flag) { m_formCallTree = flag; } + bool isFinal() const { return m_isFinal; } + void isFinal(bool flag) { m_isFinal = flag; } bool slow() const { return m_slow; } void slow(bool flag) { m_slow = flag; } bool funcPublic() const { return m_funcPublic; } @@ -9085,6 +9185,13 @@ public: } AstNode* stmtsp() const { return op1p(); } void addStmtsp(AstNode* nodep) { addOp1p(nodep); } + void addStmtsFirstp(AstNode* nodep) { + if (stmtsp()) { + stmtsp()->addHereThisAsNext(nodep); + } else { + addStmtsp(nodep); + } + } ExecMTask* execMTaskp() const { return m_execMTaskp; } void execMTaskp(ExecMTask* execMTaskp) { m_execMTaskp = execMTaskp; } virtual void dump(std::ostream& str = std::cout) const override; @@ -9133,7 +9240,7 @@ class AstTypeTable final : public AstNode { AstEmptyQueueDType* m_emptyQueuep = nullptr; AstQueueDType* m_queueIndexp = nullptr; AstVoidDType* m_voidp = nullptr; - AstBasicDType* m_basicps[AstBasicDTypeKwd::_ENUM_MAX]; + AstBasicDType* m_basicps[VBasicDTypeKwd::_ENUM_MAX]; // using DetailedMap = std::map; DetailedMap m_detailedMap; @@ -9141,12 +9248,20 @@ class AstTypeTable final : public AstNode { public: explicit AstTypeTable(FileLine* fl); ASTNODE_NODE_FUNCS(TypeTable) + virtual bool maybePointedTo() const override { return true; } + virtual const char* broken() const override { + BROKEN_RTN(m_emptyQueuep && !m_emptyQueuep->brokeExists()); + BROKEN_RTN(m_queueIndexp && !m_queueIndexp->brokeExists()); + BROKEN_RTN(m_voidp && !m_voidp->brokeExists()); + return nullptr; + } + virtual void cloneRelink() override { V3ERROR_NA; } AstNodeDType* typesp() const { return VN_AS(op1p(), NodeDType); } // op1 = List of dtypes void addTypesp(AstNodeDType* nodep) { addOp1p(nodep); } - AstBasicDType* findBasicDType(FileLine* fl, AstBasicDTypeKwd kwd); - AstBasicDType* findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kwd, int width, int widthMin, + AstBasicDType* findBasicDType(FileLine* fl, VBasicDTypeKwd kwd); + AstBasicDType* findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, int width, int widthMin, VSigning numeric); - AstBasicDType* findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kwd, const VNumRange& range, + AstBasicDType* findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, const VNumRange& range, int widthMin, VSigning numeric); AstBasicDType* findInsertSameDType(AstBasicDType* nodep); AstEmptyQueueDType* findEmptyQueueDType(FileLine* fl); @@ -9169,6 +9284,13 @@ class AstConstPool final : public AstNode { public: explicit AstConstPool(FileLine* fl); ASTNODE_NODE_FUNCS(ConstPool) + virtual bool maybePointedTo() const override { return true; } + virtual const char* broken() const override { + BROKEN_RTN(m_modp && !m_modp->brokeExists()); + BROKEN_RTN(m_scopep && !m_scopep->brokeExists()); + return nullptr; + } + virtual void cloneRelink() override { V3ERROR_NA; } AstModule* modp() const { return m_modp; } // Find a table (unpacked array) within the constant pool which is initialized with the @@ -9208,12 +9330,15 @@ public: AstNetlist(); ASTNODE_NODE_FUNCS(Netlist) virtual const char* broken() const override { + BROKEN_RTN(m_typeTablep && !m_typeTablep->brokeExists()); + BROKEN_RTN(m_constPoolp && !m_constPoolp->brokeExists()); BROKEN_RTN(m_dollarUnitPkgp && !m_dollarUnitPkgp->brokeExists()); BROKEN_RTN(m_evalp && !m_evalp->brokeExists()); BROKEN_RTN(m_dpiExportTriggerp && !m_dpiExportTriggerp->brokeExists()); BROKEN_RTN(m_topScopep && !m_topScopep->brokeExists()); return nullptr; } + virtual void cloneRelink() override { V3ERROR_NA; } virtual string name() const override { return "$root"; } virtual void dump(std::ostream& str) const override; AstNodeModule* modulesp() const { // op1 = List of modules diff --git a/src/V3AstUserAllocator.h b/src/V3AstUserAllocator.h index 896d19dfe..3be1cf481 100644 --- a/src/V3AstUserAllocator.h +++ b/src/V3AstUserAllocator.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -24,6 +24,7 @@ #include "V3Ast.h" #include +#include #include template class AstUserAllocatorBase VL_NOT_FINAL { @@ -72,15 +73,15 @@ protected: AstUserAllocatorBase() { // This simplifies statically as T_UserN is constant. In C++17, use 'if constexpr'. if (T_UserN == 1) { - AstUser1InUse::check(); + VNUser1InUse::check(); } else if (T_UserN == 2) { - AstUser2InUse::check(); + VNUser2InUse::check(); } else if (T_UserN == 3) { - AstUser3InUse::check(); + VNUser3InUse::check(); } else if (T_UserN == 4) { - AstUser4InUse::check(); + VNUser4InUse::check(); } else { - AstUser5InUse::check(); + VNUser5InUse::check(); } } @@ -89,12 +90,15 @@ protected: for (T_Data* const p : m_allocated) { delete p; } } + VL_UNCOPYABLE(AstUserAllocatorBase); + public: - // Get a reference to the user data - T_Data& operator()(T_Node* nodep) { + // Get a reference to the user data. If does not exist, construct it with given arguments. + template // + T_Data& operator()(T_Node* nodep, Args&&... args) { T_Data* userp = getUserp(nodep); if (!userp) { - userp = new T_Data; + userp = new T_Data{std::forward(args)...}; m_allocated.push_back(userp); setUserp(nodep, userp); } @@ -107,6 +111,9 @@ public: UASSERT_OBJ(userp, nodep, "Missing User data on const AstNode"); return *userp; } + + // Get a pointer to the user data if exists, otherwise nullptr + T_Data* tryGet(const T_Node* nodep) { return getUserp(nodep); } }; // User pointer allocator classes. T_Node is the type of node the allocator should be applied to diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index 76e540747..75efa0f03 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -41,7 +41,7 @@ private: // NODE STATE // Entire netlist: // AstNodeFTask::user1 -> bool, 1=processed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; bool m_anyFuncInBegin = false; public: @@ -56,7 +56,7 @@ public: //###################################################################### -class BeginVisitor final : public AstNVisitor { +class BeginVisitor final : public VNVisitor { private: // STATE BeginState* const m_statep; // Current global state @@ -271,7 +271,7 @@ public: //###################################################################### -class BeginRelinkVisitor final : public AstNVisitor { +class BeginRelinkVisitor final : public VNVisitor { // Replace tasks with new pointer private: // NODE STATE diff --git a/src/V3Begin.h b/src/V3Begin.h index b1ca0c3fe..491821e3d 100644 --- a/src/V3Begin.h +++ b/src/V3Begin.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Branch.cpp b/src/V3Branch.cpp index da13df889..a7d751d37 100644 --- a/src/V3Branch.cpp +++ b/src/V3Branch.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -35,12 +35,12 @@ //###################################################################### // Branch state, as a visitor of each AstNode -class BranchVisitor final : public AstNVisitor { +class BranchVisitor final : public VNVisitor { private: // NODE STATE // Entire netlist: // AstFTask::user1() -> int. Number of references - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE int m_likely = false; // Excuses for branch likely taken diff --git a/src/V3Branch.h b/src/V3Branch.h index d693f6488..8ad39daa4 100644 --- a/src/V3Branch.h +++ b/src/V3Branch.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp index f1e422ea1..42f57e4e8 100644 --- a/src/V3Broken.cpp +++ b/src/V3Broken.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -137,36 +137,10 @@ public: bool V3Broken::isLinkable(const AstNode* nodep) { return s_linkableTable.isLinkable(nodep); } -//###################################################################### -// Mark every node in the tree - -class BrokenMarkVisitor final : public AstNVisitor { -private: - const uint8_t m_brokenCntCurrent = s_brokenCntGlobal.get(); - - // VISITORS - virtual void visit(AstNode* nodep) override { -#ifdef VL_LEAK_CHECKS - UASSERT_OBJ(s_allocTable.isAllocated(nodep), nodep, - "AstNode is in tree, but not allocated"); -#endif - UASSERT_OBJ(nodep->brokenState() != m_brokenCntCurrent, nodep, - "AstNode is already in tree at another location"); - if (nodep->maybePointedTo()) s_linkableTable.addLinkable(nodep); - nodep->brokenState(m_brokenCntCurrent); - iterateChildrenConst(nodep); - } - -public: - // CONSTRUCTORS - explicit BrokenMarkVisitor(AstNetlist* nodep) { iterate(nodep); } - virtual ~BrokenMarkVisitor() override = default; -}; - //###################################################################### // Check every node in tree -class BrokenCheckVisitor final : public AstNVisitor { +class BrokenCheckVisitor final : public VNVisitor { bool m_inScope = false; // Under AstScope // Constants for marking we are under/not under a node @@ -225,7 +199,7 @@ private: while (nodep) { processAndIterate(nodep); nodep = nodep->nextp(); - }; + } } void pushLocalScope() { if (m_cfuncp) m_localsStack.emplace_back(); @@ -246,6 +220,12 @@ private: && !VN_AS(nodep->lhsp(), NodeVarRef)->access().isWriteOrRW()), nodep, "Assignment LHS is not an lvalue"); } + virtual void visit(AstRelease* nodep) override { + processAndIterate(nodep); + UASSERT_OBJ(!(v3Global.assertDTypesResolved() && VN_IS(nodep->lhsp(), NodeVarRef) + && !VN_AS(nodep->lhsp(), NodeVarRef)->access().isWriteOrRW()), + nodep, "Release LHS is not an lvalue"); + } virtual void visit(AstScope* nodep) override { VL_RESTORER(m_inScope); { @@ -343,8 +323,23 @@ void V3Broken::brokenAll(AstNetlist* nodep) { UINFO(1, "Broken called under broken, skipping recursion.\n"); // LCOV_EXCL_LINE } else { inBroken = true; - const BrokenMarkVisitor mvisitor{nodep}; + + // Mark every node in the tree + const uint8_t brokenCntCurrent = s_brokenCntGlobal.get(); + nodep->foreach([brokenCntCurrent](AstNode* nodep) { +#ifdef VL_LEAK_CHECKS + UASSERT_OBJ(s_allocTable.isAllocated(nodep), nodep, + "AstNode is in tree, but not allocated"); +#endif + UASSERT_OBJ(nodep->brokenState() != brokenCntCurrent, nodep, + "AstNode is already in tree at another location"); + if (nodep->maybePointedTo()) s_linkableTable.addLinkable(nodep); + nodep->brokenState(brokenCntCurrent); + }); + + // Check every node in tree const BrokenCheckVisitor cvisitor{nodep}; + s_allocTable.checkForLeaks(); s_linkableTable.clear(); s_brokenCntGlobal.inc(); diff --git a/src/V3Broken.h b/src/V3Broken.h index 94387ef06..b6d6b2419 100644 --- a/src/V3Broken.h +++ b/src/V3Broken.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -23,8 +23,8 @@ //============================================================================ // Forward declare so we can include this in V3Ast.h -class AstNode; class AstNetlist; +class AstNode; class V3Broken final { public: diff --git a/src/V3CCtors.cpp b/src/V3CCtors.cpp index 9ce40651f..2ebb9f73c 100644 --- a/src/V3CCtors.cpp +++ b/src/V3CCtors.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -118,7 +118,7 @@ public: rootFuncp->addStmtsp(callp); } } - }; + } private: VL_UNCOPYABLE(V3CCtorsBuilder); diff --git a/src/V3CCtors.h b/src/V3CCtors.h index f48652ed9..41ad3e49c 100644 --- a/src/V3CCtors.h +++ b/src/V3CCtors.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,9 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" - //============================================================================ class V3CCtors final { diff --git a/src/V3CUse.cpp b/src/V3CUse.cpp index 2b4543bfe..cf52c03da 100644 --- a/src/V3CUse.cpp +++ b/src/V3CUse.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,10 +36,10 @@ // Visit within a module all nodes and data types they reference, finding // any classes so we can make sure they are defined when Verilated code // compiles -class CUseVisitor final : public AstNVisitor { +class CUseVisitor final : public VNVisitor { // NODE STATE // AstNode::user1() -> bool. True if already visited - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // MEMBERS bool m_impOnly = false; // In details needed only for implementation diff --git a/src/V3CUse.h b/src/V3CUse.h index f2ec4afbb..88e1e0425 100644 --- a/src/V3CUse.h +++ b/src/V3CUse.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,9 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" - //============================================================================ class V3CUse final { diff --git a/src/V3Case.cpp b/src/V3Case.cpp index a80bf9146..db83eff66 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -50,7 +50,7 @@ //###################################################################### -class CaseLintVisitor final : public AstNVisitor { +class CaseLintVisitor final : public VNVisitor { private: const AstNodeCase* m_caseExprp = nullptr; // Under a CASE value node, if so the relevant case statement @@ -117,12 +117,12 @@ public: //###################################################################### // Case state, as a visitor of each AstNode -class CaseVisitor final : public AstNVisitor { +class CaseVisitor final : public VNVisitor { private: // NODE STATE // Cleared each Case // AstIf::user3() -> bool. Set true to indicate clone not needed - const AstUser3InUse m_inuser3; + const VNUser3InUse m_inuser3; // STATE VDouble0 m_statCaseFast; // Statistic tracking diff --git a/src/V3Case.h b/src/V3Case.h index 0c503d8bc..c52a90246 100644 --- a/src/V3Case.h +++ b/src/V3Case.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,8 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; +class AstNodeCase; //============================================================================ diff --git a/src/V3Cast.cpp b/src/V3Cast.cpp index 2436d532c..d0a26e6c9 100644 --- a/src/V3Cast.cpp +++ b/src/V3Cast.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -49,12 +49,12 @@ //###################################################################### // Cast state, as a visitor of each AstNode -class CastVisitor final : public AstNVisitor { +class CastVisitor final : public VNVisitor { private: // NODE STATE // Entire netlist: // AstNode::user() // bool. Indicates node is of known size - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE @@ -63,7 +63,7 @@ private: void insertCast(AstNode* nodep, int needsize) { // We'll insert ABOVE passed node UINFO(4, " NeedCast " << nodep << endl); - AstNRelinker relinkHandle; + VNRelinker relinkHandle; nodep->unlinkFrBack(&relinkHandle); // AstCCast* const castp @@ -102,7 +102,7 @@ private: void ensureNullChecked(AstNode* nodep) { // TODO optimize to track null checked values and avoid where possible if (!VN_IS(nodep->backp(), NullCheck)) { - AstNRelinker relinkHandle; + VNRelinker relinkHandle; nodep->unlinkFrBack(&relinkHandle); AstNode* const newp = new AstNullCheck{nodep->fileline(), nodep}; relinkHandle.relink(newp); diff --git a/src/V3Cast.h b/src/V3Cast.h index b73cb52da..716fba353 100644 --- a/src/V3Cast.h +++ b/src/V3Cast.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp index ee0f91ac6..871a5fd8c 100644 --- a/src/V3Cdc.cpp +++ b/src/V3Cdc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -41,7 +41,7 @@ constexpr int CDC_WEIGHT_ASYNC = 0x1000; // Weight for edges that feed async lo //###################################################################### -class CdcBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class CdcBaseVisitor VL_NOT_FINAL : public VNVisitor { public: VL_DEBUG_FUNC; // Declare debug() }; @@ -140,7 +140,7 @@ private: // NODE STATE // Entire netlist: // {statement}Node::user3 -> bool, indicating not hazard - std::ofstream* m_ofp; // Output file + std::ofstream* const m_ofp = nullptr; // Output file string m_prefix; virtual void visit(AstNode* nodep) override { @@ -217,9 +217,9 @@ private: // AstVarScope::user2 -> bool Used in sensitivity list // {statement}Node::user1p -> CdcLogicVertex* for this statement // AstNode::user3 -> bool True indicates to print %% (via V3EmitV) - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; // STATE V3Graph m_graph; // Scoreboard of var usages/dependencies @@ -715,6 +715,7 @@ private: // Ignores virtual void visit(AstInitial*) override {} + virtual void visit(AstInitialAutomatic*) override {} virtual void visit(AstTraceDecl*) override {} virtual void visit(AstCoverToggle*) override {} virtual void visit(AstNodeDType*) override {} diff --git a/src/V3Cdc.h b/src/V3Cdc.h index cc3470d30..31d26d879 100644 --- a/src/V3Cdc.h +++ b/src/V3Cdc.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Changed.cpp b/src/V3Changed.cpp index f4dbdde75..bddcf76a7 100644 --- a/src/V3Changed.cpp +++ b/src/V3Changed.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,7 +32,6 @@ #include "V3Global.h" #include "V3Ast.h" #include "V3Changed.h" -#include "V3EmitCBase.h" #include @@ -115,47 +114,44 @@ public: //###################################################################### // Utility visitor to find elements to be compared -class ChangedInsertVisitor final : public AstNVisitor { +class ChangedInsertVisitor final : public VNVisitor { private: // STATE - ChangedState* m_statep; // Shared state across visitors - AstVarScope* m_vscp; // Original (non-change) variable we're change-detecting - AstVarScope* m_newvscp; // New (change detect) variable we're change-detecting - AstNode* m_varEqnp; // Original var's equation to get var value - AstNode* m_newLvEqnp; // New var's equation to read value - AstNode* m_newRvEqnp; // New var's equation to set value - uint32_t m_detects; // # detects created + ChangedState& m_state; // Shared state across visitors + AstVarScope* const m_vscp; // Original (non-change) variable we're change-detecting + AstVarScope* m_newvscp = nullptr; // New (change detect) variable we're change-detecting + AstNode* m_varEqnp = nullptr; // Original var's equation to get var value + AstNode* m_newLvEqnp = nullptr; // New var's equation to read value + AstNode* m_newRvEqnp = nullptr; // New var's equation to set value + uint32_t m_detects = 0; // # detects created // CONSTANTS - enum MiscConsts { - DETECTARRAY_MAX_INDEXES = 256 // How many indexes before error - // Ok to increase this, but may result in much slower model - }; + // How many indexes before error. Ok to increase this, but may result in much slower model + static constexpr uint32_t DETECTARRAY_MAX_INDEXES = 256; void newChangeDet() { if (++m_detects > DETECTARRAY_MAX_INDEXES) { m_vscp->v3warn(E_DETECTARRAY, "Unsupported: Can't detect more than " - << cvtToStr(DETECTARRAY_MAX_INDEXES) + << DETECTARRAY_MAX_INDEXES << " array indexes (probably with UNOPTFLAT warning suppressed): " << m_vscp->prettyName() << '\n' << m_vscp->warnMore() << "... Could recompile with DETECTARRAY_MAX_INDEXES increased"); return; } - m_statep->maybeCreateChgFuncp(); + m_state.maybeCreateChgFuncp(); AstChangeDet* const changep = new AstChangeDet{ m_vscp->fileline(), m_varEqnp->cloneTree(true), m_newRvEqnp->cloneTree(true)}; - m_statep->m_chgFuncp->addStmtsp(changep); + m_state.m_chgFuncp->addStmtsp(changep); AstAssign* const initp = new AstAssign{m_vscp->fileline(), m_newLvEqnp->cloneTree(true), m_varEqnp->cloneTree(true)}; - m_statep->m_chgFuncp->addFinalsp(initp); + m_state.m_chgFuncp->addFinalsp(initp); // Later code will expand words which adds to GCC compile time, // so add penalty based on word width also - const EmitCBaseCounterVisitor visitor{initp}; - m_statep->m_numStmts += visitor.count() + m_varEqnp->widthWords(); + m_state.m_numStmts += initp->nodeCount() + m_varEqnp->widthWords(); } virtual void visit(AstBasicDType*) override { // @@ -204,14 +200,13 @@ private: public: // CONSTRUCTORS - ChangedInsertVisitor(AstVarScope* vscp, ChangedState* statep) { + ChangedInsertVisitor(AstVarScope* vscp, ChangedState& state) + : m_state{state} + , m_vscp{vscp} { // DPI export trigger should never need change detect. See similar assertions in V3Order // (OrderVisitor::nodeMarkCircular), and V3GenClk (GenClkRenameVisitor::genInpClk). UASSERT_OBJ(vscp != v3Global.rootp()->dpiExportTriggerp(), vscp, "DPI export trigger should not need change detect"); - m_statep = statep; - m_vscp = vscp; - m_detects = 0; { AstVar* const varp = m_vscp->varp(); const string newvarname{"__Vchglast__" + m_vscp->scopep()->nameDotless() + "__" @@ -221,10 +216,10 @@ public: // ... // CHANGEDET(VARREF(_last), VARREF(var)) AstVar* const newvarp - = new AstVar{varp->fileline(), AstVarType::MODULETEMP, newvarname, varp}; - m_statep->m_topModp->addStmtp(newvarp); - m_newvscp = new AstVarScope{m_vscp->fileline(), m_statep->m_scopetopp, newvarp}; - m_statep->m_scopetopp->addVarp(m_newvscp); + = new AstVar{varp->fileline(), VVarType::MODULETEMP, newvarname, varp}; + m_state.m_topModp->addStmtp(newvarp); + m_newvscp = new AstVarScope{m_vscp->fileline(), m_state.m_scopetopp, newvarp}; + m_state.m_scopetopp->addVarp(m_newvscp); m_varEqnp = new AstVarRef{m_vscp->fileline(), m_vscp, VAccess::READ}; m_newLvEqnp = new AstVarRef{m_vscp->fileline(), m_newvscp, VAccess::WRITE}; @@ -239,72 +234,22 @@ public: VL_UNCOPYABLE(ChangedInsertVisitor); }; -//###################################################################### -// Changed state, as a visitor of each AstNode - -class ChangedVisitor final : public AstNVisitor { -private: - // NODE STATE - // Entire netlist: - // AstVarScope::user1() -> bool. True indicates processed - const AstUser1InUse m_inuser1; - - // STATE - ChangedState* const m_statep; // Shared state across visitors - - // METHODS - VL_DEBUG_FUNC; // Declare debug() - - void genChangeDet(AstVarScope* vscp) { - vscp->v3warn(IMPERFECTSCH, "Imperfect scheduling of variable: " << vscp->prettyNameQ()); - { ChangedInsertVisitor{vscp, m_statep}; } - } - - // VISITORS - virtual void visit(AstNodeModule* nodep) override { - UINFO(4, " MOD " << nodep << endl); - if (nodep->isTop()) m_statep->m_topModp = nodep; - iterateChildren(nodep); - } - - virtual void visit(AstTopScope* nodep) override { - UINFO(4, " TS " << nodep << endl); - // Clearing - AstNode::user1ClearTree(); - // Prep for if make change detection function - AstScope* const scopep = nodep->scopep(); - UASSERT_OBJ(scopep, nodep, "No scope found on top level, perhaps you have no statements?"); - m_statep->m_scopetopp = scopep; - - iterateChildren(nodep); - } - virtual void visit(AstVarScope* nodep) override { - if (nodep->isCircular()) { - UINFO(8, " CIRC " << nodep << endl); - if (!nodep->user1SetOnce()) genChangeDet(nodep); - } - } - //-------------------- - virtual void visit(AstNodeMath*) override {} // Accelerate - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - ChangedVisitor(AstNetlist* nodep, ChangedState* statep) - : m_statep{statep} { - iterate(nodep); - } - virtual ~ChangedVisitor() override = default; -}; - //###################################################################### // Changed class functions void V3Changed::changedAll(AstNetlist* nodep) { UINFO(2, __FUNCTION__ << ": " << endl); - { - ChangedState state; - ChangedVisitor{nodep, &state}; - } // Destruct before checking + + ChangedState state; + state.m_scopetopp = nodep->topScopep()->scopep(); + state.m_topModp = nodep->topModulep(); + nodep->foreach([&state](AstVarScope* vscp) { + if (vscp->isCircular()) { + vscp->v3warn(IMPERFECTSCH, + "Imperfect scheduling of variable: " << vscp->prettyNameQ()); + ChangedInsertVisitor{vscp, state}; + } + }); + V3Global::dumpCheckGlobalTree("changed", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); } diff --git a/src/V3Changed.h b/src/V3Changed.h index 48d96a58b..f9afbec85 100644 --- a/src/V3Changed.h +++ b/src/V3Changed.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Class.cpp b/src/V3Class.cpp index 421319f85..c7bbc91c3 100644 --- a/src/V3Class.cpp +++ b/src/V3Class.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -29,18 +29,21 @@ //###################################################################### -class ClassVisitor final : public AstNVisitor { +class ClassVisitor final : public VNVisitor { private: + // NODE STATE + // AstClass::user1() -> bool. True if iterated already + // AstVar::user1p() -> AstVarScope* Scope used with this var + const VNUser1InUse m_inuser1; + // MEMBERS - const AstUser1InUse m_inuser1; string m_prefix; // String prefix to add to name based on hier + AstNodeModule* m_classPackagep = nullptr; // Package moving into const AstScope* m_classScopep = nullptr; // Package moving scopes into AstScope* m_packageScopep = nullptr; // Class package scope const AstNodeFTask* m_ftaskp = nullptr; // Current task - std::vector> m_moves; - - // NODE STATE - // AstClass::user1() -> bool. True if iterated already + std::vector> m_toScopeMoves; + std::vector> m_toPackageMoves; // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -54,15 +57,19 @@ private: // Make containing package // Note origName is the same as the class origName so errors look correct AstClassPackage* const packagep - = new AstClassPackage(nodep->fileline(), nodep->origName()); + = new AstClassPackage{nodep->fileline(), nodep->origName()}; packagep->name(nodep->name() + "__Vclpkg"); nodep->classOrPackagep(packagep); packagep->classp(nodep); v3Global.rootp()->addModulep(packagep); // Add package to hierarchy - AstCell* const cellp - = new AstCell(packagep->fileline(), packagep->fileline(), packagep->name(), - packagep->name(), nullptr, nullptr, nullptr); + AstCell* const cellp = new AstCell{packagep->fileline(), + packagep->fileline(), + packagep->name(), + packagep->name(), + nullptr, + nullptr, + nullptr}; cellp->modp(packagep); v3Global.rootp()->topModulep()->addStmtp(cellp); // Find class's scope @@ -75,14 +82,16 @@ private: // Add scope AstScope* const scopep - = new AstScope(nodep->fileline(), packagep, classScopep->name(), - classScopep->aboveScopep(), classScopep->aboveCellp()); + = new AstScope{nodep->fileline(), packagep, classScopep->name(), + classScopep->aboveScopep(), classScopep->aboveCellp()}; packagep->addStmtp(scopep); // Iterate VL_RESTORER(m_prefix); + VL_RESTORER(m_classPackagep); VL_RESTORER(m_classScopep); VL_RESTORER(m_packageScopep); { + m_classPackagep = packagep; m_classScopep = classScopep; m_packageScopep = scopep; m_prefix = nodep->name() + "__02e"; // . @@ -100,10 +109,19 @@ private: virtual void visit(AstVar* nodep) override { iterateChildren(nodep); - // Don't move now, or wouldn't keep interating the class - // TODO move class statics too - if (m_packageScopep && m_ftaskp && m_ftaskp->lifetime().isStatic()) { - m_moves.push_back(std::make_pair(nodep, m_packageScopep)); + if (m_packageScopep) { + if (m_ftaskp && m_ftaskp->lifetime().isStatic()) { + // Move later, or we wouldn't keep interating the class + // We're really moving the VarScope but we might not + // have a pointer to it yet + m_toScopeMoves.push_back(std::make_pair(nodep, m_packageScopep)); + } + if (!m_ftaskp && nodep->lifetime().isStatic()) { + m_toPackageMoves.push_back(std::make_pair(nodep, m_classPackagep)); + // We're really moving the VarScope but we might not + // have a pointer to it yet + m_toScopeMoves.push_back(std::make_pair(nodep, m_packageScopep)); + } } } @@ -118,19 +136,23 @@ private: m_ftaskp = nodep; iterateChildren(nodep); if (m_packageScopep && nodep->lifetime().isStatic()) { - m_moves.push_back(std::make_pair(nodep, m_packageScopep)); + m_toScopeMoves.push_back(std::make_pair(nodep, m_packageScopep)); } } } - virtual void visit(AstCFunc* nodep) override { iterateChildren(nodep); // Don't move now, or wouldn't keep interating the class // TODO move function statics only // if (m_classScopep) { - // m_moves.push_back(std::make_pair(nodep, m_classScopep)); + // m_toScopeMoves.push_back(std::make_pair(nodep, m_classScopep)); //} } + virtual void visit(AstInitial* nodep) override { + // But not AstInitialAutomatic, which remains under the class + iterateChildren(nodep); + if (m_packageScopep) { m_toScopeMoves.push_back(std::make_pair(nodep, m_packageScopep)); } + } virtual void visit(AstNodeMath* nodep) override {} // Short circuit virtual void visit(AstNodeStmt* nodep) override {} // Short circuit @@ -140,15 +162,31 @@ public: // CONSTRUCTORS explicit ClassVisitor(AstNetlist* nodep) { iterate(nodep); } virtual ~ClassVisitor() override { - for (auto moved : m_moves) { - if (VN_IS(moved.first, NodeFTask)) { - moved.second->addActivep(moved.first->unlinkFrBack()); - } else if (VN_IS(moved.first, Var)) { - AstVarScope* const scopep = VN_AS(moved.first->user1p(), VarScope); - scopep->unlinkFrBack(); - moved.second->addVarp(scopep); + for (auto moved : m_toScopeMoves) { + AstNode* const nodep = moved.first; + AstScope* const scopep = moved.second; + UINFO(9, "moving " << nodep << " to " << scopep << endl); + if (VN_IS(nodep, NodeFTask)) { + scopep->addActivep(nodep->unlinkFrBack()); + } else if (VN_IS(nodep, Var)) { + AstVarScope* const vscp = VN_AS(nodep->user1p(), VarScope); + vscp->scopep(scopep); + vscp->unlinkFrBack(); + scopep->addVarp(vscp); + } else if (VN_IS(nodep, Initial)) { + nodep->unlinkFrBack(); + scopep->addActivep(nodep); + } else { + nodep->v3fatalSrc("Bad case"); } } + for (auto moved : m_toPackageMoves) { + AstNode* const nodep = moved.first; + AstNodeModule* const modp = moved.second; + UINFO(9, "moving " << nodep << " to " << modp << endl); + nodep->unlinkFrBack(); + modp->addStmtp(nodep); + } } }; diff --git a/src/V3Class.h b/src/V3Class.h index 10902fe06..6eed73f71 100644 --- a/src/V3Class.h +++ b/src/V3Class.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp index 666d5ccc1..613b681d7 100644 --- a/src/V3Clean.cpp +++ b/src/V3Clean.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -35,16 +35,16 @@ //###################################################################### // Clean state, as a visitor of each AstNode -class CleanVisitor final : public AstNVisitor { +class CleanVisitor final : public VNVisitor { private: // NODE STATE // Entire netlist: // AstNode::user() -> CleanState. For this node, 0==UNKNOWN // AstNode::user2() -> bool. True indicates widthMin has been propagated // AstNodeDType::user3() -> AstNodeDType*. Alternative node with C size - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; // TYPES enum CleanState : uint8_t { CS_UNKNOWN, CS_CLEAN, CS_DIRTY }; @@ -120,7 +120,7 @@ private: // Operate on nodes void insertClean(AstNode* nodep) { // We'll insert ABOVE passed node UINFO(4, " NeedClean " << nodep << endl); - AstNRelinker relinkHandle; + VNRelinker relinkHandle; nodep->unlinkFrBack(&relinkHandle); // computeCppWidth(nodep); diff --git a/src/V3Clean.h b/src/V3Clean.h index 6ba7364ba..ee3405c03 100644 --- a/src/V3Clean.h +++ b/src/V3Clean.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index 2989aea3c..77b655963 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,14 +33,13 @@ #include "V3Global.h" #include "V3Clock.h" #include "V3Ast.h" -#include "V3EmitCBase.h" #include //###################################################################### // Convert every WRITE AstVarRef to a READ ref -class ConvertWriteRefsToRead final : public AstNVisitor { +class ConvertWriteRefsToRead final : public VNVisitor { private: // MEMBERS AstNode* m_result = nullptr; @@ -68,12 +67,12 @@ public: //###################################################################### // Clock state, as a visitor of each AstNode -class ClockVisitor final : public AstNVisitor { +class ClockVisitor final : public VNVisitor { private: // NODE STATE // Cleared each Module: // AstVarScope::user1p() -> AstVarScope*. Temporary signal that was created. - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE AstNodeModule* m_modp = nullptr; // Current module @@ -99,7 +98,7 @@ private: } const string newvarname = (string("__Vclklast__") + vscp->scopep()->nameDotless() + "__" + varp->name()); - AstVar* const newvarp = new AstVar(vscp->fileline(), AstVarType::MODULETEMP, newvarname, + AstVar* const newvarp = new AstVar(vscp->fileline(), VVarType::MODULETEMP, newvarname, VFlagLogicPacked(), 1); newvarp->noReset(true); // Reset by below assign m_modp->addStmtp(newvarp); @@ -207,8 +206,7 @@ private: } void splitCheck(AstCFunc* ofuncp) { if (!v3Global.opt.outputSplitCFuncs() || !ofuncp->stmtsp()) return; - if (EmitCBaseCounterVisitor(ofuncp->stmtsp()).count() < v3Global.opt.outputSplitCFuncs()) - return; + if (ofuncp->nodeCount() < v3Global.opt.outputSplitCFuncs()) return; int funcnum = 0; int func_stmts = 0; @@ -220,11 +218,12 @@ private: if (ofuncp->finalsp()) tempp->addStmtsp(ofuncp->finalsp()->unlinkFrBackWithNext()); while (tempp->stmtsp()) { AstNode* const itemp = tempp->stmtsp()->unlinkFrBack(); - const int stmts = EmitCBaseCounterVisitor(itemp).count(); + const int stmts = itemp->nodeCount(); if (!funcp || (func_stmts + stmts) > v3Global.opt.outputSplitCFuncs()) { // Make a new function - funcp = new AstCFunc{ofuncp->fileline(), ofuncp->name() + cvtToStr(++funcnum), - m_topScopep->scopep()}; + funcp + = new AstCFunc{ofuncp->fileline(), ofuncp->name() + "__" + cvtToStr(funcnum++), + m_topScopep->scopep()}; funcp->dontCombine(true); funcp->isStatic(false); funcp->isLoose(true); @@ -323,8 +322,8 @@ private: virtual void visit(AstCFunc* nodep) override { iterateChildren(nodep); // Link to global function - if (nodep->formCallTree()) { - UINFO(4, " formCallTree " << nodep << endl); + if (nodep->isFinal()) { + UINFO(4, " isFinal " << nodep << endl); AstCCall* const callp = new AstCCall(nodep->fileline(), nodep); m_finalFuncp->addStmtsp(callp); } diff --git a/src/V3Clock.h b/src/V3Clock.h index 4186ec1f6..d000abc77 100644 --- a/src/V3Clock.h +++ b/src/V3Clock.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Combine.cpp b/src/V3Combine.cpp index 89b81accd..eaf5e3708 100644 --- a/src/V3Combine.cpp +++ b/src/V3Combine.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -27,195 +27,203 @@ #include "V3DupFinder.h" #include "V3Stats.h" #include "V3Ast.h" +#include "V3AstUserAllocator.h" -#include -#include +#include #include -//###################################################################### - -class CombBaseVisitor VL_NOT_FINAL : public AstNVisitor { -protected: - // STATE - - // METHODS - virtual ~CombBaseVisitor() override = default; - VL_DEBUG_FUNC; // Declare debug() -}; - -//###################################################################### -// Combine replacement function - -class CombCallVisitor final : CombBaseVisitor { - // Find all CCALLS of each CFUNC, so that we can later rename them -private: +class CombineVisitor final : VNVisitor { // NODE STATE - std::multimap m_callMmap; // Associative array of {function}{call} - // METHODS -public: - void replaceFunc(AstCFunc* oldfuncp, AstCFunc* newfuncp) { - if (oldfuncp == newfuncp) return; - if (newfuncp) { - UINFO(4, " Replace " << oldfuncp << " -WITH-> " << newfuncp << endl); - } else { - UINFO(4, " Remove " << oldfuncp << endl); - } - // Note: m_callMmap modified in loop, so not using equal_range. - for (auto it = m_callMmap.find(oldfuncp); it != m_callMmap.end(); - it = m_callMmap.find(oldfuncp)) { - AstCCall* const oldp = it->second; - UINFO(4, " Called " << oldp << endl); - UASSERT_OBJ(oldp->funcp() == oldfuncp, oldp, - "Call list broken, points to call w/different func"); - if (newfuncp) { - // Replace call to oldfuncp with call to newfuncp - AstNode* const argsp - = oldp->argsp() ? oldp->argsp()->unlinkFrBackWithNext() : nullptr; - AstCCall* const newp = new AstCCall(oldp->fileline(), newfuncp, argsp); - newp->selfPointer(oldp->selfPointer()); - newp->argTypes(oldp->argTypes()); - addCall(newp); // Fix the table, in case the newfuncp itself gets replaced - oldp->replaceWith(newp); - } else { - // Just deleting empty function - oldp->unlinkFrBack(); - } - VL_DO_DANGLING(pushDeletep(oldp), oldp); - m_callMmap.erase(it); // Fix the table, This call has been replaced - } - } - // METHODS - void addCall(AstCCall* nodep) { m_callMmap.emplace(nodep->funcp(), nodep); } + // AstNodeModule::user1() List of AstCFuncs in this module (via m_cfuncs) + // AstCFunc::user1() List of AstCCalls to this function (via m_callSites) + // AstCFunc::user2() bool: Already replaced (in 'process') + // AstCFunc::user3() bool: Marks functions earlier in iteration order (in 'combinePass') + // *::user4() Used by V3Hasher + const VNUser1InUse m_user1InUse; -private: - // VISITORS - virtual void visit(AstCCall* nodep) override { - if (nodep->funcp()->dontCombine()) return; - addCall(nodep); - } - // LCOV_EXCL_START - virtual void visit(AstAddrOfCFunc* nodep) override { - // We cannot yet handle references via AstAddrOfCFunc, but currently those are - // only used in tracing functions, which are not combined. Blow up in case this changes. - if (nodep->funcp()->dontCombine()) return; - nodep->v3fatalSrc( - "Don't know how to combine functions that are referenced via AstAddrOfCFunc"); - } - // LCOV_EXCL_END - // Speed things up - virtual void visit(AstNodeAssign*) override {} - virtual void visit(AstNodeMath*) override {} - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - CombCallVisitor() = default; - virtual ~CombCallVisitor() override = default; - void main(AstNetlist* nodep) { iterate(nodep); } -}; - -//###################################################################### -// Combine state, as a visitor of each AstNode - -class CombineVisitor final : CombBaseVisitor { -private: - // NODE STATE - // Entire netlist: - const AstUser3InUse m_user3InUse; // Marks replaced AstCFuncs - // AstUser4InUse part of V3Hasher in V3DupFinder + // TYPES + using funcit_t = std::list::iterator; + struct CFuncs { + std::list m_fast; + std::list m_slow; + }; // STATE + AstUser1Allocator m_cfuncs; // AstCFuncs under module + AstUser1Allocator> m_callSites; // Call sites of the AstCFunc + AstNodeModule* m_modp = nullptr; // Current module + const V3Hasher m_hasher; // For hashing VDouble0 m_cfuncsCombined; // Statistic tracking - CombCallVisitor m_call; // Tracking of function call users - V3DupFinder m_dupFinder; // Duplicate finder for CFuncs in module // METHODS - void walkEmptyFuncs() { - for (const auto& itr : m_dupFinder) { - AstCFunc* const oldfuncp = VN_AS(itr.second, CFunc); - UASSERT_OBJ(oldfuncp, itr.second, "Not a CFunc in hash"); - if (!oldfuncp->emptyBody()) continue; - UASSERT_OBJ(!oldfuncp->dontCombine(), oldfuncp, - "dontCombine function should not be in hash"); + VL_DEBUG_FUNC; // Declare debug() - // Remove calls to empty function - UASSERT_OBJ(!oldfuncp->user3(), oldfuncp, "Should not be processed yet"); - UINFO(5, " Drop empty CFunc " << itr.first << " " << oldfuncp << endl); - oldfuncp->user3SetOnce(); // Mark replaced - m_call.replaceFunc(oldfuncp, nullptr); - oldfuncp->unlinkFrBack(); - VL_DO_DANGLING(pushDeletep(oldfuncp), oldfuncp); + void removeEmptyFunctions(std::list& funcps) { + for (funcit_t it = funcps.begin(), nit; it != funcps.end(); it = nit) { + AstCFunc* const funcp = *it; + nit = it; + ++nit; + + if (funcp->emptyBody()) { + // Delete call sites + for (AstCCall* const callp : m_callSites(funcp)) { + VL_DO_DANGLING(callp->unlinkFrBack()->deleteTree(), callp); + } + m_callSites(funcp).clear(); + // Remove from list + funcps.erase(it); + // Delete function + VL_DO_DANGLING(funcp->unlinkFrBack()->deleteTree(), funcp); + } } } - void walkDupFuncs() { - // Do non-slow first as then favors naming functions based on fast name - for (const bool slow : {false, true}) { - for (auto newIt = m_dupFinder.begin(); newIt != m_dupFinder.end(); ++newIt) { - AstCFunc* const newfuncp = VN_AS(newIt->second, CFunc); - UASSERT_OBJ(newfuncp, newIt->second, "Not a CFunc in hash"); - if (newfuncp->user3()) continue; // Already replaced - if (newfuncp->slow() != slow) continue; - auto oldIt = newIt; - ++oldIt; // Skip over current position - for (; oldIt != m_dupFinder.end(); ++oldIt) { - AstCFunc* const oldfuncp = VN_AS(oldIt->second, CFunc); - UASSERT_OBJ(oldfuncp, oldIt->second, "Not a CFunc in hash"); - UASSERT_OBJ(newfuncp != oldfuncp, newfuncp, - "Same function hashed multiple times"); - if (newIt->first != oldIt->first) break; // Iterate over same hashes only - if (oldfuncp->user3()) continue; // Already replaced - if (!newfuncp->sameTree(oldfuncp)) continue; // Different functions + // One pass of combining. Returns true if did replacement. + bool combinePass(std::list& funcps, V3DupFinder& dupFinder) { + const VNUser3InUse user3InUse; - // Replace calls to oldfuncp with calls to newfuncp - UINFO(5, " Replace CFunc " << newIt->first << " " << newfuncp << endl); - UINFO(5, " with " << oldIt->first << " " << oldfuncp << endl); - ++m_cfuncsCombined; - oldfuncp->user3SetOnce(); // Mark replaced - m_call.replaceFunc(oldfuncp, newfuncp); - oldfuncp->unlinkFrBack(); - // Replacement may promote a slow routine to fast path - if (!oldfuncp->slow()) newfuncp->slow(false); - VL_DO_DANGLING(pushDeletep(oldfuncp), oldfuncp); + bool replaced = false; + + // Replace all identical functions with the first function in the list + for (funcit_t it = funcps.begin(), nit; it != funcps.end(); it = nit) { + AstCFunc* const funcp = *it; + nit = it; + ++nit; + + // Remove functions already replaced in the previous iteration + if (funcp->user2()) { + funcps.erase(it); + VL_DO_DANGLING(funcp->unlinkFrBack()->deleteTree(), funcp); + continue; + } + + while (true) { + auto dit = dupFinder.findDuplicate(funcp); + if (dit == dupFinder.end()) break; + + AstCFunc* oldp = VN_AS(dit->second, CFunc); + AstCFunc* newp = funcp; + UASSERT_OBJ(!oldp->user2(), oldp, "Should have been removed from dupFinder"); + + // Swap them, if the duplicate is earlier in the list of functions. This is + // necessary because replacing a call site in a later function might have made that + // function equivalent to an earlier function, but we want the first equivalent + // function in the list to be the canonical one. + if (oldp->user3()) std::swap(oldp, newp); + + // Something is being replaced + UINFO(9, "Replacing " << oldp << endl); + UINFO(9, " with " << newp << endl); + ++m_cfuncsCombined; + replaced = true; + + // Mark as replaced + oldp->user2(true); + + // Redirect the calls + for (AstCCall* const callp : m_callSites(oldp)) { + // For sanity check only + const V3Hash oldHash = m_hasher(callp); + + // Redirect the call + callp->funcp(newp); + + // When redirecting a call to an equivalent function, we do not need to re-hash + // the caller, because the hash of the two calls must be the same, and hence + // the hash of the caller should not change. + UASSERT_OBJ(oldHash == m_hasher.rehash(callp), callp, "Hash changed"); } + + // Erase the replaced duplicate + UASSERT_OBJ(dupFinder.erase(oldp) == 1, oldp, "Replaced node not in dupFinder"); + + // If we just replaced the function we are iterating (because there was an + // equivalent earlier in the list), then move on, as this is on longer a candidate + if (oldp == funcp) break; + } + + // Mark as function earlier in list of functions. + funcp->user3(true); + } + + return replaced; + } + + void process(AstNetlist* netlistp) { + // First, remove empty functions. We need to do this separately, because removing + // calls can change the hashes of the callers. + for (AstNodeModule* modulep = netlistp->modulesp(); modulep; + modulep = VN_AS(modulep->nextp(), NodeModule)) { + removeEmptyFunctions(m_cfuncs(modulep).m_fast); + removeEmptyFunctions(m_cfuncs(modulep).m_slow); + } + + // Combine functions within each module + for (AstNodeModule* modulep = netlistp->modulesp(); modulep; + modulep = VN_AS(modulep->nextp(), NodeModule)) { + // Put fast functions first, so they are preferred over slow functions + auto funcps = std::move(m_cfuncs(modulep).m_fast); + funcps.splice(funcps.end(), m_cfuncs(modulep).m_slow); + + V3DupFinder dupFinder{m_hasher}; + + // First, hash all functions + for (AstCFunc* const funcp : funcps) dupFinder.insert(funcp); + + // Iterate to fixed point + { + const VNUser2InUse user2InUse; + while (combinePass(funcps, dupFinder)) {} } } } // VISITORS virtual void visit(AstNetlist* nodep) override { - m_call.main(nodep); // Track all call sites of each function - iterateChildren(nodep); + // Gather functions and references + iterateChildrenConst(nodep); + // Combine functions + process(nodep); } virtual void visit(AstNodeModule* nodep) override { - UINFO(4, " MOD " << nodep << endl); - m_dupFinder.clear(); - // Compute hash of all CFuncs in the module - iterateChildren(nodep); - if (debug() >= 9) m_dupFinder.dumpFilePrefixed("combine"); - // Walk the hashes removing empty functions - walkEmptyFuncs(); - // Walk the hashes looking for duplicate functions - walkDupFuncs(); + UASSERT_OBJ(!m_modp, nodep, "Should not nest"); + m_modp = nodep; + iterateChildrenConst(nodep); + m_modp = nullptr; } virtual void visit(AstCFunc* nodep) override { + iterateChildrenConst(nodep); if (nodep->dontCombine()) return; - // Hash the entire function - m_dupFinder.insert(nodep); + auto& coll = nodep->slow() ? m_cfuncs(m_modp).m_slow : m_cfuncs(m_modp).m_fast; + coll.emplace_back(nodep); + } + virtual void visit(AstCCall* nodep) override { + iterateChildrenConst(nodep); + AstCFunc* const funcp = nodep->funcp(); + if (funcp->dontCombine()) return; + m_callSites(funcp).emplace_back(nodep); + } + + virtual void visit(AstAddrOfCFunc* nodep) override { + iterateChildrenConst(nodep); + if (nodep->funcp()->dontCombine()) return; + // LCOV_EXCL_START + // We cannot yet handle references via AstAddrOfCFunc, but currently those are + // only used in tracing functions, which are not combined. Blow up in case this changes. + nodep->v3fatalSrc( + "Don't know how to combine functions that are referenced via AstAddrOfCFunc"); + // LCOV_EXCL_END } //-------------------- - // Default: Just iterate - virtual void visit(AstVar*) override {} // Accelerate - virtual void visit(AstNodeStmt* nodep) override {} // Accelerate - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } + virtual void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } -public: // CONSTRUCTORS explicit CombineVisitor(AstNetlist* nodep) { iterate(nodep); } - virtual ~CombineVisitor() override { - V3Stats::addStat("Optimizations, Combined CFuncs", m_cfuncsCombined); - } + ~CombineVisitor() { V3Stats::addStat("Optimizations, Combined CFuncs", m_cfuncsCombined); } + +public: + static void apply(AstNetlist* netlistp) { CombineVisitor{netlistp}; } }; //###################################################################### @@ -223,6 +231,6 @@ public: void V3Combine::combineAll(AstNetlist* nodep) { UINFO(2, __FUNCTION__ << ": " << endl); - { CombineVisitor{nodep}; } // Destruct before checking + CombineVisitor::apply(nodep); V3Global::dumpCheckGlobalTree("combine", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); } diff --git a/src/V3Combine.h b/src/V3Combine.h index 6e510dd05..88ac94e19 100644 --- a/src/V3Combine.h +++ b/src/V3Combine.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Common.cpp b/src/V3Common.cpp index 1bfb366f3..7915126a4 100644 --- a/src/V3Common.cpp +++ b/src/V3Common.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -71,7 +71,7 @@ static void makeToStringMiddle(AstClass* nodep) { comma = ", "; stmt += itemp->origNameProtect(); stmt += ":\" + "; - if (itemp->isWide()) { + if (VN_IS(itemp->dtypep()->skipRefp(), BasicDType) && itemp->isWide()) { stmt += "VL_TO_STRING_W("; stmt += cvtToStr(itemp->widthWords()); stmt += ", "; @@ -109,7 +109,7 @@ void V3Common::commonAll() { // NODE STATE // Entire netlist: // AstClass::user1() -> bool. True if class needs to_string dumper - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // Create ToString methods makeVlToString(classp); makeToString(classp); diff --git a/src/V3Common.h b/src/V3Common.h index 408507e77..54f9f92bc 100644 --- a/src/V3Common.h +++ b/src/V3Common.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Config.cpp b/src/V3Config.cpp index c131ee826..166297344 100644 --- a/src/V3Config.cpp +++ b/src/V3Config.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2010-2021 by Wilson Snyder. This program is free software; you +// Copyright 2010-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -85,9 +85,12 @@ public: // Only public_flat_rw has the sensitity tree class V3ConfigVarAttr final { public: - AstAttrType m_type; // Type of attribute + VAttrType m_type; // Type of attribute AstSenTree* m_sentreep; // Sensitivity tree for public_flat_rw - V3ConfigVarAttr(AstAttrType type, AstSenTree* sentreep) + explicit V3ConfigVarAttr(VAttrType type) + : m_type{type} + , m_sentreep{nullptr} {} + V3ConfigVarAttr(VAttrType type, AstSenTree* sentreep) : m_type{type} , m_sentreep{sentreep} {} }; @@ -105,7 +108,7 @@ public: for (const_iterator it = begin(); it != end(); ++it) { AstNode* const newp = new AstAttrOf(varp->fileline(), it->m_type); varp->addAttrsp(newp); - if (it->m_type == AstAttrType::VAR_PUBLIC_FLAT_RW && it->m_sentreep) { + if (it->m_type == VAttrType::VAR_PUBLIC_FLAT_RW && it->m_sentreep) { newp->addNext(new AstAlwaysPublic(varp->fileline(), it->m_sentreep, nullptr)); } } @@ -141,9 +144,9 @@ public: void apply(AstNodeFTask* ftaskp) const { if (m_noinline) - ftaskp->addStmtsp(new AstPragma(ftaskp->fileline(), AstPragmaType::NO_INLINE_TASK)); + ftaskp->addStmtsp(new AstPragma(ftaskp->fileline(), VPragmaType::NO_INLINE_TASK)); if (m_public) - ftaskp->addStmtsp(new AstPragma(ftaskp->fileline(), AstPragmaType::PUBLIC_TASK)); + ftaskp->addStmtsp(new AstPragma(ftaskp->fileline(), VPragmaType::PUBLIC_TASK)); // Only functions can have isolate (return value) if (VN_IS(ftaskp, Func)) ftaskp->attrIsolateAssign(m_isolate); } @@ -158,7 +161,7 @@ class V3ConfigModule final { V3ConfigFTaskResolver m_tasks; // Functions/tasks in module V3ConfigVarResolver m_vars; // Variables in module std::unordered_set m_coverageOffBlocks; // List of block names for coverage_off - std::set m_modPragmas; // List of Pragmas for modules + std::set m_modPragmas; // List of Pragmas for modules bool m_inline = false; // Whether to force the inline bool m_inlineValue = false; // The inline value (on/off) @@ -186,12 +189,12 @@ public: m_inline = true; m_inlineValue = set; } - void addModulePragma(AstPragmaType pragma) { m_modPragmas.insert(pragma); } + void addModulePragma(VPragmaType pragma) { m_modPragmas.insert(pragma); } void apply(AstNodeModule* modp) { if (m_inline) { - const AstPragmaType type - = m_inlineValue ? AstPragmaType::INLINE_MODULE : AstPragmaType::NO_INLINE_MODULE; + const VPragmaType type + = m_inlineValue ? VPragmaType::INLINE_MODULE : VPragmaType::NO_INLINE_MODULE; AstNode* const nodep = new AstPragma(modp->fileline(), type); modp->addStmtp(nodep); } @@ -202,7 +205,7 @@ public: } void applyBlock(AstNodeBlock* nodep) { - const AstPragmaType pragma = AstPragmaType::COVERAGE_BLOCK_OFF; + const VPragmaType pragma = VPragmaType::COVERAGE_BLOCK_OFF; if (!nodep->unnamed()) { for (const string& i : m_coverageOffBlocks) { if (VString::wildmatch(nodep->name(), i)) { @@ -247,7 +250,7 @@ std::ostream& operator<<(std::ostream& os, const V3ConfigIgnoresLine& rhs) { // Some attributes are attached to entities of the occur on a fileline // and multiple attributes can be attached to a line -using V3ConfigLineAttribute = std::bitset; +using V3ConfigLineAttribute = std::bitset; // File entity class V3ConfigFile final { @@ -266,7 +269,7 @@ class V3ConfigFile final { } m_lastIgnore; // Last ignore line run // Match a given line and attribute to the map, line 0 is any - bool lineMatch(int lineno, AstPragmaType type) { + bool lineMatch(int lineno, VPragmaType type) { if (m_lineAttrs.find(0) != m_lineAttrs.end() && m_lineAttrs[0][type]) return true; if (m_lineAttrs.find(lineno) == m_lineAttrs.end()) return false; return m_lineAttrs[lineno][type]; @@ -287,7 +290,7 @@ public: m_waivers.reserve(m_waivers.size() + file.m_waivers.size()); m_waivers.insert(m_waivers.end(), file.m_waivers.begin(), file.m_waivers.end()); } - void addLineAttribute(int lineno, AstPragmaType attr) { m_lineAttrs[lineno].set(attr); } + void addLineAttribute(int lineno, VPragmaType attr) { m_lineAttrs[lineno].set(attr); } void addIgnore(V3ErrorCode code, int lineno, bool on) { m_ignLines.insert(V3ConfigIgnoresLine(code, lineno, on)); m_lastIgnore.it = m_ignLines.begin(); @@ -298,7 +301,7 @@ public: void applyBlock(AstNodeBlock* nodep) { // Apply to block at this line - const AstPragmaType pragma = AstPragmaType::COVERAGE_BLOCK_OFF; + const VPragmaType pragma = VPragmaType::COVERAGE_BLOCK_OFF; if (lineMatch(nodep->fileline()->lineno(), pragma)) { nodep->addStmtsp(new AstPragma(nodep->fileline(), pragma)); } @@ -306,8 +309,8 @@ public: void applyCase(AstCase* nodep) { // Apply to this case at this line const int lineno = nodep->fileline()->lineno(); - if (lineMatch(lineno, AstPragmaType::FULL_CASE)) nodep->fullPragma(true); - if (lineMatch(lineno, AstPragmaType::PARALLEL_CASE)) nodep->parallelPragma(true); + if (lineMatch(lineno, VPragmaType::FULL_CASE)) nodep->fullPragma(true); + if (lineMatch(lineno, VPragmaType::PARALLEL_CASE)) nodep->parallelPragma(true); } inline void applyIgnores(FileLine* filelinep) { // HOT routine, called each parsed token line of this filename @@ -383,17 +386,17 @@ V3ConfigResolver V3ConfigResolver::s_singleton; void V3Config::addCaseFull(const string& filename, int lineno) { V3ConfigFile& file = V3ConfigResolver::s().files().at(filename); - file.addLineAttribute(lineno, AstPragmaType::FULL_CASE); + file.addLineAttribute(lineno, VPragmaType::FULL_CASE); } void V3Config::addCaseParallel(const string& filename, int lineno) { V3ConfigFile& file = V3ConfigResolver::s().files().at(filename); - file.addLineAttribute(lineno, AstPragmaType::PARALLEL_CASE); + file.addLineAttribute(lineno, VPragmaType::PARALLEL_CASE); } void V3Config::addCoverageBlockOff(const string& filename, int lineno) { V3ConfigFile& file = V3ConfigResolver::s().files().at(filename); - file.addLineAttribute(lineno, AstPragmaType::COVERAGE_BLOCK_OFF); + file.addLineAttribute(lineno, VPragmaType::COVERAGE_BLOCK_OFF); } void V3Config::addCoverageBlockOff(const string& module, const string& blockname) { @@ -422,7 +425,7 @@ void V3Config::addInline(FileLine* fl, const string& module, const string& ftask } } -void V3Config::addModulePragma(const string& module, AstPragmaType pragma) { +void V3Config::addModulePragma(const string& module, VPragmaType pragma) { V3ConfigResolver::s().modules().at(module).addModulePragma(pragma); } @@ -432,37 +435,48 @@ void V3Config::addProfileData(FileLine* fl, const string& model, const string& k } void V3Config::addVarAttr(FileLine* fl, const string& module, const string& ftask, - const string& var, AstAttrType attr, AstSenTree* sensep) { + const string& var, VAttrType attr, AstSenTree* sensep) { // Semantics: sensep only if public_flat_rw - if ((attr != AstAttrType::VAR_PUBLIC_FLAT_RW) && sensep) { + if ((attr != VAttrType::VAR_PUBLIC_FLAT_RW) && sensep) { sensep->v3error("sensitivity not expected for attribute"); return; } // Semantics: Most of the attributes operate on signals if (var.empty()) { - if (attr == AstAttrType::VAR_ISOLATE_ASSIGNMENTS) { + if (attr == VAttrType::VAR_ISOLATE_ASSIGNMENTS) { if (ftask.empty()) { fl->v3error("isolate_assignments only applies to signals or functions/tasks"); } else { V3ConfigResolver::s().modules().at(module).ftasks().at(ftask).setIsolate(true); } - } else if (attr == AstAttrType::VAR_PUBLIC) { + } else if (attr == VAttrType::VAR_PUBLIC) { if (ftask.empty()) { // public module, this is the only exception from var here V3ConfigResolver::s().modules().at(module).addModulePragma( - AstPragmaType::PUBLIC_MODULE); + VPragmaType::PUBLIC_MODULE); } else { V3ConfigResolver::s().modules().at(module).ftasks().at(ftask).setPublic(true); } } else { - fl->v3error("missing -signal"); + fl->v3error("missing -var"); } } else { - V3ConfigModule& mod = V3ConfigResolver::s().modules().at(module); - if (ftask.empty()) { - mod.vars().at(var).push_back(V3ConfigVarAttr(attr, sensep)); + if (attr == VAttrType::VAR_FORCEABLE) { + if (module.empty()) { + fl->v3error("missing -module"); + } else if (!ftask.empty()) { + fl->v3error("Signals inside functions/tasks cannot be marked forceable"); + } else { + V3ConfigResolver::s().modules().at(module).vars().at(var).push_back( + V3ConfigVarAttr(attr)); + } } else { - mod.ftasks().at(ftask).vars().at(var).push_back(V3ConfigVarAttr(attr, sensep)); + V3ConfigModule& mod = V3ConfigResolver::s().modules().at(module); + if (ftask.empty()) { + mod.vars().at(var).push_back(V3ConfigVarAttr(attr, sensep)); + } else { + mod.ftasks().at(ftask).vars().at(var).push_back(V3ConfigVarAttr(attr, sensep)); + } } } } diff --git a/src/V3Config.h b/src/V3Config.h index 1559e64a0..c966074f1 100644 --- a/src/V3Config.h +++ b/src/V3Config.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2010-2021 by Wilson Snyder. This program is free software; you +// Copyright 2010-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,12 +34,12 @@ public: static void addCoverageBlockOff(const string& module, const string& blockname); static void addIgnore(V3ErrorCode code, bool on, const string& filename, int min, int max); static void addInline(FileLine* fl, const string& module, const string& ftask, bool on); - static void addModulePragma(const string& module, AstPragmaType pragma); + static void addModulePragma(const string& module, VPragmaType pragma); static void addProfileData(FileLine* fl, const string& model, const string& key, vluint64_t cost); static void addWaiver(V3ErrorCode code, const string& filename, const string& message); static void addVarAttr(FileLine* fl, const string& module, const string& ftask, - const string& signal, AstAttrType type, AstSenTree* nodep); + const string& signal, VAttrType type, AstSenTree* nodep); static void applyCase(AstCase* nodep); static void applyCoverageBlock(AstNodeModule* modulep, AstBegin* nodep); diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 5011b7711..6a782accd 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -38,46 +38,6 @@ //###################################################################### // Utilities -class ConstVarMarkVisitor final : public AstNVisitor { - // NODE STATE - // AstVar::user4p -> bool, Var marked, 0=not set yet -private: - // VISITORS - virtual void visit(AstVarRef* nodep) override { - if (nodep->varp()) nodep->varp()->user4(1); - } - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - explicit ConstVarMarkVisitor(AstNode* nodep) { - AstNode::user4ClearTree(); // Check marked InUse before we're called - iterate(nodep); - } - virtual ~ConstVarMarkVisitor() override = default; -}; - -class ConstVarFindVisitor final : public AstNVisitor { - // NODE STATE - // AstVar::user4p -> bool, input from ConstVarMarkVisitor - // MEMBERS - bool m_found = false; - -private: - // VISITORS - virtual void visit(AstVarRef* nodep) override { - if (nodep->varp() && nodep->varp()->user4()) m_found = true; - } - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - explicit ConstVarFindVisitor(AstNode* nodep) { iterateAndNextNull(nodep); } - virtual ~ConstVarFindVisitor() override = default; - // METHODS - bool found() const { return m_found; } -}; - static bool isConst(const AstNode* nodep, uint64_t v) { const AstConst* const constp = VN_CAST(nodep, Const); return constp && constp->toUQuad() == v; @@ -106,11 +66,11 @@ static int countTrailingZeroes(uint64_t val) { // This visitor can be used in the post-expanded Ast from V3Expand, where the Ast satisfies: // - Constants are 64 bit at most (because words are accessed via AstWordSel) // - Variables are scoped. -class ConstBitOpTreeVisitor final : public AstNVisitor { +class ConstBitOpTreeVisitor final : public VNVisitor { // NODE STATE // AstVarRef::user4u -> Base index of m_varInfos that points VarInfo // AstVarScope::user4u -> Same as AstVarRef::user4 - const AstUser4InUse m_inuser4; + const VNUser4InUse m_inuser4; // TYPES @@ -806,12 +766,12 @@ public: //###################################################################### // Const state, as a visitor of each AstNode -class ConstVisitor final : public AstNVisitor { +class ConstVisitor final : public VNVisitor { private: // NODE STATE // ** only when m_warn/m_doExpensive is set. If state is needed other times, // ** must track down everywhere V3Const is called and make sure no overlaps. - // AstVar::user4p -> Used by ConstVarMarkVisitor/ConstVarFindVisitor + // AstVar::user4p -> Used by variable marking/finding // AstJumpLabel::user4 -> bool. Set when AstJumpGo uses this label // AstEnum::user4 -> bool. Recursing. @@ -951,8 +911,9 @@ private: } else if (VN_IS(nodep->rhsp(), And)) { andp = VN_AS(nodep->rhsp(), And); ap = nodep->lhsp(); - } else + } else { return false; + } const AstNodeUniop* notp; AstNode* cp; if (VN_IS(andp->lhsp(), Not)) { @@ -1809,7 +1770,7 @@ private: } void replaceShiftOp(AstNodeBiop* nodep) { UINFO(5, "SHIFT(AND(a,b),CONST)->AND(SHIFT(a,CONST),SHIFT(b,CONST)) " << nodep << endl); - AstNRelinker handle; + VNRelinker handle; nodep->unlinkFrBack(&handle); AstNodeBiop* const lhsp = VN_AS(nodep->lhsp(), NodeBiop); lhsp->unlinkFrBack(); @@ -1978,10 +1939,13 @@ private: if (m_warn && !VN_IS(nodep, AssignDly)) { // Is same var on LHS and RHS? // Note only do this (need user4) when m_warn, which is // done as unique visitor - const AstUser4InUse m_inuser4; - const ConstVarMarkVisitor mark{nodep->lhsp()}; - const ConstVarFindVisitor find{nodep->rhsp()}; - if (find.found()) need_temp = true; + const VNUser4InUse m_inuser4; + nodep->lhsp()->foreach([](const AstVarRef* nodep) { + if (nodep->varp()) nodep->varp()->user4(1); + }); + nodep->rhsp()->foreach([&need_temp](const AstVarRef* nodep) { + if (nodep->varp() && nodep->varp()->user4()) need_temp = true; + }); } if (need_temp) { // The first time we constify, there may be the same variable on the LHS @@ -2029,10 +1993,10 @@ private: // We could create just one temp variable, but we'll get better optimization // if we make one per term. AstVar* const temp1p - = new AstVar(sel1p->fileline(), AstVarType::BLOCKTEMP, + = new AstVar(sel1p->fileline(), VVarType::BLOCKTEMP, m_concswapNames.get(sel1p), VFlagLogicPacked(), msb1 - lsb1 + 1); AstVar* const temp2p - = new AstVar(sel2p->fileline(), AstVarType::BLOCKTEMP, + = new AstVar(sel2p->fileline(), VVarType::BLOCKTEMP, m_concswapNames.get(sel2p), VFlagLogicPacked(), msb2 - lsb2 + 1); m_modp->addStmtp(temp1p); m_modp->addStmtp(temp2p); @@ -2698,7 +2662,7 @@ private: // SENGATE(SENITEM(x)) -> SENITEM(x), then let it collapse with the // other SENITEM(x). { - const AstUser4InUse m_inuse4; + const VNUser4InUse m_inuse4; // Mark x in SENITEM(x) for (AstSenItem* senp = nodep->sensesp(); senp; senp = VN_AS(senp->nextp(), SenItem)) { @@ -2804,6 +2768,18 @@ private: varrefp->varp()->valuep(initvaluep); } } + virtual void visit(AstRelease* nodep) override { + if (AstConcat* const concatp = VN_CAST(nodep->lhsp(), Concat)) { + FileLine* const flp = nodep->fileline(); + AstRelease* const newLp = new AstRelease{flp, concatp->lhsp()->unlinkFrBack()}; + AstRelease* const newRp = new AstRelease{flp, concatp->rhsp()->unlinkFrBack()}; + nodep->replaceWith(newLp); + newLp->addNextHere(newRp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + visit(newLp); + visit(newRp); + } + } virtual void visit(AstNodeIf* nodep) override { iterateChildren(nodep); @@ -2900,10 +2876,10 @@ private: AstDisplay* const prevp = VN_CAST(nodep->backp(), Display); if (!prevp) return false; if (!((prevp->displayType() == nodep->displayType()) - || (prevp->displayType() == AstDisplayType::DT_WRITE - && nodep->displayType() == AstDisplayType::DT_DISPLAY) - || (prevp->displayType() == AstDisplayType::DT_DISPLAY - && nodep->displayType() == AstDisplayType::DT_WRITE))) + || (prevp->displayType() == VDisplayType::DT_WRITE + && nodep->displayType() == VDisplayType::DT_DISPLAY) + || (prevp->displayType() == VDisplayType::DT_DISPLAY + && nodep->displayType() == VDisplayType::DT_WRITE))) return false; if ((prevp->filep() && !nodep->filep()) || (!prevp->filep() && nodep->filep()) || !prevp->filep()->sameTree(nodep->filep())) @@ -2928,8 +2904,8 @@ private: // UINFO(9, "DISPLAY(SF({a})) DISPLAY(SF({b})) -> DISPLAY(SF({a}+{b}))" << endl); // Convert DT_DISPLAY to DT_WRITE as may allow later optimizations - if (prevp->displayType() == AstDisplayType::DT_DISPLAY) { - prevp->displayType(AstDisplayType::DT_WRITE); + if (prevp->displayType() == VDisplayType::DT_DISPLAY) { + prevp->displayType(VDisplayType::DT_WRITE); pformatp->text(pformatp->text() + "\n"); } // We can't replace prev() as the edit tracking iterators will get confused. @@ -3204,12 +3180,12 @@ private: // Non-zero on one side or the other TREEOP ("AstAnd {$lhsp.isAllOnes, $rhsp}", "replaceWRhs(nodep)"); TREEOP ("AstLogAnd{$lhsp.isNeqZero, $rhsp}", "replaceWRhs(nodep)"); - TREEOP ("AstOr {$lhsp.isAllOnes, $rhsp, isTPure($rhsp)}", "replaceWLhs(nodep)"); //->allOnes + TREEOP ("AstOr {$lhsp.isAllOnes, $rhsp, isTPure($rhsp)}", "replaceWLhs(nodep)"); // ->allOnes TREEOP ("AstLogOr {$lhsp.isNeqZero, $rhsp}", "replaceNum(nodep,1)"); TREEOP ("AstAnd {$lhsp, $rhsp.isAllOnes}", "replaceWLhs(nodep)"); TREEOP ("AstLogAnd{$lhsp, $rhsp.isNeqZero}", "replaceWLhs(nodep)"); - TREEOP ("AstOr {$lhsp, $rhsp.isAllOnes, isTPure($lhsp)}", "replaceWRhs(nodep)"); //->allOnes - TREEOP ("AstLogOr {$lhsp, $rhsp.isNeqZero, isTPure($lhsp)}", "replaceNum(nodep,1)"); + TREEOP ("AstOr {$lhsp, $rhsp.isAllOnes, isTPure($lhsp)}", "replaceWRhs(nodep)"); // ->allOnes + TREEOP ("AstLogOr {$lhsp, $rhsp.isNeqZero, isTPure($lhsp), nodep->isPure()}", "replaceNum(nodep,1)"); TREEOP ("AstXor {$lhsp.isAllOnes, $rhsp}", "AstNot{$rhsp}"); TREEOP ("AstMul {$lhsp.isOne, $rhsp}", "replaceWRhs(nodep)"); TREEOP ("AstMulS {$lhsp.isOne, $rhsp}", "replaceWRhs(nodep)"); @@ -3317,7 +3293,6 @@ private: // AstLogAnd/AstLogOr already converted to AstAnd/AstOr for these rules // AstAdd->ShiftL(#,1) but uncommon TREEOP ("AstAnd {operandsSame($lhsp,,$rhsp)}", "replaceWLhs(nodep)"); - TREEOP ("AstChangeXor{operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)"); TREEOP ("AstDiv {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)"); TREEOP ("AstDivS {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)"); TREEOP ("AstOr {operandsSame($lhsp,,$rhsp)}", "replaceWLhs(nodep)"); @@ -3383,7 +3358,7 @@ private: TREEOPV("AstOneHot0{$lhsp.width1}", "replaceNum(nodep,1)"); // Binary AND/OR is faster than logical and/or (usually) TREEOPV("AstLogAnd{$lhsp.width1, $rhsp.width1, isTPure($lhsp), isTPure($rhsp)}", "AstAnd{$lhsp,$rhsp}"); - TREEOPV("AstLogOr {$lhsp.width1, $rhsp.width1, isTPure($lhsp), isTPure($rhsp)}", "AstOr{$lhsp,$rhsp}"); + TREEOPV("AstLogOr {$lhsp.width1, $rhsp.width1, nodep->isPure(), isTPure($lhsp), isTPure($rhsp)}", "AstOr{$lhsp,$rhsp}"); TREEOPV("AstLogNot{$lhsp.width1, isTPure($lhsp)}", "AstNot{$lhsp}"); // CONCAT(CONCAT({a},{b}),{c}) -> CONCAT({a},CONCAT({b},{c})) // CONCAT({const},CONCAT({const},{c})) -> CONCAT((constifiedCONC{const|const},{c})) diff --git a/src/V3Const.h b/src/V3Const.h index 11e50cc03..59f5a5f76 100644 --- a/src/V3Const.h +++ b/src/V3Const.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,8 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; +class AstNode; //============================================================================ diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index 8e0415bba..cac65eb31 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -37,7 +37,7 @@ //###################################################################### // Coverage state, as a visitor of each AstNode -class CoverageVisitor final : public AstNVisitor { +class CoverageVisitor final : public VNVisitor { private: // TYPES using LinenoSet = std::set; @@ -73,7 +73,7 @@ private: // NODE STATE // Entire netlist: // AstIf::user1() -> bool. True indicates ifelse processed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE CheckState m_state; // State save-restored on each new coverage scope/block @@ -123,8 +123,8 @@ private: AstCoverInc* const incp = new AstCoverInc(fl, declp); if (!trace_var_name.empty() && v3Global.opt.traceCoverage()) { - AstVar* const varp = new AstVar(incp->fileline(), AstVarType::MODULETEMP, - trace_var_name, incp->findUInt32DType()); + AstVar* const varp = new AstVar(incp->fileline(), VVarType::MODULETEMP, trace_var_name, + incp->findUInt32DType()); varp->trace(true); varp->fileline()->modifyWarnOff(V3ErrorCode::UNUSED, true); m_modp->addStmtp(varp); @@ -280,7 +280,7 @@ private: // Add signal to hold the old value const string newvarname = string("__Vtogcov__") + nodep->shortName(); AstVar* const chgVarp - = new AstVar(nodep->fileline(), AstVarType::MODULETEMP, newvarname, nodep); + = new AstVar(nodep->fileline(), VVarType::MODULETEMP, newvarname, nodep); chgVarp->fileline()->modifyWarnOff(V3ErrorCode::UNUSED, true); m_modp->addStmtp(chgVarp); @@ -498,7 +498,7 @@ private: m_state.m_on = false; } virtual void visit(AstPragma* nodep) override { - if (nodep->pragType() == AstPragmaType::COVERAGE_BLOCK_OFF) { + if (nodep->pragType() == VPragmaType::COVERAGE_BLOCK_OFF) { // Skip all NEXT nodes under this block, and skip this if/case branch UINFO(4, " OFF: h" << m_state.m_handle << " " << nodep << endl); m_state.m_on = false; diff --git a/src/V3Coverage.h b/src/V3Coverage.h index 1b2cc7c40..efacd3f33 100644 --- a/src/V3Coverage.h +++ b/src/V3Coverage.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3CoverageJoin.cpp b/src/V3CoverageJoin.cpp index f372571ab..864e3b6fe 100644 --- a/src/V3CoverageJoin.cpp +++ b/src/V3CoverageJoin.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,10 +30,10 @@ //###################################################################### // CoverageJoin state, as a visitor of each AstNode -class CoverageJoinVisitor final : public AstNVisitor { +class CoverageJoinVisitor final : public VNVisitor { private: // NODE STATE - // AstUser4InUse In V3Hasher via V3DupFinder + // VNUser4InUse In V3Hasher via V3DupFinder // STATE std::vector m_toggleps; // List of of all AstCoverToggle's diff --git a/src/V3CoverageJoin.h b/src/V3CoverageJoin.h index 5b52eb3ff..fb786c2c8 100644 --- a/src/V3CoverageJoin.h +++ b/src/V3CoverageJoin.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp index 1a2fc6be7..6347fc098 100644 --- a/src/V3Dead.cpp +++ b/src/V3Dead.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -43,32 +43,10 @@ #include #include -//###################################################################### - -class DeadModVisitor final : public AstNVisitor { - // In a module that is dead, cleanup the in-use counts of the modules -private: - // NODE STATE - // ** Shared with DeadVisitor ** - // VISITORS - virtual void visit(AstCell* nodep) override { - iterateChildren(nodep); - nodep->modp()->user1Inc(-1); - } - //----- - virtual void visit(AstNodeMath*) override {} // Accelerate - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - explicit DeadModVisitor(AstNodeModule* nodep) { iterate(nodep); } - virtual ~DeadModVisitor() override = default; -}; - //###################################################################### // Dead state, as a visitor of each AstNode -class DeadVisitor final : public AstNVisitor { +class DeadVisitor final : public VNVisitor { private: // NODE STATE // Entire Netlist: @@ -76,13 +54,14 @@ private: // AstVar::user1() -> int. Count of number of references // AstVarScope::user1() -> int. Count of number of references // AstNodeDType::user1() -> int. Count of number of references - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // TYPES using AssignMap = std::multimap; // STATE AstNodeModule* m_modp = nullptr; // Current module + AstSelLoopVars* m_selloopvarsp = nullptr; // Current loop vars // List of all encountered to avoid another loop through tree std::vector m_varsp; std::vector m_dtypesp; @@ -113,6 +92,7 @@ private: if (!nodep->generic() // Don't remove generic types && m_elimDTypes // dtypes stick around until post-widthing && !VN_IS(nodep, MemberDType) // Keep member names iff upper type exists + && !nodep->undead() // VoidDType or something Netlist points to ) { m_dtypesp.push_back(nodep); } @@ -249,6 +229,13 @@ private: } checkAll(nodep); } + virtual void visit(AstSelLoopVars* nodep) override { + // Var under a SelLoopVars means we haven't called V3Width to remove them yet + VL_RESTORER(m_selloopvarsp); + m_selloopvarsp = nodep; + iterateChildren(nodep); + checkAll(nodep); + } virtual void visit(AstTypedef* nodep) override { iterateChildren(nodep); if (m_elimCells && !nodep->attrPublic()) { @@ -270,6 +257,7 @@ private: iterateChildren(nodep); checkAll(nodep); if (nodep->isSigPublic() && m_modp && VN_IS(m_modp, Package)) m_modp->user1Inc(); + if (m_selloopvarsp) nodep->user1Inc(); if (mightElimVar(nodep)) m_varsp.push_back(nodep); } virtual void visit(AstNodeAssign* nodep) override { @@ -318,7 +306,9 @@ private: // And its children may now be killable too; correct counts // Recurse, as cells may not be directly under the module but in a generate if (!modp->dead()) { // If was dead didn't increment user1's - DeadModVisitor{modp}; + modp->foreach([](const AstCell* cellp) { // + cellp->modp()->user1Inc(-1); + }); } VL_DO_DANGLING(modp->unlinkFrBack()->deleteTree(), modp); retry = true; diff --git a/src/V3Dead.h b/src/V3Dead.h index 409b7ac52..01486c6fc 100644 --- a/src/V3Dead.h +++ b/src/V3Dead.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index d1e2b80ca..f16223128 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -63,7 +63,7 @@ //###################################################################### // Delayed state, as a visitor of each AstNode -class DelayedVisitor final : public AstNVisitor { +class DelayedVisitor final : public VNVisitor { private: // NODE STATE // Cleared each module: @@ -81,11 +81,11 @@ private: // Cleared each scope/active: // AstAssignDly::user3() -> AstVarScope*. __Vdlyvset__ created for this assign // AstAlwaysPost::user3() -> AstVarScope*. __Vdlyvset__ last referenced in IF - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; - const AstUser4InUse m_inuser4; - const AstUser5InUse m_inuser5; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; + const VNUser4InUse m_inuser4; + const VNUser5InUse m_inuser5; // STATE AstActive* m_activep = nullptr; // Current activate @@ -103,6 +103,8 @@ private: VL_DEBUG_FUNC; // Declare debug() void markVarUsage(AstNodeVarRef* nodep, bool blocking) { + // Ignore if warning is disabled on this reference (used by V3Force). + if (nodep->fileline()->warnIsOff(V3ErrorCode::BLKANDNBLK)) return; if (blocking) nodep->user5(true); AstVarScope* const vscp = nodep->varScopep(); // UINFO(4, " MVU " << blocking << " " << nodep << endl); @@ -139,13 +141,13 @@ private: varp = it->second; } else { if (newdtypep) { - varp = new AstVar(oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, newdtypep); + varp = new AstVar(oldvarscp->fileline(), VVarType::BLOCKTEMP, name, newdtypep); } else if (width == 0) { - varp = new AstVar(oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, + varp = new AstVar(oldvarscp->fileline(), VVarType::BLOCKTEMP, name, oldvarscp->varp()); varp->dtypeFrom(oldvarscp); } else { // Used for vset and dimensions, so can zero init - varp = new AstVar(oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, + varp = new AstVar(oldvarscp->fileline(), VVarType::BLOCKTEMP, name, VFlagBitPacked(), width); } addmodp->addStmtp(varp); diff --git a/src/V3Delayed.h b/src/V3Delayed.h index 745dbb8c6..96d6f9e2e 100644 --- a/src/V3Delayed.h +++ b/src/V3Delayed.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp index 912d900fa..d83d69d66 100644 --- a/src/V3Depth.cpp +++ b/src/V3Depth.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -35,12 +35,13 @@ //###################################################################### -class DepthVisitor final : public AstNVisitor { +class DepthVisitor final : public VNVisitor { private: // NODE STATE // STATE AstCFunc* m_cfuncp = nullptr; // Current block + AstMTaskBody* m_mtaskbodyp = nullptr; // Current mtaskbody AstNode* m_stmtp = nullptr; // Current statement int m_depth = 0; // How deep in an expression int m_maxdepth = 0; // Maximum depth in an expression @@ -52,17 +53,22 @@ private: void createDeepTemp(AstNode* nodep) { UINFO(6, " Deep " << nodep << endl); // if (debug() >= 9) nodep->dumpTree(cout, "deep:"); - AstVar* const varp = new AstVar{nodep->fileline(), AstVarType::STMTTEMP, + AstVar* const varp = new AstVar{nodep->fileline(), VVarType::STMTTEMP, m_tempNames.get(nodep), nodep->dtypep()}; - UASSERT_OBJ(m_cfuncp, nodep, "Deep expression not under a function"); - m_cfuncp->addInitsp(varp); + if (m_cfuncp) { + m_cfuncp->addInitsp(varp); + } else if (m_mtaskbodyp) { + m_mtaskbodyp->addStmtsFirstp(varp); + } else { + nodep->v3fatalSrc("Deep expression not under a function"); + } // Replace node tree with reference to var AstVarRef* const newp = new AstVarRef{nodep->fileline(), varp, VAccess::READ}; nodep->replaceWith(newp); // Put assignment before the referencing statement AstAssign* const assp = new AstAssign{ nodep->fileline(), new AstVarRef{nodep->fileline(), varp, VAccess::WRITE}, nodep}; - AstNRelinker linker2; + VNRelinker linker2; m_stmtp->unlinkFrBack(&linker2); assp->addNext(m_stmtp); linker2.relink(assp); @@ -71,14 +77,28 @@ private: // VISITORS virtual void visit(AstCFunc* nodep) override { VL_RESTORER(m_cfuncp); + VL_RESTORER(m_mtaskbodyp); { m_cfuncp = nodep; + m_mtaskbodyp = nullptr; m_depth = 0; m_maxdepth = 0; m_tempNames.reset(); iterateChildren(nodep); } } + virtual void visit(AstMTaskBody* nodep) override { + VL_RESTORER(m_cfuncp); + VL_RESTORER(m_mtaskbodyp); + { + m_cfuncp = nullptr; + m_mtaskbodyp = nodep; + m_depth = 0; + m_maxdepth = 0; + // We don't reset the names, as must share across tasks + iterateChildren(nodep); + } + } void visitStmt(AstNodeStmt* nodep) { VL_RESTORER(m_stmtp); { diff --git a/src/V3Depth.h b/src/V3Depth.h index 09f43c33c..372636d54 100644 --- a/src/V3Depth.h +++ b/src/V3Depth.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3DepthBlock.cpp b/src/V3DepthBlock.cpp index e0461f9ef..13ebc929c 100644 --- a/src/V3DepthBlock.cpp +++ b/src/V3DepthBlock.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,7 +32,7 @@ //###################################################################### -class DepthBlockVisitor final : public AstNVisitor { +class DepthBlockVisitor final : public VNVisitor { private: // NODE STATE @@ -46,7 +46,7 @@ private: VL_DEBUG_FUNC; // Declare debug() AstCFunc* createDeepFunc(AstNode* nodep) { - AstNRelinker relinkHandle; + VNRelinker relinkHandle; nodep->unlinkFrBack(&relinkHandle); // Create sub function AstScope* const scopep = m_cfuncp->scopep(); diff --git a/src/V3DepthBlock.h b/src/V3DepthBlock.h index bbc04d7a6..099c43f7b 100644 --- a/src/V3DepthBlock.h +++ b/src/V3DepthBlock.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp index 567875def..29bdd3abc 100644 --- a/src/V3Descope.cpp +++ b/src/V3Descope.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,12 +34,12 @@ //###################################################################### -class DescopeVisitor final : public AstNVisitor { +class DescopeVisitor final : public VNVisitor { private: // NODE STATE // Cleared entire netlist // AstCFunc::user() // bool. Indicates processing completed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // TYPES using FuncMmap = std::multimap; @@ -73,8 +73,6 @@ private: // module. string descopedSelfPointer(const AstScope* scopep) { UASSERT(scopep, "Var/Func not scoped"); - UASSERT(!VN_IS(scopep->modp(), Class), "References to classes handled elsewhere"); - // Static functions can't use relative references via 'this->' const bool relativeRefOk = !m_funcp->isStatic(); @@ -82,7 +80,11 @@ private: UINFO(8, " ref to " << scopep << endl); UINFO(8, " aboveScope " << scopep->aboveScopep() << endl); - if (relativeRefOk && scopep == m_scopep) { + if (VN_IS(scopep->modp(), Class)) { + // Direct reference to class members are from within the class itself, references from + // outside the class must go via AstMemberSel + return "this"; + } else if (relativeRefOk && scopep == m_scopep) { return "this"; } else if (relativeRefOk && !m_modSingleton && scopep->aboveScopep() == m_scopep && VN_IS(scopep->modp(), Module)) { @@ -168,7 +170,7 @@ private: // Not really any way the user could do this, and we'd need // to come up with some return value // newfuncp->addStmtsp(new AstDisplay(newfuncp->fileline(), - // AstDisplayType::DT_WARNING, + // VDisplayType::DT_WARNING, // string("%%Error: ")+name+"() called with bad // scope", nullptr)); // newfuncp->addStmtsp(new AstStop(newfuncp->fileline())); @@ -224,15 +226,11 @@ private: } else if (scopep->modp() == v3Global.rootp()->constPoolp()->modp()) { // Reference to constant pool value need no self pointer nodep->selfPointer(""); - } else if (VN_IS(scopep->modp(), Class)) { - // Direct reference to class members are from within the class itself, references from - // outside the class must go via AstMemberSel - nodep->selfPointer("this"); } else { nodep->selfPointer(descopedSelfPointer(scopep)); } nodep->varScopep(nullptr); - UINFO(9, " refout " << nodep << endl); + UINFO(9, " refout " << nodep << " selfPtr=" << nodep->selfPointer() << endl); } virtual void visit(AstCCall* nodep) override { // UINFO(9, " " << nodep << endl); @@ -240,13 +238,7 @@ private: // Convert the hierch name UASSERT_OBJ(m_scopep, nodep, "Node not under scope"); const AstScope* const scopep = nodep->funcp()->scopep(); - if (VN_IS(scopep->modp(), Class)) { - // Direct call to class methods are from within the class itself, method calls from - // outside the class must go via AstCMethodCall - nodep->selfPointer("this"); - } else { - nodep->selfPointer(descopedSelfPointer(scopep)); - } + nodep->selfPointer(descopedSelfPointer(scopep)); // Can't do this, as we may have more calls later // nodep->funcp()->scopep(nullptr); } diff --git a/src/V3Descope.h b/src/V3Descope.h index 9f3fc6ce6..c7175ff73 100644 --- a/src/V3Descope.h +++ b/src/V3Descope.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3DupFinder.cpp b/src/V3DupFinder.cpp index 9b8187f1a..809c06670 100644 --- a/src/V3DupFinder.cpp +++ b/src/V3DupFinder.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,6 +30,17 @@ //###################################################################### // V3DupFinder class functions +V3DupFinder::size_type V3DupFinder::erase(AstNode* nodep) { + const auto& er = equal_range(m_hasher(nodep)); + for (iterator it = er.first; it != er.second; ++it) { + if (nodep == it->second) { + erase(it); + return 1; + } + } + return 0; +} + V3DupFinder::iterator V3DupFinder::findDuplicate(AstNode* nodep, V3DupFinderUserSame* checkp) { const auto& er = equal_range(m_hasher(nodep)); for (iterator it = er.first; it != er.second; ++it) { @@ -37,7 +48,7 @@ V3DupFinder::iterator V3DupFinder::findDuplicate(AstNode* nodep, V3DupFinderUser if (nodep == node2p) continue; // Same node is not a duplicate if (checkp && !checkp->isSame(nodep, node2p)) continue; // User says it is not a duplicate if (!nodep->sameTree(node2p)) continue; // Not the same trees - // Found duplicate! + // Found duplicate return it; } return end(); diff --git a/src/V3DupFinder.h b/src/V3DupFinder.h index 0b512462e..4cf4b485a 100644 --- a/src/V3DupFinder.h +++ b/src/V3DupFinder.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -28,6 +28,7 @@ #include "V3Hasher.h" #include +#include //============================================================================ @@ -43,12 +44,20 @@ class V3DupFinder final : private std::multimap { using Super = std::multimap; // MEMBERS - const V3Hasher m_hasher; + const V3Hasher* const m_hasherp; // Pointer to owned hasher + const V3Hasher& m_hasher; // Reference to hasher public: // CONSTRUCTORS - V3DupFinder(){}; - ~V3DupFinder() = default; + V3DupFinder() + : m_hasherp{new V3Hasher} + , m_hasher{*m_hasherp} {} + V3DupFinder(const V3Hasher& hasher) + : m_hasherp{nullptr} + , m_hasher{hasher} {} + ~V3DupFinder() { + if (m_hasherp) delete m_hasherp; + } // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -63,10 +72,14 @@ public: using Super::end; using Super::erase; using Super::iterator; + using Super::size_type; // Insert node into data structure iterator insert(AstNode* nodep) { return emplace(m_hasher(nodep), nodep); } + // Erase node from data structure + size_type erase(AstNode* nodep); + // Return duplicate, if one was inserted, with optional user check for sameness iterator findDuplicate(AstNode* nodep, V3DupFinderUserSame* checkp = nullptr); diff --git a/src/V3EmitC.h b/src/V3EmitC.h index a9e6c5ea9..cafec665a 100644 --- a/src/V3EmitC.h +++ b/src/V3EmitC.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,9 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" - //============================================================================ class V3EmitC final { diff --git a/src/V3EmitCBase.cpp b/src/V3EmitCBase.cpp index cc98971b9..0fa62cc25 100644 --- a/src/V3EmitCBase.cpp +++ b/src/V3EmitCBase.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -184,7 +184,6 @@ void EmitCBaseVisitor::emitVarDecl(const AstVar* nodep, bool asRef) { puts("16"); } else if (nodep->isWide()) { puts("W"); - refNeedParens = true; } puts("("); @@ -235,7 +234,11 @@ void EmitCBaseVisitor::emitModCUse(const AstNodeModule* modp, VUseType useType) puts(nl); } -void EmitCBaseVisitor::emitTextSection(const AstNodeModule* modp, AstType type) { +void EmitCBaseVisitor::emitTextSection(const AstNodeModule* modp, VNType type) { + // Short circuit if nothing to do. This can save a lot of time on large designs as this + // function needs to traverse the entire module linearly. + if (!v3Global.hasSCTextSections()) return; + int last_line = -999; for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) { if (const AstNodeText* const textp = VN_CAST(nodep, NodeText)) { diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h index 65a83f69c..5f3f09f33 100644 --- a/src/V3EmitCBase.h +++ b/src/V3EmitCBase.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,7 +34,7 @@ class EmitCParentModule final { // NODE STATE // AstFunc::user4p() AstNodeModule* Parent module pointer // AstVar::user4p() AstNodeModule* Parent module pointer - const AstUser4InUse user4InUse; + const VNUser4InUse user4InUse; public: EmitCParentModule(); @@ -48,7 +48,7 @@ public: //###################################################################### // Base Visitor class -- holds output file pointer -class EmitCBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class EmitCBaseVisitor VL_NOT_FINAL : public VNVisitor { public: // STATE V3OutCFile* m_ofp = nullptr; @@ -106,31 +106,11 @@ public: void emitCFuncDecl(const AstCFunc* funcp, const AstNodeModule* modp, bool cLinkage = false); void emitVarDecl(const AstVar* nodep, bool asRef = false); void emitModCUse(const AstNodeModule* modp, VUseType useType); - void emitTextSection(const AstNodeModule* modp, AstType type); + void emitTextSection(const AstNodeModule* modp, VNType type); // CONSTRUCTORS EmitCBaseVisitor() = default; virtual ~EmitCBaseVisitor() override = default; }; -//###################################################################### -// Count operations under the given node, as a visitor of each AstNode - -class EmitCBaseCounterVisitor final : public AstNVisitor { -private: - // MEMBERS - int m_count = 0; // Number of statements - // VISITORS - virtual void visit(AstNode* nodep) override { - ++m_count; - iterateChildren(nodep); - } - -public: - // CONSTRUCTORS - explicit EmitCBaseCounterVisitor(AstNode* nodep) { iterate(nodep); } - virtual ~EmitCBaseCounterVisitor() override = default; - int count() const { return m_count; } -}; - #endif // guard diff --git a/src/V3EmitCConstInit.h b/src/V3EmitCConstInit.h index 0c2b680f1..2728fd629 100644 --- a/src/V3EmitCConstInit.h +++ b/src/V3EmitCConstInit.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,35 +34,64 @@ class EmitCConstInit VL_NOT_FINAL : public EmitCBaseVisitor { // METHODS VL_DEBUG_FUNC; // Declare debug() + uint32_t tabModulus(AstNodeDType* dtypep) { + const uint32_t elemBytes = dtypep->widthTotalBytes(); + return dtypep->isString() ? 1 // String + : elemBytes <= 2 ? 8 // CData, SData + : elemBytes <= 4 ? 4 // IData + : elemBytes <= 8 ? 2 // QData + : 1; + } + protected: // VISITORS virtual void visit(AstInitArray* nodep) override { - const AstUnpackArrayDType* const dtypep - = VN_AS(nodep->dtypep()->skipRefp(), UnpackArrayDType); - UASSERT_OBJ(dtypep, nodep, "Array initializer has non-array dtype"); - const uint32_t size = dtypep->elementsConst(); - const uint32_t elemBytes = dtypep->subDTypep()->widthTotalBytes(); - const uint32_t tabMod = dtypep->subDTypep()->isString() ? 1 // String - : elemBytes <= 2 ? 8 // CData, SData - : elemBytes <= 4 ? 4 // IData - : elemBytes <= 8 ? 2 // QData - : 1; VL_RESTORER(m_inUnpacked); VL_RESTORER(m_unpackedWord); m_inUnpacked = true; - // Note the double {{ initializer. The first { starts the initializer of the VlUnpacked, - // and the second starts the initializer of m_storage within the VlUnpacked. - puts("{"); - ofp()->putsNoTracking("{"); - puts("\n"); - for (uint32_t n = 0; n < size; ++n) { - m_unpackedWord = n; - if (n) puts((n % tabMod) ? ", " : ",\n"); - iterate(nodep->getIndexDefaultedValuep(n)); + if (const AstAssocArrayDType* const dtypep + = VN_CAST(nodep->dtypep()->skipRefp(), AssocArrayDType)) { + // Note the double {{ initializer. The first { starts the initializer of the + // VlUnpacked, and the second starts the initializer of m_storage within the + // VlUnpacked. + puts("{"); + ofp()->putsNoTracking("{"); + puts("\n"); + int comma = 0; + const auto& mapr = nodep->map(); + for (const auto& itr : mapr) { + if (comma++) putbs(",\n"); + puts(cvtToStr(itr.first)); + ofp()->printf("%" PRIx64 "ULL", itr.first); + ofp()->putsNoTracking(":"); + ofp()->putsNoTracking("{"); + iterate(nodep->getIndexValuep(itr.first)); + ofp()->putsNoTracking("}"); + } + puts("\n"); + puts("}"); + ofp()->putsNoTracking("}"); + } else if (const AstUnpackArrayDType* const dtypep + = VN_CAST(nodep->dtypep()->skipRefp(), UnpackArrayDType)) { + const vluint64_t size = dtypep->elementsConst(); + const uint32_t tabMod = tabModulus(dtypep->subDTypep()); + // Note the double {{ initializer. The first { starts the initializer of the + // VlUnpacked, and the second starts the initializer of m_storage within the + // VlUnpacked. + puts("{"); + ofp()->putsNoTracking("{"); + puts("\n"); + for (vluint64_t n = 0; n < size; ++n) { + m_unpackedWord = n; + if (n) puts((n % tabMod) ? ", " : ",\n"); + iterate(nodep->getIndexDefaultedValuep(n)); + } + puts("\n"); + puts("}"); + ofp()->putsNoTracking("}"); + } else { + nodep->v3fatalSrc("Array initializer has non-array dtype"); } - puts("\n"); - puts("}"); - ofp()->putsNoTracking("}"); } virtual void visit(AstInitItem* nodep) override { // LCOV_EXCL_START diff --git a/src/V3EmitCConstPool.cpp b/src/V3EmitCConstPool.cpp index 0aee902c4..3b11b4236 100644 --- a/src/V3EmitCConstPool.cpp +++ b/src/V3EmitCConstPool.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp index b60eca2db..5c3808332 100644 --- a/src/V3EmitCFunc.cpp +++ b/src/V3EmitCFunc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -79,8 +79,9 @@ void EmitCFunc::emitOpName(AstNode* nodep, const string& format, AstNode* lhsp, if (needComma) { if (pos[1] == ' ') { nextComma = ", "; - } else + } else { nextComma = ","; + } needComma = false; } if (pos[1] == ' ') ++pos; // Must do even if no nextComma @@ -307,7 +308,7 @@ void EmitCFunc::displayArg(AstNode* dispp, AstNode** elistp, bool isScan, const } emitDispState.pushFormat(pfmt); if (!ignore) { - if (argp->dtypep()->basicp()->keyword() == AstBasicDTypeKwd::STRING) { + if (argp->dtypep()->basicp()->keyword() == VBasicDTypeKwd::STRING) { // string in SystemVerilog is std::string in C++ which is not POD emitDispState.pushArg(' ', nullptr, "-1"); } else { @@ -542,9 +543,8 @@ void EmitCFunc::emitConstant(AstConst* nodep, AstVarRef* assigntop, const string } for (int word = VL_WORDS_I(upWidth) - 1; word >= 0; word--) { // Only 32 bits - llx + long long here just to appease CPP format warning - ofp()->printf(",0x%08" VL_PRI64 "x", - static_cast( - nodep->num().edataWord(word + chunks * EMITC_NUM_CONSTW))); + ofp()->printf(",0x%08" PRIx64, static_cast(nodep->num().edataWord( + word + chunks * EMITC_NUM_CONSTW))); } puts(")"); } @@ -565,9 +565,8 @@ void EmitCFunc::emitConstant(AstConst* nodep, AstVarRef* assigntop, const string } for (int word = EMITC_NUM_CONSTW - 1; word >= 0; word--) { // Only 32 bits - llx + long long here just to appease CPP format warning - ofp()->printf(",0x%08" VL_PRI64 "x", - static_cast( - nodep->num().edataWord(word + chunks * EMITC_NUM_CONSTW))); + ofp()->printf(",0x%08" PRIx64, static_cast(nodep->num().edataWord( + word + chunks * EMITC_NUM_CONSTW))); } puts(")"); } @@ -583,9 +582,9 @@ void EmitCFunc::emitConstant(AstConst* nodep, AstVarRef* assigntop, const string } else if (nodep->isQuad()) { const vluint64_t num = nodep->toUQuad(); if (num < 10) { - ofp()->printf("%" VL_PRI64 "uULL", num); + ofp()->printf("%" PRIu64 "ULL", num); } else { - ofp()->printf("0x%" VL_PRI64 "xULL", num); + ofp()->printf("0x%" PRIx64 "ULL", num); } } else { const uint32_t num = nodep->toUInt(); @@ -593,7 +592,7 @@ void EmitCFunc::emitConstant(AstConst* nodep, AstVarRef* assigntop, const string if (num < 10) { puts(cvtToStr(num)); } else { - ofp()->printf("0x%" VL_PRI64 "x", static_cast(num)); + ofp()->printf("0x%" PRIx64, static_cast(num)); } // If signed, we'll do our own functions // But must be here, or <= comparisons etc may end up signed @@ -622,14 +621,25 @@ void EmitCFunc::emitVarReset(AstVar* varp) { // If an ARRAYINIT we initialize it using an initial block similar to a signal // puts("// parameter "+varp->nameProtect()+" = "+varp->valuep()->name()+"\n"); } else if (const AstInitArray* const initarp = VN_CAST(varp->valuep(), InitArray)) { - if (AstUnpackArrayDType* const adtypep = VN_CAST(dtypep, UnpackArrayDType)) { + if (AstAssocArrayDType* const adtypep = VN_CAST(dtypep, AssocArrayDType)) { + if (initarp->defaultp()) { + emitSetVarConstant(varNameProtected + ".atDefault()", + VN_AS(initarp->defaultp(), Const)); + } + const auto& mapr = initarp->map(); + for (const auto& itr : mapr) { + AstNode* const valuep = itr.second->valuep(); + emitSetVarConstant(varNameProtected + ".at(" + cvtToStr(itr.first) + ")", + VN_AS(valuep, Const)); + } + } else if (AstUnpackArrayDType* const adtypep = VN_CAST(dtypep, UnpackArrayDType)) { if (initarp->defaultp()) { puts("for (int __Vi=0; __Vi<" + cvtToStr(adtypep->elementsConst())); puts("; ++__Vi) {\n"); emitSetVarConstant(varNameProtected + "[__Vi]", VN_AS(initarp->defaultp(), Const)); puts("}\n"); } - const AstInitArray::KeyItemMap& mapr = initarp->map(); + const auto& mapr = initarp->map(); for (const auto& itr : mapr) { AstNode* const valuep = itr.second->valuep(); emitSetVarConstant(varNameProtected + "[" + cvtToStr(itr.first) + "]", @@ -675,7 +685,7 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, const string& varNameP depth + 1, suffix + "[" + ivar + "]"); const string post = "}\n"; return below.empty() ? "" : pre + below + post; - } else if (basicp && basicp->keyword() == AstBasicDTypeKwd::STRING) { + } else if (basicp && basicp->keyword() == VBasicDTypeKwd::STRING) { // String's constructor deals with it return ""; } else if (basicp) { diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index a301e13cb..3910417aa 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,10 +34,10 @@ constexpr int EMITC_NUM_CONSTW = 8; //###################################################################### // Emit lazy forward declarations -class EmitCLazyDecls final : public AstNVisitor { +class EmitCLazyDecls final : public VNVisitor { // NODE STATE/TYPES // AstNode::user2() -> bool. Already emitted decl for symbols. - const AstUser2InUse m_inuser2; + const VNUser2InUse m_inuser2; // MEMBERS std::unordered_set m_emittedManually; // Set of names already declared manually. @@ -115,9 +115,9 @@ public: class EmitCFunc VL_NOT_FINAL : public EmitCConstInit { private: - AstVarRef* m_wideTempRefp; // Variable that _WW macros should be setting - int m_labelNum; // Next label number - int m_splitSize; // # of cfunc nodes placed into output file + AstVarRef* m_wideTempRefp = nullptr; // Variable that _WW macros should be setting + int m_labelNum = 0; // Next label number + int m_splitSize = 0; // # of cfunc nodes placed into output file bool m_inUC = false; // Inside an AstUCStmt or AstUCMath std::vector m_blkChangeDetVec; // All encountered changes in block bool m_emitConstInit = false; // Emitting constant initializer @@ -134,7 +134,7 @@ public: // ACCESSORS void splitSizeInc(int count) { m_splitSize += count; } - void splitSizeInc(AstNode* nodep) { splitSizeInc(EmitCBaseCounterVisitor(nodep).count()); } + void splitSizeInc(AstNode* nodep) { splitSizeInc(nodep->nodeCount()); } void splitSizeReset() { m_splitSize = 0; } bool splitNeeded() const { return v3Global.opt.outputSplit() && m_splitSize >= v3Global.opt.outputSplit(); @@ -283,7 +283,6 @@ public: } else { putbs("VL_ASSIGNSEL_"); emitIQW(selp->fromp()); - puts("II"); emitIQW(nodep->rhsp()); puts("("); puts(cvtToStr(selp->fromp()->widthMin()) + ","); @@ -442,9 +441,6 @@ public: iterateAndNextNull(nodep->exprp()); puts("; }\n"); } - virtual void visit(AstIntfRef* nodep) override { - putsQuoted(VIdProtect::protectWordsIf(AstNode::vcdName(nodep->name()), nodep->protect())); - } virtual void visit(AstNodeCase* nodep) override { // LCOV_EXCL_LINE // In V3Case... nodep->v3fatalSrc("Case statements should have been reduced out"); @@ -1229,11 +1225,7 @@ public: } EmitCFunc() - : m_lazyDecls(*this) { - m_wideTempRefp = nullptr; - m_labelNum = 0; - m_splitSize = 0; - } + : m_lazyDecls(*this) {} EmitCFunc(AstNode* nodep, V3OutCFile* ofp, bool trackText = false) : EmitCFunc{} { m_ofp = ofp; diff --git a/src/V3EmitCHeaders.cpp b/src/V3EmitCHeaders.cpp index f4b9a18de..bb26512f2 100644 --- a/src/V3EmitCHeaders.cpp +++ b/src/V3EmitCHeaders.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -192,6 +192,12 @@ class EmitCHeader final : public EmitCConstInit { puts("enum " + tdefp->name() + " {\n"); for (const AstEnumItem* itemp = edtypep->itemsp(); itemp; itemp = VN_AS(itemp->nextp(), EnumItem)) { + if (const AstConst* const constp = VN_CAST(itemp->valuep(), Const)) { + if (constp->num().isFourState()) { + puts("// " + itemp->nameProtect() + " is four-state\n"); + continue; + } + } puts(itemp->nameProtect()); puts(" = "); iterate(itemp->valuep()); @@ -243,7 +249,7 @@ class EmitCHeader final : public EmitCConstInit { emitModCUse(modp, VUseType::INT_FWD_CLASS); // From `systemc_header - emitTextSection(modp, AstType::atScHdr); + emitTextSection(modp, VNType::atScHdr); // Open class body {{{ if (const AstClass* const classp = VN_CAST(modp, Class)) { @@ -271,7 +277,7 @@ class EmitCHeader final : public EmitCConstInit { emitFuncDecls(modp, /* inClassBody: */ true); // From `systemc_interface - emitTextSection(modp, AstType::atScInt); + emitTextSection(modp, VNType::atScInt); // Close class body if (!VN_IS(modp, Class)) { diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index 2b471b6f1..94a314015 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,7 +31,7 @@ //###################################################################### // Visitor that gathers the headers required by an AstCFunc -class EmitCGatherDependencies final : AstNVisitor { +class EmitCGatherDependencies final : VNVisitor { // Ordered set, as it is used as a key in another map. std::set m_dependencies; // Header names to be included in output C++ file @@ -186,7 +186,7 @@ class EmitCImp final : EmitCFunc { puts("\n"); for (const string& name : headers) puts("#include \"" + name + ".h\"\n"); - emitTextSection(m_modp, AstType::atScImpHdr); + emitTextSection(m_modp, VNType::atScImpHdr); } void emitStaticVarDefns(const AstNodeModule* modp) { @@ -266,7 +266,7 @@ class EmitCImp final : EmitCFunc { putsDecoration("// Reset structure values\n"); puts(modName + "__" + protect("_ctor_var_reset") + "(this);\n"); - emitTextSection(modp, AstType::atScCtor); + emitTextSection(modp, VNType::atScCtor); puts("}\n"); } @@ -329,7 +329,7 @@ class EmitCImp final : EmitCFunc { void emitDestructorImp(const AstNodeModule* modp) { puts("\n"); puts(prefixNameProtect(modp) + "::~" + prefixNameProtect(modp) + "() {\n"); - emitTextSection(modp, AstType::atScDtor); + emitTextSection(modp, VNType::atScDtor); puts("}\n"); splitSizeInc(10); } @@ -353,7 +353,7 @@ class EmitCImp final : EmitCFunc { hash.insert(varp->dtypep()->width()); } } - ofp()->printf("vluint64_t __Vcheckval = 0x%" VL_PRI64 "xULL;\n", + ofp()->printf("vluint64_t __Vcheckval = 0x%" PRIx64 "ULL;\n", static_cast(hash.digestUInt64())); if (de) { puts("os.readAssert(__Vcheckval);\n"); @@ -395,7 +395,7 @@ class EmitCImp final : EmitCFunc { // Want to detect types that are represented as arrays // (i.e. packed types of more than 64 bits). if (elementp->isWide() - && !(basicp && basicp->keyword() == AstBasicDTypeKwd::STRING)) { + && !(basicp && basicp->keyword() == VBasicDTypeKwd::STRING)) { const int vecnum = vects++; const string ivar = string("__Vi") + cvtToStr(vecnum); puts("for (int __Vi" + cvtToStr(vecnum) + "=" + cvtToStr(0)); @@ -441,7 +441,7 @@ class EmitCImp final : EmitCFunc { emitCoverageImp(); } else { // From `systemc_implementation - emitTextSection(modp, AstType::atScImp); + emitTextSection(modp, VNType::atScImp); } } void emitCommonImp(const AstNodeModule* modp) { @@ -556,7 +556,7 @@ class EmitCTrace final : EmitCFunc { // NODE STATE/TYPES // Cleared on netlist // AstNode::user1() -> int. Enum number - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // MEMBERS const bool m_slow; // Making slow file @@ -631,9 +631,7 @@ class EmitCTrace final : EmitCFunc { puts("(c+" + cvtToStr(nodep->code())); if (nodep->arrayRange().ranged()) puts("+i*" + cvtToStr(nodep->widthWords())); puts(","); - if (nodep->isScoped()) puts("Verilated::catName(scopep,"); putsQuoted(VIdProtect::protectWordsIf(nodep->showname(), nodep->protect())); - if (nodep->isScoped()) puts(",(int)scopet,\" \")"); // Direction if (v3Global.opt.traceFormat().fst()) { puts("," + cvtToStr(enumNum)); @@ -649,35 +647,35 @@ class EmitCTrace final : EmitCFunc { } // // fstVarType - const AstVarType vartype = nodep->varType(); - const AstBasicDTypeKwd kwd = nodep->declKwd(); + const VVarType vartype = nodep->varType(); + const VBasicDTypeKwd kwd = nodep->declKwd(); string fstvt; // Doubles have special decoding properties, so must indicate if a double if (nodep->dtypep()->basicp()->isDouble()) { - if (vartype == AstVarType::GPARAM || vartype == AstVarType::LPARAM) { + if (vartype == VVarType::GPARAM || vartype == VVarType::LPARAM) { fstvt = "FST_VT_VCD_REAL_PARAMETER"; } else { fstvt = "FST_VT_VCD_REAL"; } } // clang-format off - else if (vartype == AstVarType::GPARAM) { fstvt = "FST_VT_VCD_PARAMETER"; } - else if (vartype == AstVarType::LPARAM) { fstvt = "FST_VT_VCD_PARAMETER"; } - else if (vartype == AstVarType::SUPPLY0) { fstvt = "FST_VT_VCD_SUPPLY0"; } - else if (vartype == AstVarType::SUPPLY1) { fstvt = "FST_VT_VCD_SUPPLY1"; } - else if (vartype == AstVarType::TRI0) { fstvt = "FST_VT_VCD_TRI0"; } - else if (vartype == AstVarType::TRI1) { fstvt = "FST_VT_VCD_TRI1"; } - else if (vartype == AstVarType::TRIWIRE) { fstvt = "FST_VT_VCD_TRI"; } - else if (vartype == AstVarType::WIRE) { fstvt = "FST_VT_VCD_WIRE"; } - else if (vartype == AstVarType::PORT) { fstvt = "FST_VT_VCD_WIRE"; } + else if (vartype == VVarType::GPARAM) { fstvt = "FST_VT_VCD_PARAMETER"; } + else if (vartype == VVarType::LPARAM) { fstvt = "FST_VT_VCD_PARAMETER"; } + else if (vartype == VVarType::SUPPLY0) { fstvt = "FST_VT_VCD_SUPPLY0"; } + else if (vartype == VVarType::SUPPLY1) { fstvt = "FST_VT_VCD_SUPPLY1"; } + else if (vartype == VVarType::TRI0) { fstvt = "FST_VT_VCD_TRI0"; } + else if (vartype == VVarType::TRI1) { fstvt = "FST_VT_VCD_TRI1"; } + else if (vartype == VVarType::TRIWIRE) { fstvt = "FST_VT_VCD_TRI"; } + else if (vartype == VVarType::WIRE) { fstvt = "FST_VT_VCD_WIRE"; } + else if (vartype == VVarType::PORT) { fstvt = "FST_VT_VCD_WIRE"; } // - else if (kwd == AstBasicDTypeKwd::INTEGER) { fstvt = "FST_VT_VCD_INTEGER"; } - else if (kwd == AstBasicDTypeKwd::BIT) { fstvt = "FST_VT_SV_BIT"; } - else if (kwd == AstBasicDTypeKwd::LOGIC) { fstvt = "FST_VT_SV_LOGIC"; } - else if (kwd == AstBasicDTypeKwd::INT) { fstvt = "FST_VT_SV_INT"; } - else if (kwd == AstBasicDTypeKwd::SHORTINT) { fstvt = "FST_VT_SV_SHORTINT"; } - else if (kwd == AstBasicDTypeKwd::LONGINT) { fstvt = "FST_VT_SV_LONGINT"; } - else if (kwd == AstBasicDTypeKwd::BYTE) { fstvt = "FST_VT_SV_BYTE"; } + else if (kwd == VBasicDTypeKwd::INTEGER) { fstvt = "FST_VT_VCD_INTEGER"; } + else if (kwd == VBasicDTypeKwd::BIT) { fstvt = "FST_VT_SV_BIT"; } + else if (kwd == VBasicDTypeKwd::LOGIC) { fstvt = "FST_VT_SV_LOGIC"; } + else if (kwd == VBasicDTypeKwd::INT) { fstvt = "FST_VT_SV_INT"; } + else if (kwd == VBasicDTypeKwd::SHORTINT) { fstvt = "FST_VT_SV_SHORTINT"; } + else if (kwd == VBasicDTypeKwd::LONGINT) { fstvt = "FST_VT_SV_LONGINT"; } + else if (kwd == VBasicDTypeKwd::BYTE) { fstvt = "FST_VT_SV_BYTE"; } else { fstvt = "FST_VT_SV_BIT"; } // clang-format on // @@ -836,12 +834,22 @@ class EmitCTrace final : EmitCFunc { EmitCFunc::visit(nodep); } + virtual void visit(AstTracePushNamePrefix* nodep) override { + puts("tracep->pushNamePrefix("); + putsQuoted(VIdProtect::protectWordsIf(nodep->prefix(), nodep->protect())); + puts(");\n"); + } + virtual void visit(AstTracePopNamePrefix* nodep) override { // + puts("tracep->popNamePrefix("); + puts(cvtToStr(nodep->count())); + puts(");\n"); + } virtual void visit(AstTraceDecl* nodep) override { const int enumNum = emitTraceDeclDType(nodep->dtypep()); if (nodep->arrayRange().ranged()) { - puts("{int i; for (i=0; i<" + cvtToStr(nodep->arrayRange().elements()) + "; i++) {\n"); + puts("for (int i = 0; i < " + cvtToStr(nodep->arrayRange().elements()) + "; ++i) {\n"); emitTraceInitOne(nodep, enumNum); - puts("}}\n"); + puts("\n}\n"); } else { emitTraceInitOne(nodep, enumNum); puts("\n"); diff --git a/src/V3EmitCInlines.cpp b/src/V3EmitCInlines.cpp index 2b68ac16f..d2002bf0d 100644 --- a/src/V3EmitCInlines.cpp +++ b/src/V3EmitCInlines.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCMain.cpp b/src/V3EmitCMain.cpp index b0475fe40..6e0ee7674 100644 --- a/src/V3EmitCMain.cpp +++ b/src/V3EmitCMain.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCMain.h b/src/V3EmitCMain.h index e9f936ea5..c61826b9b 100644 --- a/src/V3EmitCMain.h +++ b/src/V3EmitCMain.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp index dbad11203..b1919bf59 100644 --- a/src/V3EmitCMake.cpp +++ b/src/V3EmitCMake.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCMake.h b/src/V3EmitCMake.h index d62d73d42..9c17c0563 100644 --- a/src/V3EmitCMake.h +++ b/src/V3EmitCMake.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCModel.cpp b/src/V3EmitCModel.cpp index 93d84d292..84b08d76b 100644 --- a/src/V3EmitCModel.cpp +++ b/src/V3EmitCModel.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -563,9 +563,10 @@ class EmitCModel final : public EmitCFunc { "0.\");\n"); puts("}\n"); puts("vlSymsp->__Vm_baseCode = code;\n"); - puts("tracep->module(vlSymsp->name());\n"); puts("tracep->scopeEscape(' ');\n"); + puts("tracep->pushNamePrefix(std::string{vlSymsp->name()} + ' ');\n"); puts(topModNameProtected + "__" + protect("trace_init_top") + "(vlSelf, tracep);\n"); + puts("tracep->popNamePrefix();\n"); puts("tracep->scopeEscape('.');\n"); // Restore so later traced files won't break puts("}\n"); @@ -581,6 +582,14 @@ class EmitCModel final : public EmitCFunc { // ::trace puts("\nVL_ATTR_COLD void " + topClassName() + "::trace("); puts(v3Global.opt.traceClassBase() + "C* tfp, int levels, int options) {\n"); + if (optSystemC()) { + puts(/**/ "if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {\n"); + puts(/****/ "vl_fatal(__FILE__, __LINE__, name(), \"" + topClassName() + + +"::trace() is called before sc_core::sc_start(). " + "Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before trace() to complete " + "elaboration.\");\n"); + puts(/**/ "}"); + } puts(/**/ "if (false && levels && options) {} // Prevent unused\n"); puts(/**/ "tfp->spTrace()->addInitCb(&" + protect("trace_init") + ", &(vlSymsp->TOP));\n"); puts(/**/ topModNameProtected + "__" + protect("trace_register") diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index d66d4fa67..53fa6f628 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,7 +34,7 @@ class EmitCSyms final : EmitCBaseVisitor { // NODE STATE // Cleared on Netlist // AstNodeModule::user1() -> bool. Set true __Vconfigure called - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // TYPES struct ScopeData { diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index abfb1fdac..3f8024f99 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitMk.h b/src/V3EmitMk.h index 26a01e786..6b8d6b5fd 100644 --- a/src/V3EmitMk.h +++ b/src/V3EmitMk.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index ff043a143..ecec3802e 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -65,9 +65,8 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { puts(nodep->prettyName()); puts(";\n"); // Only putfs the first time for each visitor; later for same node is putqs - putqs(nodep, "begin\n"); iterateAndNextNull(nodep->stmtsp()); - putqs(nodep, "end\n"); + putfs(nodep, nodep->isFunction() ? "endfunction\n" : "endtask\n"); } virtual void visit(AstBegin* nodep) override { @@ -99,6 +98,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { iterateChildren(nodep); putqs(nodep, "end\n"); } + virtual void visit(AstInitialAutomatic* nodep) override { iterateChildren(nodep); } virtual void visit(AstAlways* nodep) override { putfs(nodep, "always "); if (m_sensesp) { @@ -124,6 +124,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { putqs(nodep, "*/\n"); } virtual void visit(AstNodeAssign* nodep) override { + if (VN_IS(nodep, AssignForce)) puts("force "); iterateAndNextNull(nodep->lhsp()); putfs(nodep, " " + nodep->verilogKwd() + " "); iterateAndNextNull(nodep->rhsp()); @@ -149,6 +150,11 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { iterateAndNextNull(nodep->rhsp()); if (!m_suppressSemi) puts(";\n"); } + virtual void visit(AstRelease* nodep) override { + puts("release "); + iterateAndNextNull(nodep->lhsp()); + if (!m_suppressSemi) puts(";\n"); + } virtual void visit(AstBreak*) override { putbs("break"); if (!m_suppressSemi) puts(";\n"); @@ -498,7 +504,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { virtual void visit(AstInitArray* nodep) override { putfs(nodep, "'{"); int comma = 0; - const AstInitArray::KeyItemMap& mapr = nodep->map(); + const auto& mapr = nodep->map(); for (const auto& itr : mapr) { if (comma++) putbs(", "); puts(cvtToStr(itr.first)); @@ -592,6 +598,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { puts(nodep->verilogKwd() + " "); if (nodep->packed()) puts("packed "); puts("\n"); + puts("{"); iterateAndNextNull(nodep->membersp()); puts("}"); } @@ -599,7 +606,6 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { iterate(nodep->subDTypep()); puts(" "); puts(nodep->name()); - puts("}"); } virtual void visit(AstNodeFTaskRef* nodep) override { if (nodep->dotted() != "") { @@ -624,18 +630,26 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { if (nodep->varScopep()) { putfs(nodep, nodep->varScopep()->prettyName()); } else { - if (nodep->selfPointer().empty()) { - putfs(nodep, nodep->varp()->prettyName()); + if (nodep->varp()) { + if (nodep->selfPointer().empty()) { + putfs(nodep, nodep->varp()->prettyName()); + } else { + putfs(nodep, nodep->selfPointer() + "->"); + puts(nodep->varp()->prettyName()); + } } else { - putfs(nodep, nodep->selfPointer() + "->"); - puts(nodep->varp()->prettyName()); + putfs(nodep, nodep->name()); } } } virtual void visit(AstVarXRef* nodep) override { putfs(nodep, nodep->dotted()); puts("."); - puts(nodep->varp()->prettyName()); + if (nodep->varp()) { + puts(nodep->varp()->prettyName()); + } else { + puts(nodep->prettyName()); + } } virtual void visit(AstConst* nodep) override { putfs(nodep, nodep->num().ascii(true, true)); } @@ -675,6 +689,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { iterateAndNextNull(nodep->stmtsp()); m_sensesp = nullptr; } + virtual void visit(AstParseRef* nodep) override { puts(nodep->prettyName()); } virtual void visit(AstVarScope*) override {} virtual void visit(AstNodeText*) override {} virtual void visit(AstTraceDecl*) override {} @@ -754,7 +769,7 @@ class EmitVPrefixedFormatter final : public V3OutFormatter { std::ostream& m_os; const string m_prefix; // What to print at beginning of each line const int m_flWidth; // Padding of fileline - int m_column; // Rough location; need just zero or non-zero + int m_column = 0; // Rough location; need just zero or non-zero FileLine* m_prefixFl; // METHODS virtual void putcOutput(char chr) override { @@ -783,7 +798,6 @@ public: , m_os(os) // Need () or GCC 4.8 false warning , m_prefix{prefix} , m_flWidth{flWidth} { - m_column = 0; m_prefixFl = v3Global.rootp()->fileline(); // NETLIST's fileline instead of nullptr to // avoid nullptr checks } @@ -818,7 +832,7 @@ public: AstSenTree* domainp, bool user3mark) : EmitVBaseVisitor{false, domainp} , m_formatter{os, prefix, flWidth} { - if (user3mark) AstUser3InUse::check(); + if (user3mark) VNUser3InUse::check(); iterate(nodep); } virtual ~EmitVPrefixedVisitor() override = default; @@ -850,10 +864,8 @@ void V3EmitV::emitvFiles() { } } -void V3EmitV::debugEmitV(const string& stage) { +void V3EmitV::debugEmitV(const string& filename) { UINFO(2, __FUNCTION__ << ": " << endl); - const string filename - = v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + "__" + stage + ".v"; V3OutVFile of(filename); { EmitVFileVisitor{v3Global.rootp(), &of, true, true}; } } diff --git a/src/V3EmitV.h b/src/V3EmitV.h index 8c3008b67..e2be6ab25 100644 --- a/src/V3EmitV.h +++ b/src/V3EmitV.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,8 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNode; +class AstSenTree; //============================================================================ @@ -31,7 +31,7 @@ public: static void verilogPrefixedTree(AstNode* nodep, std::ostream& os, const string& prefix, int flWidth, AstSenTree* domainp, bool user3mark); static void emitvFiles(); - static void debugEmitV(const string& stage); + static void debugEmitV(const string& filename); }; #endif // Guard diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp index e2af26418..d77a959ad 100644 --- a/src/V3EmitXml.cpp +++ b/src/V3EmitXml.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -28,13 +28,13 @@ //###################################################################### // Emit statements and math operators -class EmitXmlFileVisitor final : public AstNVisitor { +class EmitXmlFileVisitor final : public VNVisitor { // NODE STATE // Entire netlist: // AstNode::user1 -> uint64_t, number to connect crossrefs // MEMBERS - V3OutFile* m_ofp; + V3OutFile* const m_ofp; uint64_t m_id = 0; // METHODS @@ -61,7 +61,7 @@ class EmitXmlFileVisitor final : public AstNVisitor { void outputTag(AstNode* nodep, const string& tagin) { string tag = tagin; if (tag == "") tag = VString::downcase(nodep->typeName()); - puts("<" + tag + " " + nodep->fileline()->xml()); + puts("<" + tag); puts(" " + nodep->fileline()->xmlDetailedLocation()); if (VN_IS(nodep, NodeDType)) { puts(" id="); @@ -163,12 +163,12 @@ class EmitXmlFileVisitor final : public AstNVisitor { } virtual void visit(AstInitArray* nodep) override { puts("\n"); - const AstInitArray::KeyItemMap& map = nodep->map(); - for (AstInitArray::KeyItemMap::const_iterator it = map.begin(); it != map.end(); ++it) { + const auto& mapr = nodep->map(); + for (const auto& itr : mapr) { puts("first)); + puts(cvtToStr(itr.first)); puts("\">\n"); - iterateChildren(it->second); + iterateChildren(itr.second); puts("\n"); } puts("\n"); @@ -184,7 +184,7 @@ class EmitXmlFileVisitor final : public AstNVisitor { outputChildrenEnd(nodep, ""); } virtual void visit(AstVar* nodep) override { - const AstVarType typ = nodep->varType(); + const VVarType typ = nodep->varType(); const string kw = nodep->verilogKwd(); const string vt = nodep->dtypep()->name(); outputTag(nodep, ""); @@ -193,7 +193,7 @@ class EmitXmlFileVisitor final : public AstNVisitor { putsQuoted(kw); if (nodep->pinNum() != 0) puts(" pinIndex=\"" + cvtToStr(nodep->pinNum()) + "\""); puts(" vartype="); - putsQuoted(!vt.empty() ? vt : typ == AstVarType::PORT ? "port" : "unknown"); + putsQuoted(!vt.empty() ? vt : typ == VVarType::PORT ? "port" : "unknown"); } else { puts(" vartype="); putsQuoted(!vt.empty() ? vt : kw); @@ -321,7 +321,7 @@ public: //###################################################################### // List of module files xml visitor -class ModuleFilesXmlVisitor final : public AstNVisitor { +class ModuleFilesXmlVisitor final : public VNVisitor { private: // MEMBERS std::ostream& m_os; @@ -369,7 +369,7 @@ public: //###################################################################### // Hierarchy of Cells visitor -class HierCellsXmlVisitor final : public AstNVisitor { +class HierCellsXmlVisitor final : public VNVisitor { private: // MEMBERS std::ostream& m_os; @@ -386,8 +386,7 @@ private: if (nodep->level() >= 0 && nodep->level() <= 2) { // ==2 because we don't add wrapper when in XML mode m_os << "\n"; - m_os << "fileline()->xml() << " " - << nodep->fileline()->xmlDetailedLocation() // + m_os << "fileline()->xmlDetailedLocation() // << " name=\"" << nodep->prettyName() << "\"" << " submodname=\"" << nodep->prettyName() << "\"" << " hier=\"" << nodep->prettyName() << "\""; @@ -405,8 +404,8 @@ private: virtual void visit(AstCell* nodep) override { if (nodep->modp()->dead()) return; if (!m_hasChildren) m_os << ">\n"; - m_os << "fileline()->xml() << " " - << nodep->fileline()->xmlDetailedLocation() << " name=\"" << nodep->name() << "\"" + m_os << "fileline()->xmlDetailedLocation() << " name=\"" << nodep->name() + << "\"" << " submodname=\"" << nodep->modName() << "\"" << " hier=\"" << m_hier + nodep->name() << "\""; const std::string hier = m_hier; diff --git a/src/V3EmitXml.h b/src/V3EmitXml.h index a1ac36b1f..a8a45db59 100644 --- a/src/V3EmitXml.h +++ b/src/V3EmitXml.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,9 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" - //============================================================================ class V3EmitXml final { diff --git a/src/V3Error.cpp b/src/V3Error.cpp index d4bd9e489..9452c9ff8 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Error.h b/src/V3Error.h index aaa444cec..b0b4663d7 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp index 64fa466f1..a89d893b6 100644 --- a/src/V3Expand.cpp +++ b/src/V3Expand.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -38,11 +38,11 @@ //###################################################################### // Expand state, as a visitor of each AstNode -class ExpandVisitor final : public AstNVisitor { +class ExpandVisitor final : public VNVisitor { private: // NODE STATE // AstNode::user1() -> bool. Processed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE AstNode* m_stmtp = nullptr; // Current statement @@ -82,7 +82,7 @@ private: static void insertBefore(AstNode* placep, AstNode* newp) { newp->user1(1); // Already processed, don't need to re-iterate - AstNRelinker linker; + VNRelinker linker; placep->unlinkFrBack(&linker); newp->addNext(placep); linker.relink(newp); @@ -727,21 +727,6 @@ private: return true; } - virtual void visit(AstChangeXor* nodep) override { - if (nodep->user1SetOnce()) return; // Process once - iterateChildren(nodep); - UINFO(8, " Wordize ChangeXor " << nodep << endl); - // -> (0=={or{for each_word{WORDSEL(lhs,#)^WORDSEL(rhs,#)}}} - FileLine* const fl = nodep->fileline(); - AstNode* newp = nullptr; - for (int w = 0; w < nodep->lhsp()->widthWords(); ++w) { - AstNode* const eqp = new AstXor{fl, newAstWordSelClone(nodep->lhsp(), w), - newAstWordSelClone(nodep->rhsp(), w)}; - newp = newp ? new AstOr{fl, newp, eqp} : eqp; - } - VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep); - } - void visitEqNeq(AstNodeBiop* nodep) { if (nodep->user1SetOnce()) return; // Process once iterateChildren(nodep); diff --git a/src/V3Expand.h b/src/V3Expand.h index 5ea9e9a3d..39f2f2f23 100644 --- a/src/V3Expand.h +++ b/src/V3Expand.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3File.cpp b/src/V3File.cpp index 47cc857dd..1d5062f65 100644 --- a/src/V3File.cpp +++ b/src/V3File.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -55,7 +55,7 @@ // clang-format on // If change this code, run a test with the below size set very small -//#define INFILTER_IPC_BUFSIZ 16 +// #define INFILTER_IPC_BUFSIZ 16 constexpr int INFILTER_IPC_BUFSIZ = (64 * 1024); // For debug, try this as a small number constexpr int INFILTER_CACHE_MAX = (64 * 1024); // Maximum bytes to cache if same file read twice @@ -335,7 +335,7 @@ class VInFilterImp final { #ifdef INFILTER_PIPE pid_t m_pid = 0; // fork() process id #else - const int m_pid = 0; // fork() process id - always zero as disabled + int m_pid = 0; // fork() process id - always zero as disabled #endif bool m_pidExited = false; int m_pidStatus = 0; @@ -636,8 +636,8 @@ string V3OutFormatter::indentSpaces(int num) { return st; } -bool V3OutFormatter::tokenStart(const char* cp, const char* cmp) { - while (*cmp == *cp) { +bool V3OutFormatter::tokenMatch(const char* cp, const char* cmp) { + while (*cmp && *cmp == *cp) { ++cp; ++cmp; } @@ -646,8 +646,18 @@ bool V3OutFormatter::tokenStart(const char* cp, const char* cmp) { return true; } +bool V3OutFormatter::tokenStart(const char* cp) { + return (tokenMatch(cp, "begin") || tokenMatch(cp, "case") || tokenMatch(cp, "casex") + || tokenMatch(cp, "casez") || tokenMatch(cp, "class") || tokenMatch(cp, "function") + || tokenMatch(cp, "interface") || tokenMatch(cp, "module") || tokenMatch(cp, "package") + || tokenMatch(cp, "task")); +} + bool V3OutFormatter::tokenEnd(const char* cp) { - return (tokenStart(cp, "end") || tokenStart(cp, "endcase") || tokenStart(cp, "endmodule")); + return (tokenMatch(cp, "end") || tokenMatch(cp, "endcase") || tokenMatch(cp, "endclass") + || tokenMatch(cp, "endfunction") || tokenMatch(cp, "endinterface") + || tokenMatch(cp, "endmodule") || tokenMatch(cp, "endpackage") + || tokenMatch(cp, "endtask")); } int V3OutFormatter::endLevels(const char* strg) { @@ -698,6 +708,10 @@ void V3OutFormatter::puts(const char* strg) { bool equalsForBracket = false; // Looking for "= {" for (const char* cp = strg; *cp; cp++) { putcNoTracking(*cp); + if (isalpha(*cp)) { + if (wordstart && m_lang == LA_VERILOG && tokenStart(cp)) indentInc(); + if (wordstart && m_lang == LA_VERILOG && tokenEnd(cp)) indentDec(); + } switch (*cp) { case '\n': m_lineno++; @@ -775,26 +789,6 @@ void V3OutFormatter::puts(const char* strg) { if (cp > strg && cp[-1] == '/') indentDec(); // < ..... /> stays same level } break; - case 'b': - if (wordstart && m_lang == LA_VERILOG && tokenStart(cp, "begin")) indentInc(); - wordstart = false; - break; - case 'c': - if (wordstart && m_lang == LA_VERILOG - && (tokenStart(cp, "case") || tokenStart(cp, "casex") - || tokenStart(cp, "casez"))) { - indentInc(); - } - wordstart = false; - break; - case 'e': - if (wordstart && m_lang == LA_VERILOG && tokenEnd(cp)) indentDec(); - wordstart = false; - break; - case 'm': - if (wordstart && m_lang == LA_VERILOG && tokenStart(cp, "module")) indentInc(); - wordstart = false; - break; default: wordstart = false; break; } diff --git a/src/V3File.h b/src/V3File.h index 409c6dff4..d3d54e4f4 100644 --- a/src/V3File.h +++ b/src/V3File.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -154,7 +154,8 @@ public: puts(strg); } bool exceededWidth() const { return m_column > m_commaWidth; } - bool tokenStart(const char* cp, const char* cmp); + bool tokenMatch(const char* cp, const char* cmp); + bool tokenStart(const char* cp); bool tokenEnd(const char* cp); void indentInc() { m_indentLevel += m_blockIndent; } void indentDec() { @@ -182,7 +183,7 @@ public: class V3OutFile VL_NOT_FINAL : public V3OutFormatter { // MEMBERS - FILE* m_fp; + FILE* m_fp = nullptr; public: V3OutFile(const string& filename, V3OutFormatter::Language lang); diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp index 6a5bc2660..29d99d7c4 100644 --- a/src/V3FileLine.cpp +++ b/src/V3FileLine.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -37,7 +37,8 @@ // FileLineSingleton class functions string FileLineSingleton::filenameLetters(int fileno) { - const int size = 1 + (64 / 4); // Each letter retires more than 4 bits of a > 64 bit number + constexpr int size + = 1 + (64 / 4); // Each letter retires more than 4 bits of a > 64 bit number char out[size]; char* op = out + size - 1; *--op = '\0'; // We build backwards diff --git a/src/V3FileLine.h b/src/V3FileLine.h index 0d8519d83..dbc437588 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -200,7 +200,6 @@ public: string filebasenameNoExt() const; string firstColumnLetters() const; string profileFuncname() const; - string xml() const { return "fl=\"" + filenameLetters() + cvtToStr(lastLineno()) + "\""; } string xmlDetailedLocation() const; string lineDirectiveStrg(int enterExit) const; diff --git a/src/V3Force.cpp b/src/V3Force.cpp new file mode 100644 index 000000000..137f74fde --- /dev/null +++ b/src/V3Force.cpp @@ -0,0 +1,309 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Covert forceable signals, process force/release +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* +// V3Force's Transformations: +// +// For each forceable net with name "": +// add 3 extra signals: +// - __VforceRd: a net with same type as signal +// - __VforceEn: a var with same type as signal, which is the bitwise force enable +// - __VforceVl: a var with same type as signal, which is the forced value +// add an initial statement: +// initial __VforceEn = 0; +// add a continuous assignment: +// assign __VforceRd = __VforceEn ? __VforceVl : ; +// replace all READ references to with a read reference to _VforceRd +// +// Replace each AstAssignForce with 3 assignments: +// - __VforceEn = 1 +// - __VforceVl = +// - __VforceRd = +// +// Replace each AstRelease with 1 or 2 assignments: +// - __VforceEn = 0 +// - __VforceRd = // iff lhs is a net +// +//************************************************************************* + +#include "config_build.h" +#include "verilatedos.h" + +#include "V3Error.h" +#include "V3Global.h" +#include "V3Force.h" + +#include "V3AstUserAllocator.h" + +//###################################################################### +// Convert force/release statements and signals marked 'forceable' + +class ForceConvertVisitor final : public VNVisitor { + // TYPES + struct ForceComponentsVar { + AstVar* const m_rdVarp; // New variable to replace read references with + AstVar* const m_enVarp; // Force enabled signal + AstVar* const m_valVarp; // Forced value + AstVar* const m_phVarp; // Placeholder variable for release (never read) + explicit ForceComponentsVar(AstVar* varp) + : m_rdVarp{new AstVar{varp->fileline(), VVarType::WIRE, varp->name() + "__VforceRd", + varp->dtypep()}} + , m_enVarp{new AstVar{varp->fileline(), VVarType::VAR, varp->name() + "__VforceEn", + varp->dtypep()}} + , m_valVarp{new AstVar{varp->fileline(), VVarType::VAR, varp->name() + "__VforceVal", + varp->dtypep()}} + , m_phVarp{new AstVar{varp->fileline(), VVarType::VAR, varp->name() + "__VforcePh", + varp->dtypep()}} { + m_rdVarp->addNext(m_enVarp); + m_rdVarp->addNext(m_valVarp); + m_rdVarp->addNext(m_phVarp); + varp->addNextHere(m_rdVarp); + + if (varp->isPrimaryIO()) { + varp->v3warn( + E_UNSUPPORTED, + "Unsupported: Force/Release on primary input/output net " + << varp->prettyNameQ() << "\n" + << varp->warnMore() + << "... Suggest assign it to/from a temporary net and force/release that"); + } + } + }; + + struct ForceComponentsVarScope { + AstVarScope* const m_rdVscp; // New variable to replace read references with + AstVarScope* const m_enVscp; // Force enabled signal + AstVarScope* const m_valVscp; // Forced value + AstVarScope* const m_phVscp; // Placeholder variable for release (never read) + explicit ForceComponentsVarScope(AstVarScope* vscp, ForceComponentsVar& fcv) + : m_rdVscp{new AstVarScope{vscp->fileline(), vscp->scopep(), fcv.m_rdVarp}} + , m_enVscp{new AstVarScope{vscp->fileline(), vscp->scopep(), fcv.m_enVarp}} + , m_valVscp{new AstVarScope{vscp->fileline(), vscp->scopep(), fcv.m_valVarp}} + , m_phVscp{new AstVarScope{vscp->fileline(), vscp->scopep(), fcv.m_phVarp}} { + m_rdVscp->addNext(m_enVscp); + m_rdVscp->addNext(m_valVscp); + m_rdVscp->addNext(m_phVscp); + vscp->addNextHere(m_rdVscp); + + FileLine* const flp = vscp->fileline(); + + { // Add initialization of the enable signal + AstVarRef* const lhsp = new AstVarRef{flp, m_enVscp, VAccess::WRITE}; + V3Number zero{m_enVscp, m_enVscp->width()}; + zero.setAllBits0(); + AstNodeMath* const rhsp = new AstConst{flp, zero}; + AstAssign* const assignp = new AstAssign{flp, lhsp, rhsp}; + AstActive* const activep = new AstActive{ + flp, "force-init", + new AstSenTree{flp, new AstSenItem{flp, AstSenItem::Initial{}}}}; + activep->sensesStorep(activep->sensesp()); + activep->addStmtsp(new AstInitial{flp, assignp}); + vscp->scopep()->addActivep(activep); + } + + { // Add the combinational override + AstVarRef* const lhsp = new AstVarRef{flp, m_rdVscp, VAccess::WRITE}; + AstVarRef* const origp = new AstVarRef{flp, vscp, VAccess::READ}; + origp->user2(1); // Don't replace this read ref with the read signal + AstOr* const rhsp = new AstOr{ + flp, + new AstAnd{flp, new AstVarRef{flp, m_enVscp, VAccess::READ}, + new AstVarRef{flp, m_valVscp, VAccess::READ}}, + new AstAnd{flp, new AstNot{flp, new AstVarRef{flp, m_enVscp, VAccess::READ}}, + origp}}; + AstActive* const activep + = new AstActive{flp, "force-comb", + new AstSenTree{flp, new AstSenItem{flp, AstSenItem::Combo{}}}}; + activep->sensesStorep(activep->sensesp()); + activep->addStmtsp(new AstAssignW{flp, lhsp, rhsp}); + vscp->scopep()->addActivep(activep); + } + } + }; + + // NODE STATE + // AstVar::user1p -> ForceComponentsVar* instance (via m_forceComponentsVar) + // AstVarScope::user1p -> ForceComponentsVarScope* instance (via m_forceComponentsVarScope) + // AstVarRef::user2 -> Flag indicating not to replace reference + const VNUser1InUse m_user1InUse; + const VNUser2InUse m_user2InUse; + AstUser1Allocator m_forceComponentsVar; + AstUser1Allocator m_forceComponentsVarScope; + + // METHODS + const ForceComponentsVarScope& getForceComponents(AstVarScope* vscp) { + AstVar* const varp = vscp->varp(); + return m_forceComponentsVarScope(vscp, vscp, m_forceComponentsVar(varp, varp)); + } + + // Replace each AstNodeVarRef in the given 'nodep' that writes a variable by transforming the + // referenced AstVarScope with the given function. + void transformWritenVarScopes(AstNode* nodep, std::function f) { + UASSERT_OBJ(nodep->backp(), nodep, "Must have backp, otherwise will be lost if replaced"); + nodep->foreach([this, &f](AstNodeVarRef* refp) { + if (refp->access() != VAccess::WRITE) return; + // TODO: this is not strictly speaking safe for some complicated lvalues, eg.: + // 'force foo[a(cnt)] = 1;', where 'cnt' is an out parameter, but it will + // do for now... + refp->replaceWith( + new AstVarRef{refp->fileline(), f(refp->varScopep()), VAccess::WRITE}); + pushDeletep(refp); + }); + } + + // VISIT methods + void visit(AstNode* nodep) override { iterateChildren(nodep); } + + void visit(AstAssignForce* nodep) override { + // The AstAssignForce node will be removed for sure + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + pushDeletep(nodep); + + FileLine* const flp = nodep->fileline(); + AstNode* const lhsp = nodep->lhsp(); // The LValue we are forcing + AstNode* const rhsp = nodep->rhsp(); // The value we are forcing it to + + // Set corresponding enable signals to ones + V3Number ones{lhsp, lhsp->width()}; + ones.setAllBits1(); + AstAssign* const setEnp + = new AstAssign{flp, lhsp->cloneTree(false), new AstConst{rhsp->fileline(), ones}}; + transformWritenVarScopes(setEnp->lhsp(), [this](AstVarScope* vscp) { + return getForceComponents(vscp).m_enVscp; + }); + // Set corresponding value signals to the forced value + AstAssign* const setValp + = new AstAssign{flp, lhsp->cloneTree(false), rhsp->cloneTree(false)}; + transformWritenVarScopes(setValp->lhsp(), [this](AstVarScope* vscp) { + return getForceComponents(vscp).m_valVscp; + }); + // Set corresponding read signal directly as well, in case something in the same process + // reads it later + AstAssign* const setRdp = new AstAssign{flp, lhsp->unlinkFrBack(), rhsp->unlinkFrBack()}; + transformWritenVarScopes(setRdp->lhsp(), [this](AstVarScope* vscp) { + return getForceComponents(vscp).m_rdVscp; + }); + + setEnp->addNext(setValp); + setEnp->addNext(setRdp); + relinker.relink(setEnp); + } + + void visit(AstRelease* nodep) override { + // The AstRelease node will be removed for sure + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + pushDeletep(nodep); + + FileLine* const flp = nodep->fileline(); + AstNode* const lhsp = nodep->lhsp(); // The LValue we are releasing + + // Set corresponding enable signals to zero + V3Number zero{lhsp, lhsp->width()}; + zero.setAllBits0(); + AstAssign* const resetEnp + = new AstAssign{flp, lhsp->cloneTree(false), new AstConst{lhsp->fileline(), zero}}; + transformWritenVarScopes(resetEnp->lhsp(), [this](AstVarScope* vscp) { + return getForceComponents(vscp).m_enVscp; + }); + // IEEE 1800-2017 10.6.2: If this is a net, and not a variable, then reset the read + // signal directly as well, in case something in the same process reads it later. Also, if + // it is a variable, and not a net, set the original signal to the forced value, as it + // needs to retain the forced value until the next procedural update, which might happen on + // a later eval. Luckily we can do all this in a single assignment. + FileLine* const fl_nowarn = new FileLine{flp}; + fl_nowarn->warnOff(V3ErrorCode::BLKANDNBLK, true); + AstAssign* const resetRdp + = new AstAssign{fl_nowarn, lhsp->cloneTree(false), lhsp->unlinkFrBack()}; + // Replace write refs on the LHS + resetRdp->lhsp()->foreach([this](AstNodeVarRef* refp) { + if (refp->access() != VAccess::WRITE) return; + AstVarScope* const vscp = refp->varScopep(); + AstVarScope* const newVscp + = vscp->varp()->isContinuously() ? getForceComponents(vscp).m_rdVscp : vscp; + // Disable BLKANDNBLK for this reference + FileLine* const flp = new FileLine{refp->fileline()}; + flp->warnOff(V3ErrorCode::BLKANDNBLK, true); + AstVarRef* const newpRefp = new AstVarRef{flp, newVscp, VAccess::WRITE}; + refp->replaceWith(newpRefp); + pushDeletep(refp); + }); + // Replace write refs on RHS + resetRdp->rhsp()->foreach([this](AstNodeVarRef* refp) { + if (refp->access() != VAccess::WRITE) return; + AstVarScope* const vscp = refp->varScopep(); + AstVarScope* const newVscp + = vscp->varp()->isContinuously() ? vscp : getForceComponents(vscp).m_valVscp; + AstVarRef* const newpRefp = new AstVarRef{refp->fileline(), newVscp, VAccess::READ}; + newpRefp->user2(1); // Don't replace this read ref with the read signal + refp->replaceWith(newpRefp); + pushDeletep(refp); + }); + + resetEnp->addNext(resetRdp); + relinker.relink(resetEnp); + } + + void visit(AstVarScope* nodep) override { + // If this signal is marked externally forceable, create the public force signals + if (nodep->varp()->isForceable()) { + const ForceComponentsVarScope& fc = getForceComponents(nodep); + fc.m_enVscp->varp()->sigPublic(true); + fc.m_valVscp->varp()->sigPublic(true); + } + } + + // CONSTRUCTOR + explicit ForceConvertVisitor(AstNetlist* nodep) { + // Transform all force and release statements + iterateAndNextNull(nodep->modulesp()); + + // Replace references to forced signals + nodep->modulesp()->foreachAndNext([this](AstVarRef* nodep) { + if (ForceComponentsVarScope* const fcp + = m_forceComponentsVarScope.tryGet(nodep->varScopep())) { + switch (nodep->access()) { + case VAccess::READ: + // Read references replaced to read the new, possibly forced signal + if (!nodep->user2()) { + nodep->varp(fcp->m_rdVscp->varp()); + nodep->varScopep(fcp->m_rdVscp); + } + break; + case VAccess::WRITE: + // Write references use the original signal + break; + default: + nodep->v3error( + "Unsupported: Signals used via read-write reference cannot be forced"); + break; + } + } + }); + } + +public: + static void apply(AstNetlist* nodep) { ForceConvertVisitor{nodep}; } +}; + +//###################################################################### +// + +void V3Force::forceAll(AstNetlist* nodep) { + UINFO(2, __FUNCTION__ << ": " << endl); + if (!v3Global.hasForceableSignals()) return; + ForceConvertVisitor::apply(nodep); + V3Global::dumpCheckGlobalTree("force", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); +} diff --git a/src/V3Force.h b/src/V3Force.h new file mode 100644 index 000000000..6c1e87188 --- /dev/null +++ b/src/V3Force.h @@ -0,0 +1,33 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Process force/release +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +//************************************************************************* + +#ifndef VERILATOR_V3FORCE_H_ +#define VERILATOR_V3FORCE_H_ + +#include "config_build.h" +#include "verilatedos.h" + +class AstNetlist; + +//============================================================================ + +class V3Force final { +public: + static void forceAll(AstNetlist* nodep); +}; + +#endif // Guard diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index b14618cfb..4b66c2661 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -43,7 +43,7 @@ constexpr int GATE_DEDUP_MAX_DEPTH = 20; //###################################################################### -class GateBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class GateBaseVisitor VL_NOT_FINAL : public VNVisitor { public: VL_DEBUG_FUNC; // Declare debug() }; @@ -309,8 +309,8 @@ private: // AstVarScope::user2 -> bool: Signal used in SenItem in *this* always statement // AstVar::user2 -> bool: Warned about SYNCASYNCNET // AstNodeVarRef::user2 -> bool: ConcatOffset visited - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; // STATE V3Graph m_graph; // Scoreboard of var usages/dependencies @@ -826,10 +826,10 @@ class GateElimVisitor final : public GateBaseVisitor { private: // NODE STATE // STATE - const AstVarScope* m_elimVarScp; // Variable being eliminated - AstNode* m_replaceTreep; // What to replace the variable with - bool m_didReplace; // Did we do any replacements - GateDedupeVarVisitor* m_varVisp; // Callback to keep hash up to date + const AstVarScope* const m_elimVarScp; // Variable being eliminated + AstNode* const m_replaceTreep; // What to replace the variable with + bool m_didReplace = false; // Did we do any replacements + GateDedupeVarVisitor* const m_varVisp; // Callback to keep hash up to date // METHODS void hashReplace(AstNode* oldp, AstNode* newp); @@ -867,14 +867,13 @@ public: // CONSTRUCTORS virtual ~GateElimVisitor() override = default; GateElimVisitor(AstNode* nodep, AstVarScope* varscp, AstNode* replaceTreep, - GateDedupeVarVisitor* varVisp) { + GateDedupeVarVisitor* varVisp) + : m_elimVarScp{varscp} + , m_replaceTreep{replaceTreep} + , m_varVisp{varVisp} { UINFO(9, " elimvisitor " << nodep << endl); UINFO(9, " elim varscp " << varscp << endl); UINFO(9, " elim repce " << replaceTreep << endl); - m_didReplace = false; - m_elimVarScp = varscp; - m_replaceTreep = replaceTreep; - m_varVisp = varVisp; iterate(nodep); } bool didReplace() const { return m_didReplace; } @@ -906,11 +905,11 @@ private: // Set to nullptr if this assign's tree was later replaced // Ast*::user5p -> AstNode* of assign if condition, for isSame() in test for duplicate // Set to nullptr if this assign's tree was later replaced - // AstUser1InUse m_inuser1; (Allocated for use in GateVisitor) - // AstUser2InUse m_inuser2; (Allocated for use in GateVisitor) - const AstUser3InUse m_inuser3; - // AstUser4InUse m_inuser4; (Allocated for use in V3Hasher via V3DupFinder) - const AstUser5InUse m_inuser5; + // VNUser1InUse m_inuser1; (Allocated for use in GateVisitor) + // VNUser2InUse m_inuser2; (Allocated for use in GateVisitor) + const VNUser3InUse m_inuser3; + // VNUser4InUse m_inuser4; (Allocated for use in V3Hasher via V3DupFinder) + const VNUser5InUse m_inuser5; V3DupFinder m_dupFinder; // Duplicate finder for rhs of assigns std::unordered_set m_nodeDeleteds; // Any node in this hash was deleted @@ -1126,7 +1125,7 @@ class GateDedupeGraphVisitor final : public GateGraphBaseVisitor { private: // NODE STATE // AstVarScope::user2p -> bool: already visited - // AstUser2InUse m_inuser2; (Allocated for use in GateVisitor) + // VNUser2InUse m_inuser2; (Allocated for use in GateVisitor) VDouble0 m_numDeduped; // Statistic tracking GateDedupeVarVisitor m_varVisitor; // Looks for a dupe of the logic int m_depth = 0; // Iteration depth diff --git a/src/V3Gate.h b/src/V3Gate.h index 4aa2d351e..f7950c51d 100644 --- a/src/V3Gate.h +++ b/src/V3Gate.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3GenClk.cpp b/src/V3GenClk.cpp index 0e17bb756..a358ca2aa 100644 --- a/src/V3GenClk.cpp +++ b/src/V3GenClk.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -29,7 +29,7 @@ //###################################################################### // GenClk state, as a visitor of each AstNode -class GenClkBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class GenClkBaseVisitor VL_NOT_FINAL : public VNVisitor { protected: VL_DEBUG_FUNC; // Declare debug() }; @@ -43,8 +43,8 @@ private: // Cleared on top scope // AstVarScope::user2() -> AstVarScope*. Signal replacing activation with // AstVarRef::user3() -> bool. Signal is replaced activation (already done) - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; // STATE const AstActive* m_activep = nullptr; // Inside activate statement @@ -53,9 +53,7 @@ private: // METHODS AstVarScope* genInpClk(AstVarScope* vscp) { - if (vscp->user2p()) { - return VN_AS(vscp->user2p(), VarScope); - } else { + if (!vscp->user2p()) { // In order to create a __VinpClk* for a signal, it needs to be marked circular. // The DPI export trigger is never marked circular by V3Order (see comments in // OrderVisitor::nodeMarkCircular). The only other place where one might mark @@ -76,7 +74,7 @@ private: // ... // ASSIGN(VARREF(inpclk), VARREF(var)) AstVar* const newvarp - = new AstVar(varp->fileline(), AstVarType::MODULETEMP, newvarname, varp); + = new AstVar(varp->fileline(), VVarType::MODULETEMP, newvarname, varp); m_topModp->addStmtp(newvarp); AstVarScope* const newvscp = new AstVarScope(vscp->fileline(), m_scopetopp, newvarp); m_scopetopp->addVarp(newvscp); @@ -86,22 +84,15 @@ private: m_scopetopp->addFinalClkp(asninitp); // vscp->user2p(newvscp); - return newvscp; } + return VN_AS(vscp->user2p(), VarScope); } // VISITORS - virtual void visit(AstTopScope* nodep) override { - AstNode::user2ClearTree(); // user2p() used on entire tree - iterateChildren(nodep); - } - //---- virtual void visit(AstVarRef* nodep) override { // Consumption/generation of a variable, - AstVarScope* const vscp = nodep->varScopep(); - UASSERT_OBJ(vscp, nodep, "Scope not assigned"); - if (m_activep && !nodep->user3()) { - nodep->user3(true); + if (m_activep && !nodep->user3SetOnce()) { + AstVarScope* const vscp = nodep->varScopep(); if (vscp->isCircular()) { UINFO(8, " VarActReplace " << nodep << endl); // Replace with the new variable @@ -115,10 +106,8 @@ private: } virtual void visit(AstActive* nodep) override { m_activep = nodep; - UASSERT_OBJ(nodep->sensesp(), nodep, "Unlinked"); iterate(nodep->sensesp()); m_activep = nullptr; - iterateChildren(nodep); } //----- @@ -141,7 +130,6 @@ private: // NODE STATE // Cleared on top scope // AstVarScope::user() -> bool. Set when the var has been used as clock - const AstUser1InUse m_inuser1; // STATE bool m_tracingCall = false; // Iterating into a call to a cfunc @@ -151,13 +139,13 @@ private: // VISITORS virtual void visit(AstTopScope* nodep) override { - AstNode::user1ClearTree(); // user1p() used on entire tree - iterateChildren(nodep); { - // Make the new clock signals and replace any activate references - // See rename, it does some AstNode::userClearTree()'s - GenClkRenameVisitor{nodep, m_topModp}; + const VNUser1InUse user1InUse; + iterateChildren(nodep); } + // Make the new clock signals and replace any activate references + // See rename, it does some AstNode::userClearTree()'s + GenClkRenameVisitor{nodep, m_topModp}; } virtual void visit(AstNodeModule* nodep) override { // Only track the top scopes, not lower level functions diff --git a/src/V3GenClk.h b/src/V3GenClk.h index 3ac306bc5..df20f0c82 100644 --- a/src/V3GenClk.h +++ b/src/V3GenClk.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Global.cpp b/src/V3Global.cpp index 1e6f41a9b..98129ae78 100644 --- a/src/V3Global.cpp +++ b/src/V3Global.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -46,7 +46,7 @@ void V3Global::checkTree() const { rootp()->checkTree(); } void V3Global::readFiles() { // NODE STATE // AstNode::user4p() // VSymEnt* Package and typedef symbol names - const AstUser4InUse inuser4; + const VNUser4InUse inuser4; VInFilter filter(v3Global.opt.pipeFilter()); V3ParseSym parseSyms(v3Global.rootp()); // Symbol table must be common across all parsing diff --git a/src/V3Global.h b/src/V3Global.h index 2eba07885..84a75d7e2 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -43,7 +43,8 @@ class V3HierBlockPlan; /// end-of-stope. // Object must be named, or it will not persist until end-of-scope. // Constructor needs () or GCC 4.8 false warning. -#define VL_RESTORER(var) const VRestorer restorer_##var(var); +#define VL_RESTORER(var) \ + const VRestorer::type> restorer_##var(var); // Object used by VL_RESTORER. This object must be an auto variable, not // allocated on the heap or otherwise. @@ -89,9 +90,12 @@ inline bool operator==(VWidthMinUsage::en lhs, const VWidthMinUsage& rhs) { class V3Global final { // Globals - AstNetlist* m_rootp; // Root of entire netlist - V3HierBlockPlan* m_hierPlanp; // Hierarchical verilation plan, nullptr unless hier_block - VWidthMinUsage m_widthMinUsage; // What AstNode::widthMin() is used for + AstNetlist* m_rootp = nullptr; // Root of entire netlist, + // created by makeInitNetlist(} so static constructors run first + V3HierBlockPlan* m_hierPlanp = nullptr; // Hierarchical verilation plan, + // nullptr unless hier_block, set via hierPlanp(V3HierBlockPlan*} + VWidthMinUsage m_widthMinUsage + = VWidthMinUsage::LINT_WIDTH; // What AstNode::widthMin() is used for int m_debugFileNumber = 0; // Number to append to debug files created bool m_assertDTypesResolved = false; // Tree should have dtypep()'s @@ -100,6 +104,8 @@ class V3Global final { // Experimenting with always requiring heavy, see (#2701) bool m_needTraceDumper = false; // Need __Vm_dumperp in symbols bool m_dpi = false; // Need __Dpi include files + bool m_hasForceableSignals = false; // Need to apply V3Force pass + bool m_hasSCTextSections = false; // Has `systemc_* sections that need to be emitted bool m_useParallelBuild = false; // Use parallel build for model bool m_useRandomizeMethods = false; // Need to define randomize() class methods @@ -112,10 +118,7 @@ public: V3Options opt; // All options; let user see them directly // CONSTRUCTORS - V3Global() - : m_rootp{nullptr} // created by makeInitNetlist(} so static constructors run first - , m_hierPlanp{nullptr} // Set via hierPlanp(V3HierBlockPlan*} when use hier_block - , m_widthMinUsage{VWidthMinUsage::LINT_WIDTH} {} + V3Global() {} AstNetlist* makeNetlist(); void boot() { UASSERT(!m_rootp, "call once"); @@ -145,6 +148,10 @@ public: void needTraceDumper(bool flag) { m_needTraceDumper = flag; } bool dpi() const { return m_dpi; } void dpi(bool flag) { m_dpi = flag; } + bool hasForceableSignals() const { return m_hasForceableSignals; } + void setHasForceableSignals() { m_hasForceableSignals = true; } + bool hasSCTextSections() const { return m_hasSCTextSections; } + void setHasSCTextSections() { m_hasSCTextSections = true; } V3HierBlockPlan* hierPlanp() const { return m_hierPlanp; } void hierPlanp(V3HierBlockPlan* plan) { UASSERT(!m_hierPlanp, "call once"); diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp index f16415441..d47b786a6 100644 --- a/src/V3Graph.cpp +++ b/src/V3Graph.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -371,7 +371,7 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) const { *logp << "\tn" << edgep->fromp()->dotName() << fromVnum << " -> n" << edgep->top()->dotName() << toVnum << " [" - //<<"fontsize=8 label=\""<<(edgep->name()!="" ? edgep->name() : "\\E")<<"\"" + // <<"fontsize=8 label=\""<<(edgep->name()!="" ? edgep->name() : "\\E")<<"\"" << "fontsize=8 label=\"" << (edgep->dotLabel() != "" ? edgep->dotLabel() : "") << "\"" << " weight=" << edgep->weight() << " color=" << edgep->dotColor(); diff --git a/src/V3Graph.h b/src/V3Graph.h index 5d160dce7..c8319f5a8 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -282,7 +282,7 @@ protected: bool m_cutable; // Interconnect may be broken in order sorting union { void* m_userp; // Marker for some algorithms - uint32_t m_user; // Marker for some algorithms + uint64_t m_user; // Marker for some algorithms }; // METHODS void init(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top, int weight, @@ -326,8 +326,8 @@ public: void cutable(bool cutable) { m_cutable = cutable; } void userp(void* user) { m_userp = user; } void* userp() const { return m_userp; } - void user(uint32_t user) { m_user = user; } - uint32_t user() const { return m_user; } + void user(uint64_t user) { m_user = user; } + uint64_t user() const { return m_user; } V3GraphVertex* fromp() const { return m_fromp; } V3GraphVertex* top() const { return m_top; } V3GraphVertex* closerp(GraphWay way) const { return way.forward() ? fromp() : top(); } diff --git a/src/V3GraphAcyc.cpp b/src/V3GraphAcyc.cpp index ead5da693..a62fd3d9d 100644 --- a/src/V3GraphAcyc.cpp +++ b/src/V3GraphAcyc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,7 +31,7 @@ class GraphAcycVertex final : public V3GraphVertex { // user() is used for various sub-algorithm pieces - V3GraphVertex* m_origVertexp; // Pointer to first vertex this represents + V3GraphVertex* const m_origVertexp; // Pointer to first vertex this represents protected: friend class GraphAcyc; V3ListEnt m_work; // List of vertices with optimization work left @@ -98,7 +98,7 @@ private: // GraphEdge::user() OrigEdgeList* Old graph edges // GraphVertex::user bool Detection of loops in simplifyDupIterate // MEMBERS - V3Graph* m_origGraphp; // Original graph + V3Graph* const m_origGraphp; // Original graph V3Graph m_breakGraph; // Graph with only breakable edges represented V3List m_work; // List of vertices with optimization work left std::vector m_origEdgeDelp; // List of deletions to do when done diff --git a/src/V3GraphAlg.cpp b/src/V3GraphAlg.cpp index 7ced4a36e..9d4aa776f 100644 --- a/src/V3GraphAlg.cpp +++ b/src/V3GraphAlg.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -369,7 +369,7 @@ void V3Graph::reportLoops(V3EdgeFuncP edgeFuncp, V3GraphVertex* vertexp) { class GraphAlgSubtrees final : GraphAlg<> { private: - V3Graph* m_loopGraphp; + V3Graph* const m_loopGraphp; //! Iterate through all connected nodes of a graph with a loop or loops. V3GraphVertex* vertexIterateAll(V3GraphVertex* vertexp) { diff --git a/src/V3GraphAlg.h b/src/V3GraphAlg.h index d1c0861fd..2cc4ce9b5 100644 --- a/src/V3GraphAlg.h +++ b/src/V3GraphAlg.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3GraphPathChecker.cpp b/src/V3GraphPathChecker.cpp index a33a1d357..135e1562d 100644 --- a/src/V3GraphPathChecker.cpp +++ b/src/V3GraphPathChecker.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3GraphPathChecker.h b/src/V3GraphPathChecker.h index 16eda4764..99414e679 100644 --- a/src/V3GraphPathChecker.h +++ b/src/V3GraphPathChecker.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3GraphStream.h b/src/V3GraphStream.h index c465bd1fa..f05e9a37e 100644 --- a/src/V3GraphStream.h +++ b/src/V3GraphStream.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -23,6 +23,8 @@ #include "V3Graph.h" +#include +#include #include #include @@ -43,7 +45,7 @@ private: class VxHolder final { public: // MEMBERS - const V3GraphVertex* m_vxp; // [mtask] Vertex + const V3GraphVertex* const m_vxp; // [mtask] Vertex const uint32_t m_pos; // Sort position uint32_t m_numBlockingEdges; // Number of blocking edges // CONSTRUCTORS @@ -57,7 +59,7 @@ private: // newly unblocked bool unblock() { UASSERT_OBJ(m_numBlockingEdges > 0, vertexp(), "Underflow of blocking edges"); - m_numBlockingEdges--; + --m_numBlockingEdges; return (m_numBlockingEdges == 0); } }; diff --git a/src/V3GraphTest.cpp b/src/V3GraphTest.cpp index aed59ae8a..757c7ff70 100644 --- a/src/V3GraphTest.cpp +++ b/src/V3GraphTest.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Hash.cpp b/src/V3Hash.cpp index 65059102a..38837e6c2 100644 --- a/src/V3Hash.cpp +++ b/src/V3Hash.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Hash.h b/src/V3Hash.h index ef00d0a83..8c4d75e08 100644 --- a/src/V3Hash.h +++ b/src/V3Hash.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp index f520c4a0d..56652e647 100644 --- a/src/V3Hasher.cpp +++ b/src/V3Hasher.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -24,11 +24,11 @@ //###################################################################### // Visitor that computes node hashes -class HasherVisitor final : public AstNVisitor { +class HasherVisitor final : public VNVisitor { private: // NODE STATE // AstNode::user4() -> V3Hash. Hash value of this node (hash of 0 is illegal) - // AstUser4InUse in V3Hasher.h + // VNUser4InUse in V3Hasher.h // STATE V3Hash m_hash; // Hash value accumulator @@ -39,6 +39,7 @@ private: V3Hash hashNodeAndIterate(AstNode* nodep, bool hashDType, bool hashChildren, std::function&& f) { + // See comments in visit(AstCFunc) about this breaking recursion if (m_cacheInUser4 && nodep->user4()) { return V3Hash(nodep->user4()); } else { @@ -351,17 +352,30 @@ private: m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); } virtual void visit(AstInitArray* nodep) override { - // Hash unpacked array initializers by value, as the order of initializer nodes does not - // matter, and we want semantically equivalent initializers to map to the same hash. - const AstUnpackArrayDType* const dtypep = VN_CAST(nodep->dtypep(), UnpackArrayDType); - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, /* hashChildren: */ !dtypep, [=]() { - if (dtypep) { - const uint32_t size = dtypep->elementsConst(); - for (uint32_t n = 0; n < size; ++n) { // - iterateNull(nodep->getIndexDefaultedValuep(n)); - } + if (const AstAssocArrayDType* const dtypep = VN_CAST(nodep->dtypep(), AssocArrayDType)) { + if (nodep->defaultp()) { + m_hash + += hashNodeAndIterate(nodep->defaultp(), HASH_DTYPE, HASH_CHILDREN, [=]() {}); } - }); + const auto& mapr = nodep->map(); + for (const auto& itr : mapr) { // mapr is sorted, so hash should get stable results + m_hash += itr.first; + m_hash += hashNodeAndIterate(itr.second, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + } + } else if (const AstUnpackArrayDType* const dtypep + = VN_CAST(nodep->dtypep(), UnpackArrayDType)) { + // Hash unpacked array initializers by value, as the order of initializer nodes does + // not matter, and we want semantically equivalent initializers to map to the same + // hash. + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, /* hashChildren: */ !dtypep, [=]() { + if (dtypep) { + const uint32_t size = dtypep->elementsConst(); + for (uint32_t n = 0; n < size; ++n) { // + iterateNull(nodep->getIndexDefaultedValuep(n)); + } + } + }); + } } virtual void visit(AstPragma* nodep) override { m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // @@ -380,6 +394,12 @@ private: } virtual void visit(AstCFunc* nodep) override { m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + // We might be in a recursive function, if so on *second* call + // here we need to break what would be an infinite loop. + nodep->user4(V3Hash(1).value()); // Set this "first" call + // So that a second call will then exit hashNodeAndIterate + // Having a constant in the hash just means the recursion will + // end, it shouldn't change the CFunc having a unique hash itself. m_hash += nodep->isLoose(); }); } @@ -475,11 +495,12 @@ private: public: // CONSTRUCTORS - explicit HasherVisitor(AstNode* nodep) + HasherVisitor(AstNode* nodep) : m_cacheInUser4{true} { iterate(nodep); } - explicit HasherVisitor(const AstNode* nodep) + class Uncached {}; + HasherVisitor(const AstNode* nodep, Uncached) : m_cacheInUser4{false} { iterate(const_cast(nodep)); } @@ -491,11 +512,25 @@ public: // V3Hasher methods V3Hash V3Hasher::operator()(AstNode* nodep) const { - if (!nodep->user4()) { HasherVisitor{nodep}; } + if (!nodep->user4()) HasherVisitor{nodep}; + return V3Hash(nodep->user4()); +} + +V3Hash V3Hasher::rehash(AstNode* nodep) const { + nodep->user4(0); + HasherVisitor{nodep}; return V3Hash(nodep->user4()); } V3Hash V3Hasher::uncachedHash(const AstNode* nodep) { - const HasherVisitor visitor{nodep}; + const HasherVisitor visitor{nodep, HasherVisitor::Uncached{}}; return visitor.finalHash(); } + +//###################################################################### +// This is used by the std::hash specialization for VNRef. +// Declared separately to avoid a circular header dependency. + +size_t V3HasherUncachedHash(AstNode& node) { + return static_cast(V3Hasher::uncachedHash(&node).value()); +} diff --git a/src/V3Hasher.h b/src/V3Hasher.h index 6bdfdc6be..57e3176a0 100644 --- a/src/V3Hasher.h +++ b/src/V3Hasher.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,7 +32,7 @@ class V3Hasher final { // NODE STATE // AstNode::user4() -> V3Hash. Hash value of this node (hash of 0 is illegal) - const AstUser4InUse m_inuser4; + const VNUser4InUse m_inuser4; public: // CONSTRUCTORS @@ -45,6 +45,9 @@ public: // Compute hash of node. This method caches the hash in the node's user4(). V3Hash operator()(AstNode* nodep) const; + // Re-compute hash of this node, discarding cached value, but used cached hash of children. + V3Hash rehash(AstNode* nodep) const; + // Compute hash of node, without caching in user4. static V3Hash uncachedHash(const AstNode* nodep); }; diff --git a/src/V3HierBlock.cpp b/src/V3HierBlock.cpp index 57b781b04..79701ba80 100644 --- a/src/V3HierBlock.cpp +++ b/src/V3HierBlock.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,7 +36,7 @@ // Then user can build Verilated module as usual. // // Here is more detailed internal process. -// 1) Parser adds AstPragmaType::HIER_BLOCK of AstPragma to modules +// 1) Parser adds VPragmaType::HIER_BLOCK of AstPragma to modules // that are marked with /*verilator hier_block*/ metacomment in Verilator run a). // 2) AstModule with HIER_BLOCK pragma is marked modp->hier_block(true) // in V3LinkResolve.cpp during run a). @@ -236,10 +236,10 @@ string V3HierBlock::commandArgsFileName(bool forCMake) const { //###################################################################### // Collect how hierarchical blocks are used -class HierBlockUsageCollectVisitor final : public AstNVisitor { +class HierBlockUsageCollectVisitor final : public VNVisitor { // NODE STATE // AstNode::user1() -> bool. Processed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE using ModuleSet = std::unordered_set; @@ -247,7 +247,7 @@ class HierBlockUsageCollectVisitor final : public AstNVisitor { AstModule* m_modp = nullptr; // The current module AstModule* m_hierBlockp = nullptr; // The nearest parent module that is a hierarchical block ModuleSet m_referred; // Modules that have hier_block pragma - V3HierBlock::GParams m_gparams; // list of variables that is AstVarType::GPARAM + V3HierBlock::GParams m_gparams; // list of variables that is VVarType::GPARAM virtual void visit(AstModule* nodep) override { // Don't visit twice diff --git a/src/V3HierBlock.h b/src/V3HierBlock.h index 38b34b4ed..7a01dd1a2 100644 --- a/src/V3HierBlock.h +++ b/src/V3HierBlock.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -29,11 +29,12 @@ #include #include #include +#include #include #include -class AstNodeModule; class AstNetlist; +class AstNodeModule; class AstVar; //###################################################################### diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index 858f6a83d..eabbca566 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,28 +34,45 @@ #include "V3Ast.h" #include "V3String.h" +#include "V3AstUserAllocator.h" + #include -#include #include +#include // CONFIG static const int INLINE_MODS_SMALLER = 100; // If a mod is < this # nodes, can always inline it //###################################################################### -// Inline state, as a visitor of each AstNode +// Inlining state. Kept as AstNodeModule::user1p via AstUser1Allocator -class InlineMarkVisitor final : public AstNVisitor { +namespace { + +struct ModuleState { + bool m_inlined = false; // Whether to inline this module + unsigned m_cellRefs = 0; // Number of AstCells instantiating this module + std::vector m_childCells; // AstCells under this module (to speed up traversal) +}; + +using ModuleStateUser1Allocator = AstUser1Allocator; + +} // namespace + +//###################################################################### +// Visitor that determines which modules will be inlined + +class InlineMarkVisitor final : public VNVisitor { private: // NODE STATE // Output - // AstNodeModule::user1() // OUTPUT: bool. User request to inline this module + // AstNodeModule::user1() // OUTPUT: ModuleState instance (via m_moduleState) // Internal state (can be cleared after this visit completes) // AstNodeModule::user2() // CIL_*. Allowed to automatically inline module - // AstNodeModule::user3() // int. Number of cells referencing this module // AstNodeModule::user4() // int. Statements in module - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; - const AstUser4InUse m_inuser4; + const VNUser2InUse m_inuser2; + const VNUser4InUse m_inuser4; + + ModuleStateUser1Allocator& m_moduleState; // For the user2 field: enum : uint8_t { @@ -68,13 +85,11 @@ private: // STATE AstNodeModule* m_modp = nullptr; // Current module VDouble0 m_statUnsup; // Statistic tracking - - using ModVec = std::vector; - ModVec m_allMods; // All modules, in top-down order. + std::vector m_allMods; // All modules, in top-down order. // Within the context of a given module, LocalInstanceMap maps // from child modules to the count of each child's local instantiations. - using LocalInstanceMap = std::unordered_map; + using LocalInstanceMap = std::unordered_map; // We keep a LocalInstanceMap for each module in the design std::unordered_map m_instances; @@ -98,7 +113,7 @@ private: // VISITORS virtual void visit(AstNodeModule* nodep) override { - UASSERT_OBJ(!m_modp, nodep, "Unsupported: Recursive modules"); + UASSERT_OBJ(!m_modp, nodep, "Unsupported: Nested modules"); m_modp = nodep; m_allMods.push_back(nodep); m_modp->user2(CIL_MAYBE); @@ -122,45 +137,44 @@ private: iterateChildren(nodep); } virtual void visit(AstCell* nodep) override { - nodep->modp()->user3Inc(); // Inc refs + m_moduleState(nodep->modp()).m_cellRefs++; + m_moduleState(m_modp).m_childCells.push_back(nodep); m_instances[m_modp][nodep->modp()]++; iterateChildren(nodep); } virtual void visit(AstPragma* nodep) override { - if (nodep->pragType() == AstPragmaType::INLINE_MODULE) { - // UINFO(0, "PRAG MARK " << m_modp << endl); + if (nodep->pragType() == VPragmaType::INLINE_MODULE) { if (!m_modp) { nodep->v3error("Inline pragma not under a module"); // LCOV_EXCL_LINE } else if (m_modp->user2() == CIL_MAYBE || m_modp->user2() == CIL_NOTSOFT) { m_modp->user2(CIL_USER); } - // Remove so don't propagate to upper cell... + // Remove so it does not propagate to upper cell VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->pragType() == AstPragmaType::NO_INLINE_MODULE) { + } else if (nodep->pragType() == VPragmaType::NO_INLINE_MODULE) { if (!m_modp) { nodep->v3error("Inline pragma not under a module"); // LCOV_EXCL_LINE } else if (!v3Global.opt.flatten()) { cantInline("Pragma NO_INLINE_MODULE", false); } + // Remove so it does not propagate to upper cell // Remove so don't propagate to upper cell... VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else { - iterateChildren(nodep); } } virtual void visit(AstVarXRef* nodep) override { - // Cleanup link until V3LinkDot can correct it + // Remove link. V3LinkDot will reestablish it after inlining. nodep->varp(nullptr); } virtual void visit(AstNodeFTaskRef* nodep) override { - // Cleanup link until V3LinkDot can correct it + // Remove link. V3LinkDot will reestablish it after inlining. // MethodCalls not currently supported by inliner, so keep linked if (!nodep->classOrPackagep() && !VN_IS(nodep, MethodCall)) nodep->taskp(nullptr); iterateChildren(nodep); } virtual void visit(AstAlways* nodep) override { - iterateChildren(nodep); m_modp->user4Inc(); // statement count + iterateChildren(nodep); } virtual void visit(AstNodeAssign* nodep) override { // Don't count assignments, as they'll likely flatten out @@ -170,7 +184,7 @@ private: m_modp->user4(oldcnt); } virtual void visit(AstNetlist* nodep) override { - // Build user2, user3, and user4 for all modules. + // Build ModuleState, user2, and user4 for all modules. // Also build m_allMods and m_instances. iterateChildren(nodep); @@ -182,87 +196,57 @@ private: // If we're going to inline some modules into this one, // update user4 (statement count) to reflect that: int statements = modp->user4(); - LocalInstanceMap& localsr = m_instances[modp]; - for (LocalInstanceMap::iterator iti = localsr.begin(); iti != localsr.end(); ++iti) { - const AstNodeModule* const childp = iti->first; - if (childp->user1()) { // inlining child - statements += (childp->user4() * iti->second); + for (const auto& pair : m_instances[modp]) { + const AstNodeModule* const childp = pair.first; + if (m_moduleState(childp).m_inlined) { // inlining child + statements += childp->user4() * pair.second; } } modp->user4(statements); const int allowed = modp->user2(); - const int refs = modp->user3(); + const int refs = m_moduleState(modp).m_cellRefs; // Should we automatically inline this module? // If --flatten is specified, then force everything to be inlined that can be. // inlineMult = 2000 by default. // If a mod*#refs is < this # nodes, can inline it - bool doit = ((allowed == CIL_USER) - || ((allowed == CIL_MAYBE) - && (v3Global.opt.flatten() - || (refs == 1 || statements < INLINE_MODS_SMALLER - || v3Global.opt.inlineMult() < 1 - || refs * statements < v3Global.opt.inlineMult())))); // Packages aren't really "under" anything so they confuse this algorithm - if (VN_IS(modp, Package)) doit = false; + const bool doit = !VN_IS(modp, Package) // + && allowed != CIL_NOTHARD // + && allowed != CIL_NOTSOFT // + && (allowed == CIL_USER // + || v3Global.opt.flatten() // + || refs == 1 // + || statements < INLINE_MODS_SMALLER // + || v3Global.opt.inlineMult() < 1 // + || refs * statements < v3Global.opt.inlineMult()); + m_moduleState(modp).m_inlined = doit; UINFO(4, " Inline=" << doit << " Possible=" << allowed << " Refs=" << refs << " Stmts=" << statements << " " << modp << endl); - modp->user1(doit); } } //-------------------- virtual void visit(AstNode* nodep) override { + if (m_modp) m_modp->user4Inc(); // Inc statement count iterateChildren(nodep); - if (m_modp) { - m_modp->user4Inc(); // Inc statement count - } } public: // CONSTRUCTORS - explicit InlineMarkVisitor(AstNode* nodep) { iterate(nodep); } - virtual ~InlineMarkVisitor() override { - V3Stats::addStat("Optimizations, Inline unsupported", m_statUnsup); - // Done with these, are not outputs - AstNode::user2ClearTree(); - AstNode::user3ClearTree(); - AstNode::user4ClearTree(); - } -}; - -//###################################################################### -// Using clonep(), find cell cross references. -// clone() must not be called inside this visitor - -class InlineCollectVisitor final : public AstNVisitor { -private: - // NODE STATE - // Output: - // AstCell::user4p() // AstCell* of the created clone - - // METHODS - VL_DEBUG_FUNC; // Declare debug() - - // VISITORS - virtual void visit(AstCell* nodep) override { nodep->user4p(nodep->clonep()); } - //-------------------- - virtual void visit(AstNodeStmt*) override {} // Accelerate - virtual void visit(AstNodeMath*) override {} // Accelerate - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - explicit InlineCollectVisitor(AstNodeModule* nodep) { // passed OLD module, not new one + explicit InlineMarkVisitor(AstNode* nodep, ModuleStateUser1Allocator& moduleState) + : m_moduleState{moduleState} { iterate(nodep); } - virtual ~InlineCollectVisitor() override = default; + virtual ~InlineMarkVisitor() override { + V3Stats::addStat("Optimizations, Inline unsupported", m_statUnsup); + } }; //###################################################################### // After cell is cloned, relink the new module's contents -class InlineRelinkVisitor final : public AstNVisitor { +class InlineRelinkVisitor final : public VNVisitor { private: // NODE STATE // Input: @@ -282,21 +266,18 @@ private: nodep->unlinkFrBack(); m_modp->addInlinesp(nodep); // Rename - const string name = m_cellp->name() + "__DOT__" + nodep->name(); - nodep->name(name); + nodep->name(m_cellp->name() + "__DOT__" + nodep->name()); UINFO(6, " Inline " << nodep << endl); // Do CellInlines under this, but don't move them iterateChildren(nodep); } virtual void visit(AstCell* nodep) override { // Cell under the inline cell, need to rename to avoid conflicts - const string name = m_cellp->name() + "__DOT__" + nodep->name(); - nodep->name(name); + nodep->name(m_cellp->name() + "__DOT__" + nodep->name()); iterateChildren(nodep); } virtual void visit(AstClass* nodep) override { - const string name = m_cellp->name() + "__DOT__" + nodep->name(); - nodep->name(name); + nodep->name(m_cellp->name() + "__DOT__" + nodep->name()); iterateChildren(nodep); } virtual void visit(AstModule* nodep) override { @@ -307,50 +288,48 @@ private: if (nodep->user2p()) { // Make an assignment, so we'll trace it properly // user2p is either a const or a var. + FileLine* const flp = nodep->fileline(); AstConst* const exprconstp = VN_CAST(nodep->user2p(), Const); const AstVarRef* const exprvarrefp = VN_CAST(nodep->user2p(), VarRef); UINFO(8, "connectto: " << nodep->user2p() << endl); UASSERT_OBJ(exprconstp || exprvarrefp, nodep, "Unknown interconnect type; pinReconnectSimple should have cleared up"); if (exprconstp) { - m_modp->addStmtp(new AstAssignW( - nodep->fileline(), new AstVarRef(nodep->fileline(), nodep, VAccess::WRITE), - exprconstp->cloneTree(true))); + m_modp->addStmtp(new AstAssignW(flp, new AstVarRef(flp, nodep, VAccess::WRITE), + exprconstp->cloneTree(false))); } else if (nodep->user3()) { // Public variable at the lower module end - we need to make sure we propagate // the logic changes up and down; if we aliased, we might // remove the change detection on the output variable. UINFO(9, "public pin assign: " << exprvarrefp << endl); UASSERT_OBJ(!nodep->isNonOutput(), nodep, "Outputs only - inputs use AssignAlias"); - m_modp->addStmtp(new AstAssignW( - nodep->fileline(), - new AstVarRef(nodep->fileline(), exprvarrefp->varp(), VAccess::WRITE), - new AstVarRef(nodep->fileline(), nodep, VAccess::READ))); + m_modp->addStmtp( + new AstAssignW(flp, new AstVarRef(flp, exprvarrefp->varp(), VAccess::WRITE), + new AstVarRef(flp, nodep, VAccess::READ))); } else if (nodep->isSigPublic() && VN_IS(nodep->dtypep(), UnpackArrayDType)) { // Public variable at this end and it is an unpacked array. We need to assign // instead of aliased, because otherwise it will pass V3Slice and invalid // code will be emitted. UINFO(9, "assign to public and unpacked: " << nodep << endl); - m_modp->addStmtp(new AstAssignW( - nodep->fileline(), - new AstVarRef(nodep->fileline(), exprvarrefp->varp(), VAccess::WRITE), - new AstVarRef(nodep->fileline(), nodep, VAccess::READ))); + m_modp->addStmtp( + new AstAssignW(flp, new AstVarRef(flp, exprvarrefp->varp(), VAccess::WRITE), + new AstVarRef(flp, nodep, VAccess::READ))); } else if (nodep->isIfaceRef()) { - m_modp->addStmtp(new AstAssignVarScope( - nodep->fileline(), new AstVarRef(nodep->fileline(), nodep, VAccess::WRITE), - new AstVarRef(nodep->fileline(), exprvarrefp->varp(), VAccess::READ))); - const AstNode* const nodebp = exprvarrefp->varp(); - nodep->fileline()->modifyStateInherit(nodebp->fileline()); - nodebp->fileline()->modifyStateInherit(nodep->fileline()); + m_modp->addStmtp( + new AstAssignVarScope(flp, new AstVarRef(flp, nodep, VAccess::WRITE), + new AstVarRef(flp, exprvarrefp->varp(), VAccess::READ))); + FileLine* const flbp = exprvarrefp->varp()->fileline(); + flp->modifyStateInherit(flbp); + flbp->modifyStateInherit(flp); } else { // Do to inlining child's variable now within the same // module, so a AstVarRef not AstVarXRef below - m_modp->addStmtp(new AstAssignAlias( - nodep->fileline(), new AstVarRef(nodep->fileline(), nodep, VAccess::WRITE), - new AstVarRef(nodep->fileline(), exprvarrefp->varp(), VAccess::READ))); - const AstNode* const nodebp = exprvarrefp->varp(); - nodep->fileline()->modifyStateInherit(nodebp->fileline()); - nodebp->fileline()->modifyStateInherit(nodep->fileline()); + m_modp->addStmtp( + new AstAssignAlias(flp, new AstVarRef(flp, nodep, VAccess::WRITE), + new AstVarRef(flp, exprvarrefp->varp(), VAccess::READ))); + FileLine* const flbp = exprvarrefp->varp()->fileline(); + flp->modifyStateInherit(flbp); + flbp->modifyStateInherit(flp); } } // Iterate won't hit AstIfaceRefDType directly as it is no longer underneath the module @@ -381,7 +360,6 @@ private: if (!m_cellp->isTrace()) nodep->trace(false); if (debug() >= 9) nodep->dumpTree(cout, "varchanged:"); if (debug() >= 9 && nodep->valuep()) nodep->valuep()->dumpTree(cout, "varchangei:"); - iterateChildren(nodep); } virtual void visit(AstNodeFTask* nodep) override { // Function under the inline cell, need to rename to avoid conflicts @@ -398,25 +376,22 @@ private: && !nodep->varp()->user3() // Don't constant propagate aliases (we just made) && !VN_IS(nodep->backp(), AssignAlias)) { - AstConst* const exprconstp = VN_CAST(nodep->varp()->user2p(), Const); - const AstVarRef* const exprvarrefp = VN_CAST(nodep->varp()->user2p(), VarRef); - if (exprconstp) { - nodep->replaceWith(exprconstp->cloneTree(true)); + AstVar* const varp = nodep->varp(); + if (AstConst* const constp = VN_CAST(varp->user2p(), Const)) { + nodep->replaceWith(constp->cloneTree(false)); VL_DO_DANGLING(nodep->deleteTree(), nodep); return; - } else if (exprvarrefp) { - nodep->varp(exprvarrefp->varp()); + } else if (const AstVarRef* const vrefp = VN_CAST(varp->user2p(), VarRef)) { + nodep->varp(vrefp->varp()); } else { nodep->v3fatalSrc("Null connection?"); } } nodep->name(nodep->varp()->name()); - iterateChildren(nodep); } virtual void visit(AstVarXRef* nodep) override { // Track what scope it was originally under so V3LinkDot can resolve it - const string newdots = VString::dot(m_cellp->name(), ".", nodep->inlinedDots()); - nodep->inlinedDots(newdots); + nodep->inlinedDots(VString::dot(m_cellp->name(), ".", nodep->inlinedDots())); for (string tryname = nodep->dotted(); true;) { if (m_renamedInterfaces.count(tryname)) { nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted()); @@ -434,8 +409,7 @@ private: } virtual void visit(AstNodeFTaskRef* nodep) override { // Track what scope it was originally under so V3LinkDot can resolve it - const string newdots = VString::dot(m_cellp->name(), ".", nodep->inlinedDots()); - nodep->inlinedDots(newdots); + nodep->inlinedDots(VString::dot(m_cellp->name(), ".", nodep->inlinedDots())); if (m_renamedInterfaces.count(nodep->dotted())) { nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted()); } @@ -480,23 +454,23 @@ public: //###################################################################### // Inline state, as a visitor of each AstNode -class InlineVisitor final : public AstNVisitor { +class InlineVisitor final : public VNVisitor { private: // NODE STATE // Cleared entire netlist // AstIfaceRefDType::user5p() // Whether the cell pointed to by this // // AstIfaceRefDType has been inlined // Input: - // AstNodeModule::user1p() // bool. True to inline this module (from InlineMarkVisitor) + // AstNodeModule::user1p() // ModuleState instance (via m_moduleState) // Cleared each cell // AstVar::user2p() // AstVarRef*/AstConst* Points to signal this // // is a direct connect to // AstVar::user3() // bool Don't alias the user2, keep it as signal // AstCell::user4 // AstCell* of the created clone - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; - const AstUser4InUse m_inuser4; - const AstUser5InUse m_inuser5; + const VNUser4InUse m_inuser4; + const VNUser5InUse m_inuser5; + + ModuleStateUser1Allocator& m_moduleState; // STATE AstNodeModule* m_modp = nullptr; // Current module @@ -505,10 +479,117 @@ private: // METHODS VL_DEBUG_FUNC; // Declare debug() + void inlineCell(AstCell* nodep) { + UINFO(5, " Inline CELL " << nodep << endl); + + const VNUser2InUse user2InUse; + const VNUser3InUse user3InUse; + + ++m_statCells; + + // Before cloning simplify pin assignments. Better off before, as if the module has + // multiple instantiations we will save work, and we can't call pinReconnectSimple in this + // loop as it clone()s itself. + for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { + V3Inst::pinReconnectSimple(pinp, nodep, false); + } + + // Is this the last cell referencing this module? + const bool lastCell = --m_moduleState(nodep->modp()).m_cellRefs == 0; + + // Important: If this is the last cell, then don't clone the instantiated module but + // inline the original directly. While this requires some special casing, doing so + // saves us having to temporarily clone the module for the last cell, which + // significantly reduces Verilator memory usage. This is especially true as often the + // top few levels of the hierarchy are singleton wrapper modules, which we always + // inline. In this case this special casing saves us from having to clone essentially + // the entire netlist, which would in effect double Verilator memory consumption, or + // worse if we put off deleting the inlined modules until the end. Not having to clone + // large trees also improves speed. + AstNodeModule* newmodp = nullptr; + if (!lastCell) { + // Clone original module + newmodp = nodep->modp()->cloneTree(false); + } else { + // For the last cell, reuse the original module + nodep->modp()->unlinkFrBack(); + newmodp = nodep->modp(); + } + // Find cell cross-references + nodep->modp()->foreach([](AstCell* cellp) { + // clonep is nullptr when inlining the last instance, if so the use original node + cellp->user4p(cellp->clonep() ? cellp->clonep() : cellp); + }); + // Create data for dotted variable resolution + AstCellInline* const inlinep + = new AstCellInline(nodep->fileline(), nodep->name(), nodep->modp()->origName(), + nodep->modp()->timeunit()); + m_modp->addInlinesp(inlinep); // Must be parsed before any AstCells + // Create assignments to the pins + for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { + if (!pinp->exprp()) continue; + UINFO(6, " Pin change from " << pinp->modVarp() << endl); + + AstNode* const connectRefp = pinp->exprp(); + UASSERT_OBJ(VN_IS(connectRefp, Const) || VN_IS(connectRefp, VarRef), pinp, + "Unknown interconnect type; pinReconnectSimple should have cleared up"); + V3Inst::checkOutputShort(pinp); + + // Make new signal; even though we'll optimize the interconnect, we + // need an alias to trace correctly. If tracing is disabled, we'll + // delete it in later optimizations. + AstVar* const pinOldVarp = pinp->modVarp(); + AstVar* const pinNewVarp = lastCell ? pinOldVarp : pinOldVarp->clonep(); + UASSERT_OBJ(pinNewVarp, pinOldVarp, "Cloning failed"); + // Propagate any attributes across the interconnect + pinNewVarp->propagateAttrFrom(pinOldVarp); + if (const AstVarRef* const vrefp = VN_CAST(connectRefp, VarRef)) { + vrefp->varp()->propagateAttrFrom(pinOldVarp); + } + + // One to one interconnect won't make a temporary variable. + // This prevents creating a lot of extra wires for clock signals. + // It will become a tracing alias. + UINFO(6, "One-to-one " << connectRefp << endl); + UINFO(6, " -to " << pinNewVarp << endl); + pinNewVarp->user2p(connectRefp); + // Public output inside the cell must go via an assign rather + // than alias. Else the public logic will set the alias, losing + // the value to be propagated up (InOnly isn't a problem as the + // AssignAlias will create the assignment for us) + pinNewVarp->user3(pinNewVarp->isSigUserRWPublic() + && pinNewVarp->direction() == VDirection::OUTPUT); + } + // Cleanup var names, etc, to not conflict + { InlineRelinkVisitor{newmodp, m_modp, nodep}; } + // Move statements under the module we are inlining into + if (AstNode* const stmtsp = newmodp->stmtsp()) { + stmtsp->unlinkFrBackWithNext(); + m_modp->addStmtp(stmtsp); + } + // Clear any leftover ports, etc + VL_DO_DANGLING(newmodp->deleteTree(), newmodp); + // Remove the cell we just inlined + nodep->unlinkFrBack(); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + } + // VISITORS virtual void visit(AstNetlist* nodep) override { // Iterate modules backwards, in bottom-up order. Required! - iterateChildrenBackwards(nodep); + iterateAndNextConstNullBackwards(nodep->modulesp()); + // Clean up AstIfaceRefDType references + iterateChildren(nodep->typeTablep()); + } + virtual void visit(AstNodeModule* nodep) override { + UASSERT_OBJ(!m_modp, nodep, "Unsupported: Nested modules"); + m_modp = nodep; + // Iterate the stored cells directly to reduce traversal + for (AstCell* const cellp : m_moduleState(nodep).m_childCells) { + if (m_moduleState(cellp->modp()).m_inlined) inlineCell(cellp); + } + m_moduleState(nodep).m_childCells.clear(); + m_modp = nullptr; } virtual void visit(AstIfaceRefDType* nodep) override { if (nodep->user5()) { @@ -518,101 +599,25 @@ private: nodep->cellp(nullptr); } } - virtual void visit(AstNodeModule* nodep) override { - VL_RESTORER(m_modp); - { - m_modp = nodep; - iterateChildren(nodep); - } - } - virtual void visit(AstCell* nodep) override { - if (nodep->modp()->user1()) { // Marked with inline request - UINFO(5, " Inline CELL " << nodep << endl); - UINFO(5, " To MOD " << m_modp << endl); - ++m_statCells; - - // Before cloning simplify pin assignments - // Better off before, as if module has multiple instantiations - // we'll save work, and we can't call pinReconnectSimple in - // this loop as it clone()s itself. - for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { - V3Inst::pinReconnectSimple(pinp, nodep, false); - } - - // Clone original module - if (debug() >= 9) nodep->dumpTree(cout, "inlcell:"); - // if (debug() >= 9) nodep->modp()->dumpTree(cout, "oldmod:"); - AstNodeModule* const newmodp = nodep->modp()->cloneTree(false); - if (debug() >= 9) newmodp->dumpTree(cout, "newmod:"); - // Clear var markings and find cell cross references - AstNode::user2ClearTree(); - AstNode::user4ClearTree(); - { InlineCollectVisitor{nodep->modp()}; } // {} to destroy visitor immediately - // Create data for dotted variable resolution - AstCellInline* const inlinep - = new AstCellInline(nodep->fileline(), nodep->name(), nodep->modp()->origName(), - nodep->modp()->timeunit()); - m_modp->addInlinesp(inlinep); // Must be parsed before any AstCells - // Create assignments to the pins - for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { - if (!pinp->exprp()) continue; - UINFO(6, " Pin change from " << pinp->modVarp() << endl); - // Make new signal; even though we'll optimize the interconnect, we - // need an alias to trace correctly. If tracing is disabled, we'll - // delete it in later optimizations. - AstVar* const pinOldVarp = pinp->modVarp(); - AstVar* const pinNewVarp = pinOldVarp->clonep(); - UASSERT_OBJ(pinNewVarp, pinOldVarp, "Cloning failed"); - - AstNode* const connectRefp = pinp->exprp(); - UASSERT_OBJ( - VN_IS(connectRefp, Const) || VN_IS(connectRefp, VarRef), pinp, - "Unknown interconnect type; pinReconnectSimple should have cleared up"); - V3Inst::checkOutputShort(pinp); - - // Propagate any attributes across the interconnect - pinNewVarp->propagateAttrFrom(pinOldVarp); - if (VN_IS(connectRefp, VarRef)) { - VN_AS(connectRefp, VarRef)->varp()->propagateAttrFrom(pinOldVarp); - } - - // One to one interconnect won't make a temporary variable. - // This prevents creating a lot of extra wires for clock signals. - // It will become a tracing alias. - UINFO(6, "One-to-one " << connectRefp << endl); - UINFO(6, " -to " << pinNewVarp << endl); - pinNewVarp->user2p(connectRefp); - // Public output inside the cell must go via an assign rather - // than alias. Else the public logic will set the alias, losing - // the value to be propagated up (InOnly isn't a problem as the - // AssignAlias will create the assignment for us) - pinNewVarp->user3(pinNewVarp->isSigUserRWPublic() - && pinNewVarp->direction() == VDirection::OUTPUT); - } - // Cleanup var names, etc, to not conflict - { InlineRelinkVisitor{newmodp, m_modp, nodep}; } - // Move statements to top module - if (debug() >= 9) newmodp->dumpTree(cout, "fixmod:"); - AstNode* const stmtsp = newmodp->stmtsp(); - if (stmtsp) stmtsp->unlinkFrBackWithNext(); - if (stmtsp) m_modp->addStmtp(stmtsp); - // Remove the cell - VL_DO_DANGLING(newmodp->deleteTree(), newmodp); // Clear any leftover ports, etc - nodep->unlinkFrBack(); - VL_DO_DANGLING(pushDeletep(nodep), nodep); - if (debug() >= 9) m_modp->dumpTree(cout, "donemod:"); - } - } //-------------------- - virtual void visit(AstNodeMath*) override {} // Accelerate - virtual void visit(AstNodeStmt*) override {} // Accelerate + virtual void visit(AstCell* nodep) override { // LCOV_EXCL_START + nodep->v3fatal("Traversal should have been short circuited"); + } + virtual void visit(AstNodeStmt* nodep) override { + nodep->v3fatal("Traversal should have been short circuited"); + } // LCOV_EXCL_STOP + virtual void visit(AstNodeFile*) override {} // Accelerate + virtual void visit(AstNodeDType*) override {} // Accelerate virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } public: // CONSTRUCTORS - explicit InlineVisitor(AstNode* nodep) { iterate(nodep); } - virtual ~InlineVisitor() override { // + explicit InlineVisitor(AstNode* nodep, ModuleStateUser1Allocator& moduleState) + : m_moduleState{moduleState} { + iterate(nodep); + } + virtual ~InlineVisitor() override { V3Stats::addStat("Optimizations, Inlined instances", m_statCells); } }; @@ -620,11 +625,12 @@ public: //###################################################################### // Track interface references under the Cell they reference -class InlineIntfRefVisitor final : public AstNVisitor { +class InlineIntfRefVisitor final : public VNVisitor { private: // NODE STATE // AstVar::user1p() // AstCell which this Var points to - const AstUser2InUse m_inuser2; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; string m_scope; // Scope name @@ -632,10 +638,7 @@ private: VL_DEBUG_FUNC; // Declare debug() // VISITORS - virtual void visit(AstNetlist* nodep) override { iterateChildren(nodep); } - virtual void visit(AstModule* nodep) override { - if (nodep->isTop()) iterateChildren(nodep); - } + virtual void visit(AstNetlist* nodep) override { iterateChildren(nodep->topModulep()); } virtual void visit(AstCell* nodep) override { VL_RESTORER(m_scope); if (m_scope.empty()) { @@ -708,21 +711,26 @@ public: void V3Inline::inlineAll(AstNetlist* nodep) { UINFO(2, __FUNCTION__ << ": " << endl); - const AstUser1InUse m_inuser1; // output of InlineMarkVisitor, - // input to InlineVisitor. - // Scoped to clean up temp userN's - { InlineMarkVisitor{nodep}; } - { InlineVisitor{nodep}; } - // Remove all modules that were inlined - // V3Dead will also clean them up, but if we have debug on, it's a good - // idea to avoid dumping the hugely exploded tree. - AstNodeModule* nextmodp; - for (AstNodeModule* modp = v3Global.rootp()->modulesp(); modp; modp = nextmodp) { - nextmodp = VN_AS(modp->nextp(), NodeModule); - if (modp->user1()) { // Was inlined - VL_DO_DANGLING(modp->unlinkFrBack()->deleteTree(), modp); + + { + const VNUser1InUse m_inuser1; // output of InlineMarkVisitor, input to InlineVisitor. + ModuleStateUser1Allocator moduleState; // AstUser1Allocator + + // Scoped to clean up temp userN's + { InlineMarkVisitor{nodep, moduleState}; } + + { InlineVisitor{nodep, moduleState}; } + + // Check inlined modules have been removed during traversal. Otherwise we might have blown + // up Verilator memory consumption. + for (AstNodeModule* modp = v3Global.rootp()->modulesp(); modp; + modp = VN_AS(modp->nextp(), NodeModule)) { + UASSERT_OBJ(!moduleState(modp).m_inlined, modp, + "Inlined module should have been deleted when the last cell referencing " + "it was inlined"); } } + { InlineIntfRefVisitor{nodep}; } V3Global::dumpCheckGlobalTree("inline", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); } diff --git a/src/V3Inline.h b/src/V3Inline.h index 495870bc0..0fe1126d5 100644 --- a/src/V3Inline.h +++ b/src/V3Inline.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index b98d56303..cf3906851 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,12 +34,12 @@ //###################################################################### // Inst state, as a visitor of each AstNode -class InstVisitor final : public AstNVisitor { +class InstVisitor final : public VNVisitor { private: // NODE STATE // Cleared each Cell: // AstPin::user1p() -> bool. True if created assignment already - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE AstCell* m_cellp = nullptr; // Current cell @@ -139,7 +139,7 @@ public: //###################################################################### -class InstDeModVarVisitor final : public AstNVisitor { +class InstDeModVarVisitor final : public VNVisitor { // Expand all module variables, and save names for later reference private: // STATE @@ -190,7 +190,7 @@ public: //###################################################################### -class InstDeVisitor final : public AstNVisitor { +class InstDeVisitor final : public VNVisitor { // Find all cells with arrays, and convert to non-arrayed private: // STATE @@ -320,7 +320,7 @@ private: if (!nodep->exprp()) return; // No-connect if (m_cellRangep) { UINFO(4, " PIN " << nodep << endl); - const int pinwidth = nodep->modVarp()->width(); + const int modwidth = nodep->modVarp()->width(); const int expwidth = nodep->exprp()->width(); const std::pair pinDim = nodep->modVarp()->dtypep()->dimensions(false); @@ -328,7 +328,7 @@ private: = nodep->exprp()->dtypep()->dimensions(false); UINFO(4, " PINVAR " << nodep->modVarp() << endl); UINFO(4, " EXP " << nodep->exprp() << endl); - UINFO(4, " pinwidth ew=" << expwidth << " pw=" << pinwidth << " ed=" << expDim.first + UINFO(4, " modwidth ew=" << expwidth << " pw=" << modwidth << " ed=" << expDim.first << "," << expDim.second << " pd=" << pinDim.first << "," << pinDim.second << endl); if (expDim.first == pinDim.first && expDim.second == pinDim.second + 1) { @@ -341,11 +341,11 @@ private: AstNode* exprp = nodep->exprp()->unlinkFrBack(); exprp = new AstArraySel(exprp->fileline(), exprp, arraySelNum); nodep->exprp(exprp); - } else if (expwidth == pinwidth) { + } else if (expwidth == modwidth) { // NOP: Arrayed instants: widths match so connect to each instance - } else if (expwidth == pinwidth * m_cellRangep->elementsConst()) { + } else if (expwidth == modwidth * m_cellRangep->elementsConst()) { // Arrayed instants: one bit for each of the instants (each - // assign is 1 pinwidth wide) + // assign is 1 modwidth wide) if (m_cellRangep->littleEndian()) { nodep->exprp()->v3warn(LITENDIAN, "Little endian instance range connecting to " "vector: left < right of instance range: [" @@ -362,7 +362,7 @@ private: "with output connections to non-wires."); // Note spec allows more complicated matches such as slices and such } - exprp = new AstSel(exprp->fileline(), exprp, pinwidth * m_instSelNum, pinwidth); + exprp = new AstSel(exprp->fileline(), exprp, modwidth * m_instSelNum, modwidth); nodep->exprp(exprp); } else { nodep->v3fatalSrc("Width mismatch; V3Width should have errored out."); @@ -564,7 +564,7 @@ public: // Prevent name conflict if both tri & non-tri add signals + (forTristate ? "t" : "") + "__" + cellp->name() + "__" + pinp->name()); AstVar* const newvarp - = new AstVar(pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp); + = new AstVar(pinVarp->fileline(), VVarType::MODULETEMP, newvarname, pinVarp); // Important to add statement next to cell, in case there is a // generate with same named cell cellp->addNextHere(newvarp); diff --git a/src/V3Inst.h b/src/V3Inst.h index 1b49a9dd0..0e55b8ce1 100644 --- a/src/V3Inst.h +++ b/src/V3Inst.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,10 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstAssignW; +class AstCell; +class AstNetlist; +class AstPin; //============================================================================ diff --git a/src/V3InstrCount.cpp b/src/V3InstrCount.cpp index 750322a2b..a517bee15 100644 --- a/src/V3InstrCount.cpp +++ b/src/V3InstrCount.cpp @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -29,12 +29,12 @@ /// we'll count instructions from either the 'if' or the 'else' branch, /// whichever is larger. We know we won't run both. -class InstrCountVisitor final : public AstNVisitor { +class InstrCountVisitor final : public VNVisitor { private: // NODE STATE // AstNode::user4() -> int. Path cost + 1, 0 means don't dump // AstNode::user5() -> bool. Processed if assertNoDups - const AstUser4InUse m_inuser4; + const VNUser4InUse m_inuser4; // MEMBERS uint32_t m_instrCount = 0; // Running count of instructions @@ -42,7 +42,7 @@ private: bool m_tracingCall = false; // Iterating into a CCall to a CFunc bool m_inCFunc = false; // Inside AstCFunc const bool m_assertNoDups; // Check for duplicates - const std::ostream* m_osp; // Dump file + const std::ostream* const m_osp; // Dump file // TYPES // Little class to cleanly call startVisitBase/endVisitBase @@ -258,13 +258,13 @@ private: }; // Iterate the graph printing the critical path marked by previous visitation -class InstrCountDumpVisitor final : public AstNVisitor { +class InstrCountDumpVisitor final : public VNVisitor { private: // NODE STATE // AstNode::user4() -> int. Path cost, 0 means don't dump // MEMBERS - std::ostream* m_osp; // Dump file + std::ostream* const m_osp; // Dump file unsigned m_depth = 0; // Current tree depth for printing indent public: diff --git a/src/V3InstrCount.h b/src/V3InstrCount.h index b344b33b4..bee916109 100644 --- a/src/V3InstrCount.h +++ b/src/V3InstrCount.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LangCode.h b/src/V3LangCode.h index afad9f30c..5fa1b133e 100644 --- a/src/V3LangCode.h +++ b/src/V3LangCode.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LanguageWords.h b/src/V3LanguageWords.h index c5b19317d..41aaf998d 100644 --- a/src/V3LanguageWords.h +++ b/src/V3LanguageWords.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Life.cpp b/src/V3Life.cpp index 3de19778f..da104adaf 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -41,7 +41,7 @@ class LifeState final { // NODE STATE // See below - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE public: @@ -125,16 +125,15 @@ class LifeBlock final { // For each basic block, we'll make a new map of what variables that if/else is changing using LifeMap = std::unordered_map; LifeMap m_map; // Current active lifetime map for current scope - LifeBlock* m_aboveLifep; // Upper life, or nullptr - LifeState* m_statep; // Current global state + LifeBlock* const m_aboveLifep; // Upper life, or nullptr + LifeState* const m_statep; // Current global state VL_DEBUG_FUNC; // Declare debug() public: - LifeBlock(LifeBlock* aboveLifep, LifeState* statep) { - m_aboveLifep = aboveLifep; // Null if top - m_statep = statep; - } + LifeBlock(LifeBlock* aboveLifep, LifeState* statep) + : m_aboveLifep{aboveLifep} // Null if top + , m_statep{statep} {} ~LifeBlock() = default; // METHODS void checkRemoveAssign(const LifeMap::iterator& it) { @@ -268,10 +267,10 @@ public: //###################################################################### // Life state, as a visitor of each AstNode -class LifeVisitor final : public AstNVisitor { +class LifeVisitor final : public VNVisitor { private: // STATE - LifeState* m_statep; // Current state + LifeState* const m_statep; // Current state bool m_sideEffect = false; // Side effects discovered in assign RHS bool m_noopt = false; // Disable optimization of variables in this block bool m_tracingCall = false; // Iterating into a CCall to a CFunc @@ -433,9 +432,9 @@ private: public: // CONSTRUCTORS - LifeVisitor(AstNode* nodep, LifeState* statep) { + LifeVisitor(AstNode* nodep, LifeState* statep) + : m_statep{statep} { UINFO(4, " LifeVisitor on " << nodep << endl); - m_statep = statep; { m_lifep = new LifeBlock(nullptr, m_statep); iterate(nodep); @@ -450,7 +449,7 @@ public: //###################################################################### -class LifeTopVisitor final : public AstNVisitor { +class LifeTopVisitor final : public VNVisitor { // Visit all top nodes searching for functions that are entry points we want to start // finding code within. private: diff --git a/src/V3Life.h b/src/V3Life.h index b783ee665..7186c3a99 100644 --- a/src/V3Life.h +++ b/src/V3Life.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp index 8d80d8a64..07dbae5a5 100644 --- a/src/V3LifePost.cpp +++ b/src/V3LifePost.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -40,7 +40,7 @@ //###################################################################### // LifePost class functions -class LifePostElimVisitor final : public AstNVisitor { +class LifePostElimVisitor final : public VNVisitor { private: bool m_tracingCall = false; // Iterating into a CCall to a CFunc @@ -128,12 +128,12 @@ struct LifePostLocation { //###################################################################### // LifePost delay elimination -class LifePostDlyVisitor final : public AstNVisitor { +class LifePostDlyVisitor final : public VNVisitor { private: // NODE STATE // Cleared on entire tree // AstVarScope::user4() -> AstVarScope*: Passed to LifePostElim to substitute this var - const AstUser4InUse m_inuser4; + const VNUser4InUse m_inuser4; // STATE uint32_t m_sequence = 0; // Sequence number of assigns/varrefs, diff --git a/src/V3LifePost.h b/src/V3LifePost.h index f36b64c0e..174b0b57b 100644 --- a/src/V3LifePost.h +++ b/src/V3LifePost.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp index d0d7806b3..2645b521e 100644 --- a/src/V3LinkCells.cpp +++ b/src/V3LinkCells.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -91,7 +91,7 @@ void LinkCellsGraph::loopsMessageCb(V3GraphVertex* vertexp) { //###################################################################### // Link state, as a visitor of each AstNode -class LinkCellsVisitor final : public AstNVisitor { +class LinkCellsVisitor final : public VNVisitor { private: // NODE STATE // Entire netlist: @@ -101,11 +101,11 @@ private: // AstCell::user2() // bool clone renaming completed // Allocated across all readFiles in V3Global::readFiles: // AstNode::user4p() // VSymEnt* Package and typedef symbol names - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; // STATE - VInFilter* m_filterp; // Parser filter + VInFilter* const m_filterp; // Parser filter V3ParseSym* m_parseSymp; // Parser symbol table // Below state needs to be preserved between each module call. @@ -123,7 +123,7 @@ private: V3GraphVertex* vertex(AstNodeModule* nodep) { // Return corresponding vertex for this module if (!nodep->user1p()) nodep->user1p(new LinkCellsVertex(&m_graph, nodep)); - return (nodep->user1u().toGraphVertex()); + return nodep->user1u().toGraphVertex(); } AstNodeModule* findModuleSym(const string& modName) { @@ -185,6 +185,9 @@ private: // Module: Pick up modnames, so we can resolve cells later VL_RESTORER(m_modp); { + // For nested modules/classes, child below parent + if (m_modp) new V3GraphEdge{&m_graph, vertex(m_modp), vertex(nodep), 1}; + // m_modp = nodep; UINFO(4, "Link Module: " << nodep << endl); if (nodep->fileline()->filebasenameNoExt() != nodep->prettyName() @@ -431,10 +434,10 @@ private: AstNodeArrayDType* const arrp = new AstUnpackArrayDType(nodep->fileline(), VFlagChildDType(), idtypep, nodep->rangep()->cloneTree(true)); - varp = new AstVar(nodep->fileline(), AstVarType::IFACEREF, varName, + varp = new AstVar(nodep->fileline(), VVarType::IFACEREF, varName, VFlagChildDType(), arrp); } else { - varp = new AstVar(nodep->fileline(), AstVarType::IFACEREF, varName, + varp = new AstVar(nodep->fileline(), VVarType::IFACEREF, varName, VFlagChildDType(), idtypep); } varp->isIfaceParent(true); @@ -449,6 +452,18 @@ private: } virtual void visit(AstRefDType* nodep) override { + iterateChildren(nodep); + for (AstPin* pinp = nodep->paramsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { + pinp->param(true); + if (pinp->name() == "") pinp->name("__paramNumber" + cvtToStr(pinp->pinNum())); + } + } + virtual void visit(AstClassOrPackageRef* nodep) override { + iterateChildren(nodep); + // Inside a class, an extends or reference to another class + // Note we don't add a V3GraphEdge{vertex(m_modp), vertex(nodep->classOrPackagep()} + // We could for an extends, but for another reference we cannot, as + // it is legal to have classes both with parameters that link to each other for (AstPin* pinp = nodep->paramsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { pinp->param(true); if (pinp->name() == "") pinp->name("__paramNumber" + cvtToStr(pinp->pinNum())); @@ -498,9 +513,9 @@ private: public: // CONSTRUCTORS LinkCellsVisitor(AstNetlist* nodep, VInFilter* filterp, V3ParseSym* parseSymp) - : m_mods{nodep} { - m_filterp = filterp; - m_parseSymp = parseSymp; + : m_filterp{filterp} + , m_parseSymp{parseSymp} + , m_mods{nodep} { if (v3Global.opt.hierChild()) { const V3HierBlockOptSet& hierBlocks = v3Global.opt.hierBlocks(); UASSERT(!v3Global.opt.topModule().empty(), diff --git a/src/V3LinkCells.h b/src/V3LinkCells.h index a2c8d5cc1..8e40b7fbc 100644 --- a/src/V3LinkCells.h +++ b/src/V3LinkCells.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,9 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" - +class AstNetlist; class VInFilter; class V3ParseSym; diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 6f81421e9..d8c03df52 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -129,9 +129,9 @@ private: // AstVar::user4() // bool. True if port set for this variable // AstNodeBlock::user4() // bool. Did name processing // AstNodeModule::user4() // bool. Live module - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser4InUse m_inuser4; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser4InUse m_inuser4; public: // ENUMS @@ -147,7 +147,7 @@ private: // MEMBERS VSymGraph m_syms; // Symbol table - VSymEnt* m_dunitEntp; // $unit entry + VSymEnt* m_dunitEntp = nullptr; // $unit entry std::multimap m_nameScopeSymMap; // Map of scope referenced by non-pretty textual name std::set> @@ -204,7 +204,6 @@ public: m_forPrimary = (step == LDS_PRIMARY); m_forPrearray = (step == LDS_PARAMED || step == LDS_PRIMARY); m_forScopeCreation = (step == LDS_SCOPED); - m_dunitEntp = nullptr; s_errorThisp = this; V3Error::errorExitCb(preErrorDumpHandler); // If get error, dump self } @@ -513,8 +512,9 @@ public: if (it2 != m_scopeAliasMap[samn].end()) { srcp = it2->second; continue; - } else + } else { break; + } } UINFO(9, " iiasa: Insert alias se" << lhsp << " (" << lhsp->nodep()->typeName() << ") <- se" << srcp << " " << srcp->nodep() @@ -624,8 +624,9 @@ public: } break; } - } else + } else { break; + } } if (!lookupSymp) return nullptr; // Not found } @@ -707,7 +708,7 @@ LinkDotState* LinkDotState::s_errorThisp = nullptr; //====================================================================== -class LinkDotFindVisitor final : public AstNVisitor { +class LinkDotFindVisitor final : public VNVisitor { // STATE LinkDotState* const m_statep; // State to pass between visitors, including symbol table AstNodeModule* m_classOrPackagep = nullptr; // Current package @@ -941,7 +942,7 @@ class LinkDotFindVisitor final : public AstNVisitor { // places such as tasks, where "task ...; begin ... end" // are common. for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { - if (VN_IS(stmtp, Var)) { + if (VN_IS(stmtp, Var) || VN_IS(stmtp, Foreach)) { ++m_modBlockNum; nodep->name("unnamedblk" + cvtToStr(m_modBlockNum)); break; @@ -1016,10 +1017,10 @@ class LinkDotFindVisitor final : public AstNVisitor { if (dtypep) { dtypep->unlinkFrBack(); } else { - dtypep = new AstBasicDType(nodep->fileline(), AstBasicDTypeKwd::LOGIC); + dtypep = new AstBasicDType(nodep->fileline(), VBasicDTypeKwd::LOGIC); } AstVar* const newvarp - = new AstVar(nodep->fileline(), AstVarType::VAR, nodep->name(), + = new AstVar(nodep->fileline(), VVarType::VAR, nodep->name(), VFlagChildDType(), dtypep); // Not dtype resolved yet newvarp->direction(VDirection::OUTPUT); newvarp->lifetime(VLifetime::AUTOMATIC); @@ -1042,8 +1043,6 @@ class LinkDotFindVisitor final : public AstNVisitor { iterateChildren(nodep); if (nodep->isFuncLocal() && nodep->lifetime().isStatic()) { nodep->v3warn(E_UNSUPPORTED, "Unsupported: 'static' function/task variables"); - } else if (nodep->isClassMember() && nodep->lifetime().isStatic()) { - nodep->v3warn(E_UNSUPPORTED, "Unsupported: 'static' class members"); } if (!m_statep->forScopeCreation()) { // Find under either a task or the module's vars @@ -1093,6 +1092,10 @@ class LinkDotFindVisitor final : public AstNVisitor { } else { findvarp->combineType(nodep); findvarp->fileline()->modifyStateInherit(nodep->fileline()); + if (nodep->getChildDTypep()->numeric().isSigned() + && !findvarp->getChildDTypep()->numeric().isSigned()) { + findvarp->getChildDTypep()->numeric(VSigning(true)); + } AstBasicDType* const bdtypep = VN_CAST(findvarp->childDTypep(), BasicDType); if (bdtypep && bdtypep->implicit()) { @@ -1127,14 +1130,14 @@ class LinkDotFindVisitor final : public AstNVisitor { } if (ins) { if (m_statep->forPrimary() && nodep->isGParam() + && VN_IS(m_modSymp->nodep(), Module) && (m_statep->rootEntp()->nodep() == m_modSymp->parentp()->nodep())) { // This is the toplevel module. Check for command line overwrites of parameters // We first search if the parameter is overwritten and then replace it with a // new value. It will keep the same FileLine information. if (v3Global.opt.hasParameter(nodep->name())) { - AstVar* const newp - = new AstVar(nodep->fileline(), AstVarType(AstVarType::GPARAM), - nodep->name(), nodep); + AstVar* const newp = new AstVar( + nodep->fileline(), VVarType(VVarType::GPARAM), nodep->name(), nodep); newp->combineType(nodep); const string svalue = v3Global.opt.parameter(nodep->name()); if (AstNode* const valuep @@ -1269,6 +1272,58 @@ class LinkDotFindVisitor final : public AstNVisitor { m_curSymp->exportStarStar(m_statep->symsp()); // No longer needed, but can't delete until any multi-instantiated modules are expanded } + + virtual void visit(AstForeach* nodep) override { + // Symbol table needs nodep->name() as the index variable's name + VL_RESTORER(m_curSymp); + VSymEnt* const oldCurSymp = m_curSymp; + { + ++m_modWithNum; + m_curSymp = m_statep->insertBlock(m_curSymp, "__Vforeach" + cvtToStr(m_modWithNum), + nodep, m_classOrPackagep); + m_curSymp->fallbackp(oldCurSymp); + // DOT(x, SELLOOPVARS(var, loops)) -> SELLOOPVARS(DOT(x, var), loops) + if (AstDot* const dotp = VN_CAST(nodep->arrayp(), Dot)) { + if (AstSelLoopVars* const loopvarsp = VN_CAST(dotp->rhsp(), SelLoopVars)) { + AstNode* const fromp = loopvarsp->fromp()->unlinkFrBack(); + loopvarsp->unlinkFrBack(); + dotp->replaceWith(loopvarsp); + dotp->rhsp(fromp); + loopvarsp->fromp(dotp); + } + } + const auto loopvarsp = VN_CAST(nodep->arrayp(), SelLoopVars); + if (!loopvarsp) { + AstNode* const warnp = nodep->arrayp() ? nodep->arrayp() : nodep; + warnp->v3warn(E_UNSUPPORTED, + "Unsupported (or syntax error): Foreach on this array's construct"); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + return; + } + for (AstNode *nextp, *argp = loopvarsp->elementsp(); argp; argp = nextp) { + nextp = argp->nextp(); + AstVar* argrefp = nullptr; + if (const auto parserefp = VN_CAST(argp, ParseRef)) { + // We use an int type, this might get changed in V3Width when types resolve + argrefp = new AstVar{parserefp->fileline(), VVarType::BLOCKTEMP, + parserefp->name(), argp->findSigned32DType()}; + parserefp->replaceWith(argrefp); + VL_DO_DANGLING(parserefp->deleteTree(), parserefp); + // Insert argref's name into symbol table + m_statep->insertSym(m_curSymp, argrefp->name(), argrefp, nullptr); + } else if (const auto largrefp = VN_CAST(argp, Var)) { + argrefp = largrefp; + // Insert argref's name into symbol table + m_statep->insertSym(m_curSymp, argrefp->name(), argrefp, nullptr); + } else if (VN_IS(argp, Empty)) { + } else { + argp->v3error("'foreach' loop variable expects simple variable name"); + } + } + iterateChildren(nodep); + } + } + virtual void visit(AstWithParse* nodep) override { // Change WITHPARSE(FUNCREF, equation) to FUNCREF(WITH(equation)) const auto funcrefp = VN_AS(nodep->funcrefp(), NodeFTaskRef); @@ -1330,7 +1385,7 @@ public: //====================================================================== -class LinkDotParamVisitor final : public AstNVisitor { +class LinkDotParamVisitor final : public VNVisitor { private: // NODE STATE // Cleared on global @@ -1414,8 +1469,8 @@ private: -1, // Pin# not relevant nodep->name(), exprp); cellp->addParamsp(pinp); - VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } virtual void visit(AstPort* nodep) override { // Port: Stash the pin number @@ -1522,7 +1577,7 @@ public: //====================================================================== -class LinkDotScopeVisitor final : public AstNVisitor { +class LinkDotScopeVisitor final : public VNVisitor { // STATE LinkDotState* const m_statep; // State to pass between visitors, including symbol table @@ -1592,6 +1647,11 @@ class LinkDotScopeVisitor final : public AstNVisitor { symp->fallbackp(m_modSymp); // No recursion, we don't want to pick up variables } + virtual void visit(AstForeach* nodep) override { + VSymEnt* const symp = m_statep->insertBlock(m_modSymp, nodep->name(), nodep, nullptr); + symp->fallbackp(m_modSymp); + // No recursion, we don't want to pick up variables + } virtual void visit(AstWith* nodep) override { VSymEnt* const symp = m_statep->insertBlock(m_modSymp, nodep->name(), nodep, nullptr); symp->fallbackp(m_modSymp); @@ -1684,9 +1744,9 @@ public: //====================================================================== // Iterate an interface to resolve modports -class LinkDotIfaceVisitor final : public AstNVisitor { +class LinkDotIfaceVisitor final : public VNVisitor { // STATE - LinkDotState* m_statep; // State to pass between visitors, including symbol table + LinkDotState* const m_statep; // State to pass between visitors, including symbol table VSymEnt* m_curSymp; // Symbol Entry for current table, where to lookup/insert // METHODS @@ -1757,10 +1817,10 @@ class LinkDotIfaceVisitor final : public AstNVisitor { public: // CONSTRUCTORS - LinkDotIfaceVisitor(AstIface* nodep, VSymEnt* curSymp, LinkDotState* statep) { + LinkDotIfaceVisitor(AstIface* nodep, VSymEnt* curSymp, LinkDotState* statep) + : m_statep{statep} + , m_curSymp{curSymp} { UINFO(4, __FUNCTION__ << ": " << endl); - m_curSymp = curSymp; - m_statep = statep; iterate(nodep); } virtual ~LinkDotIfaceVisitor() override = default; @@ -1777,7 +1837,7 @@ void LinkDotState::computeIfaceModSyms() { //====================================================================== -class LinkDotResolveVisitor final : public AstNVisitor { +class LinkDotResolveVisitor final : public VNVisitor { private: // NODE STATE // Cleared on global @@ -1787,8 +1847,8 @@ private: // *::user4() -> See LinkDotState // Cleared on Cell // AstVar::user5() // bool. True if pin used in this cell - const AstUser3InUse m_inuser3; - const AstUser5InUse m_inuser5; + const VNUser3InUse m_inuser3; + const VNUser5InUse m_inuser5; // TYPES enum DotPosition : uint8_t { @@ -1806,7 +1866,7 @@ private: VSymEnt* m_pinSymp = nullptr; // SymEnt for pin lookups const AstCell* m_cellp = nullptr; // Current cell AstNodeModule* m_modp = nullptr; // Current module - const AstNodeFTask* m_ftaskp = nullptr; // Current function/task + AstNodeFTask* m_ftaskp = nullptr; // Current function/task int m_modportNum = 0; // Uniqueify modport numbers struct DotStates { @@ -1867,7 +1927,7 @@ private: << (suggest.empty() ? "" : nodep->warnMore() + suggest)); } } - AstVar* const newp = new AstVar(nodep->fileline(), AstVarType::WIRE, nodep->name(), + AstVar* const newp = new AstVar(nodep->fileline(), VVarType::WIRE, nodep->name(), VFlagLogicPacked(), 1); newp->trace(modp->modTrace()); nodep->varp(newp); @@ -2057,8 +2117,9 @@ private: // Legal under a DOT: AstDot, AstParseRef, AstPackageRef, AstNodeSel // also a DOT can be part of an expression, but only above plus // AstFTaskRef are legal children - // DOT(PACKAGEREF, PARSEREF(text)) - // DOT(DOT(DOT(PARSEREF(text), ... + // Dot(PackageRef, ParseRef(text)) + // Dot(Dot(ClassOrPackageRef,ClassOrPackageRef), ParseRef(text)) + // Dot(Dot(Dot(ParseRef(text), ... if (nodep->user3SetOnce()) return; UINFO(8, " " << nodep << endl); const DotStates lastStates = m_ds; @@ -2454,6 +2515,16 @@ private: } if (start) m_ds = lastStates; } + virtual void visit(AstClassOrPackageRef* nodep) override { + UINFO(9, " linkClassOrPackageRef " << m_ds.ascii() << " n=" << nodep << endl); + if (m_ds.m_dotPos == DP_PACKAGE) { + // Already under dot, so this is {ClassOrPackage} Dot {ClassOrPackage} + // m_ds.m_dotText communicates the cell prefix between stages + m_ds.m_dotPos = DP_PACKAGE; + } + // TODO we don't iterate pins yet, as class parameters are not supported + } + virtual void visit(AstVarRef* nodep) override { // VarRef: Resolve its reference // ParseRefs are used the first pass (forPrimary) so we shouldn't get can't find @@ -2683,8 +2754,11 @@ private: if (foundp) { if (VN_IS(foundp->nodep(), Var) && m_ds.m_dotText == "" && m_ftaskp && m_ftaskp->name() == foundp->nodep()->name()) { - nodep->v3warn(E_UNSUPPORTED, "Unsupported: Recursive function call " - << nodep->prettyNameQ()); + // This is a recursive reference to the function itself, not to the var + nodep->taskp(m_ftaskp); + nodep->classOrPackagep(foundp->classOrPackagep()); + UINFO(7, " Resolved recursive " << nodep + << endl); // Also prints taskp } else { nodep->v3error("Found definition of '" << m_ds.m_dotText << (m_ds.m_dotText == "" ? "" : ".") @@ -2833,6 +2907,16 @@ private: m_ds.m_dotSymp = m_curSymp = oldCurSymp; m_ftaskp = nullptr; } + virtual void visit(AstForeach* nodep) override { + UINFO(5, " " << nodep << endl); + checkNoDot(nodep); + VSymEnt* const oldCurSymp = m_curSymp; + { + m_ds.m_dotSymp = m_curSymp = m_statep->getNodeSym(nodep); + iterateChildren(nodep); + } + m_ds.m_dotSymp = m_curSymp = oldCurSymp; + } virtual void visit(AstWith* nodep) override { UINFO(5, " " << nodep << endl); checkNoDot(nodep); diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h index 98656689e..08c4bc2ec 100644 --- a/src/V3LinkDot.h +++ b/src/V3LinkDot.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp index b27eaac91..f21764919 100644 --- a/src/V3LinkInc.cpp +++ b/src/V3LinkInc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -47,7 +47,7 @@ //###################################################################### -class LinkIncVisitor final : public AstNVisitor { +class LinkIncVisitor final : public VNVisitor { private: // TYPES enum InsertMode : uint8_t { @@ -62,6 +62,9 @@ private: AstNode* m_insStmtp = nullptr; // Where to insert statement bool m_unsupportedHere = false; // Used to detect where it's not supported yet + // METHODS + VL_DEBUG_FUNC; // Declare debug() + void insertBeforeStmt(AstNode* nodep, AstNode* newp) { // Return node that must be visited, if any // See also AstNode::addBeforeStmt; this predates that function @@ -86,7 +89,7 @@ private: // VISITORS virtual void visit(AstNodeModule* nodep) override { - // Reset increments count + VL_RESTORER(m_modIncrementsNum); m_modIncrementsNum = 0; iterateChildren(nodep); } @@ -107,6 +110,22 @@ private: // Done the loop m_insStmtp = nullptr; // Next thing should be new statement } + virtual void visit(AstForeach* nodep) override { + // Special, as statements need to be put in different places + // Body insert just before themselves + m_insStmtp = nullptr; // First thing should be new statement + iterateChildren(nodep); + // Done the loop + m_insStmtp = nullptr; // Next thing should be new statement + } + virtual void visit(AstJumpBlock* nodep) override { + // Special, as statements need to be put in different places + // Body insert just before themselves + m_insStmtp = nullptr; // First thing should be new statement + iterateChildren(nodep); + // Done the loop + m_insStmtp = nullptr; // Next thing should be new statement + } virtual void visit(AstNodeIf* nodep) override { m_insStmtp = nodep; iterateAndNextNull(nodep->condp()); @@ -115,6 +134,16 @@ private: iterateAndNextNull(nodep->elsesp()); m_insStmtp = nullptr; } + virtual void visit(AstCaseItem* nodep) override { + m_insMode = IM_BEFORE; + { + VL_RESTORER(m_unsupportedHere); + m_unsupportedHere = true; + iterateAndNextNull(nodep->condsp()); + } + m_insStmtp = nullptr; // Next thing should be new statement + iterateAndNextNull(nodep->bodysp()); + } virtual void visit(AstNodeFor* nodep) override { // LCOV_EXCL_LINE nodep->v3fatalSrc( "For statements should have been converted to while statements in V3Begin.cpp"); @@ -130,10 +159,10 @@ private: m_insStmtp = nullptr; // Next thing should be new statement } void unsupported_visit(AstNode* nodep) { + VL_RESTORER(m_unsupportedHere); m_unsupportedHere = true; UINFO(9, "Marking unsupported " << nodep << endl); iterateChildren(nodep); - m_unsupportedHere = false; } virtual void visit(AstLogAnd* nodep) override { unsupported_visit(nodep); } virtual void visit(AstLogOr* nodep) override { unsupported_visit(nodep); } @@ -189,7 +218,7 @@ private: // Prepare a temporary variable FileLine* const fl = backp->fileline(); const string name = string("__Vincrement") + cvtToStr(++m_modIncrementsNum); - AstVar* const varp = new AstVar(fl, AstVarType::BLOCKTEMP, name, VFlagChildDType(), + AstVar* const varp = new AstVar(fl, VVarType::BLOCKTEMP, name, VFlagChildDType(), varrefp->varp()->subDTypep()->cloneTree(true)); // Declare the variable @@ -246,5 +275,5 @@ public: void V3LinkInc::linkIncrements(AstNetlist* nodep) { UINFO(2, __FUNCTION__ << ": " << endl); { LinkIncVisitor{nodep}; } // Destruct before checking - V3Global::dumpCheckGlobalTree("linkInc", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); + V3Global::dumpCheckGlobalTree("linkinc", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); } diff --git a/src/V3LinkInc.h b/src/V3LinkInc.h index 3348e9961..835bddd51 100644 --- a/src/V3LinkInc.h +++ b/src/V3LinkInc.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index 2e11f72c4..c46f2f82a 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -41,12 +41,12 @@ //###################################################################### -class LinkJumpVisitor final : public AstNVisitor { +class LinkJumpVisitor final : public VNVisitor { private: // STATE AstNodeModule* m_modp = nullptr; // Current module AstNodeFTask* m_ftaskp = nullptr; // Current function/task - AstWhile* m_loopp = nullptr; // Current loop + AstNode* m_loopp = nullptr; // Current loop bool m_loopInc = false; // In loop increment bool m_inFork = false; // Under fork int m_modRepeatNum = 0; // Repeat counter @@ -66,6 +66,13 @@ private: underp = VN_AS(nodep, NodeBlock)->stmtsp(); } else if (VN_IS(nodep, NodeFTask)) { underp = VN_AS(nodep, NodeFTask)->stmtsp(); + } else if (VN_IS(nodep, Foreach)) { + if (endOfIter) { + underp = VN_AS(nodep, Foreach)->bodysp(); + } else { + underp = nodep; + under_and_next = false; // IE we skip the entire foreach + } } else if (VN_IS(nodep, While)) { if (endOfIter) { // Note we jump to end of bodysp; a FOR loop has its @@ -93,7 +100,7 @@ private: AstJumpLabel* const labelp = new AstJumpLabel(nodep->fileline(), blockp); blockp->labelp(labelp); - AstNRelinker repHandle; + VNRelinker repHandle; if (under_and_next) { underp->unlinkFrBackWithNext(&repHandle); } else { @@ -146,8 +153,8 @@ private: AstNode* const countp = nodep->countp()->unlinkFrBackWithNext(); const string name = string("__Vrepeat") + cvtToStr(m_modRepeatNum++); // Spec says value is integral, if negative is ignored - AstVar* const varp = new AstVar(nodep->fileline(), AstVarType::BLOCKTEMP, name, - nodep->findSigned32DType()); + AstVar* const varp + = new AstVar(nodep->fileline(), VVarType::BLOCKTEMP, name, nodep->findSigned32DType()); varp->usedLoopIdx(true); m_modp->addStmtp(varp); AstNode* initsp = new AstAssign( @@ -192,6 +199,13 @@ private: iterateAndNextNull(nodep->incsp()); } } + virtual void visit(AstForeach* nodep) override { + VL_RESTORER(m_loopp); + { + m_loopp = nodep; + iterateAndNextNull(nodep->bodysp()); + } + } virtual void visit(AstReturn* nodep) override { iterateChildren(nodep); const AstFunc* const funcp = VN_CAST(m_ftaskp, Func); @@ -288,5 +302,5 @@ public: void V3LinkJump::linkJump(AstNetlist* nodep) { UINFO(2, __FUNCTION__ << ": " << endl); { LinkJumpVisitor{nodep}; } // Destruct before checking - V3Global::dumpCheckGlobalTree("link", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); + V3Global::dumpCheckGlobalTree("linkjump", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); } diff --git a/src/V3LinkJump.h b/src/V3LinkJump.h index c64a68f76..e2cc25ac7 100644 --- a/src/V3LinkJump.h +++ b/src/V3LinkJump.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3LinkLValue.cpp b/src/V3LinkLValue.cpp index 05f546502..6ab7eb8e7 100644 --- a/src/V3LinkLValue.cpp +++ b/src/V3LinkLValue.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,11 +30,12 @@ //###################################################################### // Link state, as a visitor of each AstNode -class LinkLValueVisitor final : public AstNVisitor { +class LinkLValueVisitor final : public VNVisitor { private: // NODE STATE // STATE + bool m_setContinuously = false; // Set that var has some continuous assignment VAccess m_setRefLvalue; // Set VarRefs to lvalues for pin assignments AstNodeFTask* m_ftaskp = nullptr; // Function or task we're inside @@ -47,6 +48,9 @@ private: // VarRef: LValue its reference if (m_setRefLvalue != VAccess::NOCHANGE) nodep->access(m_setRefLvalue); if (nodep->varp()) { + if (nodep->access().isWriteOrRW() && m_setContinuously) { + nodep->varp()->isContinuously(true); + } if (nodep->access().isWriteOrRW() && !m_ftaskp && nodep->varp()->isReadOnly()) { nodep->v3warn(ASSIGNIN, "Assigning to input/const variable: " << nodep->prettyNameQ()); @@ -69,13 +73,25 @@ private: } virtual void visit(AstNodeAssign* nodep) override { VL_RESTORER(m_setRefLvalue); + VL_RESTORER(m_setContinuously); { m_setRefLvalue = VAccess::WRITE; + m_setContinuously = VN_IS(nodep, AssignW) || VN_IS(nodep, AssignAlias); iterateAndNextNull(nodep->lhsp()); m_setRefLvalue = VAccess::NOCHANGE; + m_setContinuously = false; iterateAndNextNull(nodep->rhsp()); } } + virtual void visit(AstRelease* nodep) override { + VL_RESTORER(m_setRefLvalue); + VL_RESTORER(m_setContinuously); + { + m_setRefLvalue = VAccess::WRITE; + m_setContinuously = false; + iterateAndNextNull(nodep->lhsp()); + } + } virtual void visit(AstCastDynamic* nodep) override { VL_RESTORER(m_setRefLvalue); { @@ -176,6 +192,13 @@ private: VL_RESTORER(m_setRefLvalue); iterateChildren(nodep); } + virtual void visit(AstRand* nodep) override { + VL_RESTORER(m_setRefLvalue); + { + if (!nodep->urandom()) m_setRefLvalue = VAccess::WRITE; + iterateAndNextNull(nodep->seedp()); + } + } virtual void visit(AstReadMem* nodep) override { VL_RESTORER(m_setRefLvalue); { diff --git a/src/V3LinkLValue.h b/src/V3LinkLValue.h index 41e43e428..d9e4d78d9 100644 --- a/src/V3LinkLValue.h +++ b/src/V3LinkLValue.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,8 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; +class AstNode; //============================================================================ diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index d0d344908..be8706477 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkLevel.h b/src/V3LinkLevel.h index 9c42e6700..49e56254b 100644 --- a/src/V3LinkLevel.h +++ b/src/V3LinkLevel.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -23,6 +23,8 @@ #include "V3Error.h" #include "V3Ast.h" +#include + //============================================================================ class V3LinkLevel final { diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 45ffd1aec..b99b8e3a9 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,14 +34,14 @@ //###################################################################### // Link state, as a visitor of each AstNode -class LinkParseVisitor final : public AstNVisitor { +class LinkParseVisitor final : public VNVisitor { private: // NODE STATE // Cleared on netlist // AstNode::user1() -> bool. True if processed // AstNode::user2() -> bool. True if fileline recomputed - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; // TYPES using ImplTypedefMap = std::map, AstTypedef*>; @@ -232,11 +232,11 @@ private: if (v3Global.opt.publicFlatRW()) { switch (nodep->varType()) { - case AstVarType::VAR: // FALLTHRU - case AstVarType::GPARAM: // FALLTHRU - case AstVarType::LPARAM: // FALLTHRU - case AstVarType::PORT: // FALLTHRU - case AstVarType::WIRE: nodep->sigUserRWPublic(true); break; + case VVarType::VAR: // FALLTHRU + case VVarType::GPARAM: // FALLTHRU + case VVarType::LPARAM: // FALLTHRU + case VVarType::PORT: // FALLTHRU + case VVarType::WIRE: nodep->sigUserRWPublic(true); break; default: break; } } @@ -272,7 +272,11 @@ private: auto* const assp = new AstAssign(newfl, new AstVarRef(newfl, nodep->name(), VAccess::WRITE), nodep->valuep()->unlinkFrBack()); - nodep->addNextHere(new AstInitial(newfl, assp)); + if (nodep->lifetime().isAutomatic()) { + nodep->addNextHere(new AstInitialAutomatic{newfl, assp}); + } else { + nodep->addNextHere(new AstInitial{newfl, assp}); + } } // 4. Under blocks, it's an initial value to be under an assign else { nodep->addNextHere(new AstAssign(fl, @@ -294,41 +298,46 @@ private: virtual void visit(AstAttrOf* nodep) override { cleanFileline(nodep); iterateChildren(nodep); - if (nodep->attrType() == AstAttrType::DT_PUBLIC) { + if (nodep->attrType() == VAttrType::DT_PUBLIC) { AstTypedef* const typep = VN_AS(nodep->backp(), Typedef); UASSERT_OBJ(typep, nodep, "Attribute not attached to typedef"); typep->attrPublic(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_CLOCK_ENABLE) { + } else if (nodep->attrType() == VAttrType::VAR_CLOCK_ENABLE) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->attrClockEn(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_PUBLIC) { + } else if (nodep->attrType() == VAttrType::VAR_FORCEABLE) { + UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); + m_varp->setForceable(); + v3Global.setHasForceableSignals(); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + } else if (nodep->attrType() == VAttrType::VAR_PUBLIC) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->sigUserRWPublic(true); m_varp->sigModPublic(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_PUBLIC_FLAT) { + } else if (nodep->attrType() == VAttrType::VAR_PUBLIC_FLAT) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->sigUserRWPublic(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_PUBLIC_FLAT_RD) { + } else if (nodep->attrType() == VAttrType::VAR_PUBLIC_FLAT_RD) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->sigUserRdPublic(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_PUBLIC_FLAT_RW) { + } else if (nodep->attrType() == VAttrType::VAR_PUBLIC_FLAT_RW) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->sigUserRWPublic(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_ISOLATE_ASSIGNMENTS) { + } else if (nodep->attrType() == VAttrType::VAR_ISOLATE_ASSIGNMENTS) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->attrIsolateAssign(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_SFORMAT) { + } else if (nodep->attrType() == VAttrType::VAR_SFORMAT) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->attrSFormat(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_SPLIT_VAR) { + } else if (nodep->attrType() == VAttrType::VAR_SPLIT_VAR) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); if (!VN_IS(m_modp, Module)) { m_varp->v3warn( @@ -340,15 +349,15 @@ private: m_varp->attrSplitVar(true); } VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_SC_BV) { + } else if (nodep->attrType() == VAttrType::VAR_SC_BV) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->attrScBv(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_CLOCKER) { + } else if (nodep->attrType() == VAttrType::VAR_CLOCKER) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->attrClocker(VVarAttrClocker::CLOCKER_YES); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } else if (nodep->attrType() == AstAttrType::VAR_NO_CLOCKER) { + } else if (nodep->attrType() == VAttrType::VAR_NO_CLOCKER) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->attrClocker(VVarAttrClocker::CLOCKER_NO); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); @@ -413,13 +422,8 @@ private: } virtual void visit(AstForeach* nodep) override { - // FOREACH(array,loopvars,body) - // -> BEGIN(declare vars, loopa=lowest; WHILE(loopa<=highest, ... body)) - // nodep->dumpTree(cout, "-foreach-old:"); + // FOREACH(array, loopvars, body) UINFO(9, "FOREACH " << nodep << endl); - // nodep->dumpTree(cout, "-foreach-in:"); - AstNode* newp = nodep->bodysp(); - if (newp) newp->unlinkFrBackWithNext(); // Separate iteration vars from base from variable // Input: // v--- arrayp @@ -433,81 +437,23 @@ private: // 3. ASTSELLOOPVARS(first, var0..var1)) // 4. DOT(DOT(first, second), ASTSELBIT(third, var0)) AstNode* bracketp = nodep->arrayp(); - AstNode* firstVarsp = nullptr; - while (AstDot* dotp = VN_CAST(bracketp, Dot)) { bracketp = dotp->rhsp(); } + while (AstDot* dotp = VN_CAST(bracketp, Dot)) bracketp = dotp->rhsp(); if (AstSelBit* const selp = VN_CAST(bracketp, SelBit)) { - firstVarsp = selp->rhsp()->unlinkFrBackWithNext(); - selp->replaceWith(selp->fromp()->unlinkFrBack()); + // Convert to AstSelLoopVars so V3LinkDot knows what's being defined + AstNode* const newp + = new AstSelLoopVars{selp->fileline(), selp->fromp()->unlinkFrBack(), + selp->rhsp()->unlinkFrBackWithNext()}; + selp->replaceWith(newp); VL_DO_DANGLING(selp->deleteTree(), selp); } else if (AstSelLoopVars* const selp = VN_CAST(bracketp, SelLoopVars)) { - firstVarsp = selp->elementsp()->unlinkFrBackWithNext(); - selp->replaceWith(selp->fromp()->unlinkFrBack()); - VL_DO_DANGLING(selp->deleteTree(), selp); + // Ok } else { nodep->v3error( - "Syntax error; foreach missing bracketed index variable (IEEE 1800-2017 12.7.3)"); + "Syntax error; foreach missing bracketed loop variable (IEEE 1800-2017 12.7.3)"); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); return; } - AstNode* const arrayp = nodep->arrayp(); // Maybe different node since bracketp looked - if (!VN_IS(arrayp, ParseRef) && !VN_IS(arrayp, Dot)) { - // Code below needs to use other then attributes to figure out the bounds - // Also need to deal with queues, etc - arrayp->v3warn(E_UNSUPPORTED, "Unsupported: foreach on non-simple variable reference"); - VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - return; - } - // Split into for loop - // Must do innermost (last) variable first - int dimension = 1; - AstNode* lastVarsp = firstVarsp; - while (lastVarsp->nextp()) { - lastVarsp = lastVarsp->nextp(); - dimension++; - } - for (AstNode* varsp = lastVarsp; varsp; varsp = varsp->backp()) { - UINFO(9, "foreachVar " << varsp << endl); - FileLine* const fl = varsp->fileline(); - AstNode* const varp - = new AstVar(fl, AstVarType::BLOCKTEMP, varsp->name(), nodep->findSigned32DType()); - // These will be the left and right dimensions and size of the array: - AstNode* const leftp = new AstAttrOf( - fl, AstAttrType::DIM_LEFT, arrayp->cloneTree(false), new AstConst(fl, dimension)); - AstNode* const rightp = new AstAttrOf( - fl, AstAttrType::DIM_RIGHT, arrayp->cloneTree(false), new AstConst(fl, dimension)); - AstNode* const sizep = new AstAttrOf( - fl, AstAttrType::DIM_SIZE, arrayp->cloneTree(false), new AstConst(fl, dimension)); - AstNode* const stmtsp = varp; - // Assign left-dimension into the loop var: - stmtsp->addNext( - new AstAssign(fl, new AstVarRef(fl, varp->name(), VAccess::WRITE), leftp)); - // This will turn into a constant bool for static arrays - AstNode* const notemptyp = new AstGt(fl, sizep, new AstConst(fl, 0)); - // This will turn into a bool constant, indicating whether - // we count the loop variable up or down: - AstNode* const countupp - = new AstLte(fl, leftp->cloneTree(true), rightp->cloneTree(true)); - AstNode* const comparep = new AstCond( - fl, countupp->cloneTree(true), - // Left increments up to right - new AstLte(fl, new AstVarRef(fl, varp->name(), VAccess::READ), - rightp->cloneTree(true)), - // Left decrements down to right - new AstGte(fl, new AstVarRef(fl, varp->name(), VAccess::READ), rightp)); - // This will reduce to comparep for static arrays - AstNode* const condp = new AstAnd(fl, notemptyp, comparep); - AstNode* const incp = new AstAssign( - fl, new AstVarRef(fl, varp->name(), VAccess::WRITE), - new AstAdd(fl, new AstVarRef(fl, varp->name(), VAccess::READ), - new AstCond(fl, countupp, new AstConst(fl, 1), new AstConst(fl, -1)))); - stmtsp->addNext(new AstWhile(fl, condp, newp, incp)); - newp = new AstBegin(nodep->fileline(), "", stmtsp, false, true); - dimension--; - } - // newp->dumpTree(cout, "-foreach-new:"); - VL_DO_DANGLING(firstVarsp->deleteTree(), firstVarsp); - nodep->replaceWith(newp); - VL_DO_DANGLING(nodep->deleteTree(), nodep); + iterateChildren(nodep); } virtual void visit(AstNodeModule* nodep) override { diff --git a/src/V3LinkParse.h b/src/V3LinkParse.h index 1d68d3d3e..f428fb935 100644 --- a/src/V3LinkParse.h +++ b/src/V3LinkParse.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index 434baf566..a0d198bc7 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -38,12 +38,12 @@ //###################################################################### // Link state, as a visitor of each AstNode -class LinkResolveVisitor final : public AstNVisitor { +class LinkResolveVisitor final : public VNVisitor { private: // NODE STATE // Entire netlist: // AstCaseItem::user2() // bool Moved default caseitems - const AstUser2InUse m_inuser2; + const VNUser2InUse m_inuser2; // STATE // Below state needs to be preserved between each module call. @@ -80,7 +80,7 @@ private: iterateChildren(nodep); } } - virtual void visit(AstInitial* nodep) override { + virtual void visit(AstInitialAutomatic* nodep) override { iterateChildren(nodep); // Initial assignments under function/tasks can just be simple // assignments without the initial @@ -96,7 +96,7 @@ private: } virtual void visit(AstVar* nodep) override { iterateChildren(nodep); - if (m_classp && !nodep->isParam()) nodep->varType(AstVarType::MEMBER); + if (m_classp && !nodep->isParam()) nodep->varType(VVarType::MEMBER); if (m_ftaskp) nodep->funcLocal(true); if (nodep->isSigModPublic()) { nodep->sigModPublic(false); // We're done with this attribute @@ -156,7 +156,7 @@ private: if (sensp && !VN_IS(sensp, NodeVarRef) && !VN_IS(sensp, Const)) { // Make a new temp wire const string newvarname = "__Vsenitemexpr" + cvtToStr(++m_senitemCvtNum); - AstVar* const newvarp = new AstVar(sensp->fileline(), AstVarType::MODULETEMP, + AstVar* const newvarp = new AstVar(sensp->fileline(), VVarType::MODULETEMP, newvarname, VFlagLogicPacked(), 1); // We can't just add under the module, because we may be // inside a generate, begin, etc. @@ -223,20 +223,20 @@ private: AstNode* const basefromp = AstArraySel::baseFromp(nodep, false); if (AstNodeVarRef* const varrefp = VN_CAST(basefromp, NodeVarRef)) { // Maybe varxref - so need to clone - nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::VAR_BASE, + nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::VAR_BASE, varrefp->cloneTree(false))); } else if (AstUnlinkedRef* const uvxrp = VN_CAST(basefromp, UnlinkedRef)) { // Maybe unlinked - so need to clone - nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::VAR_BASE, + nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::VAR_BASE, uvxrp->cloneTree(false))); } else if (auto* const fromp = VN_CAST(basefromp, LambdaArgRef)) { - nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::VAR_BASE, + nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::VAR_BASE, fromp->cloneTree(false))); } else if (AstMemberSel* const fromp = VN_CAST(basefromp, MemberSel)) { - nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::MEMBER_BASE, + nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::MEMBER_BASE, fromp->cloneTree(false))); } else if (AstEnumItemRef* const fromp = VN_CAST(basefromp, EnumItemRef)) { - nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::ENUM_BASE, + nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::ENUM_BASE, fromp->cloneTree(false))); } else if (VN_IS(basefromp, Replicate)) { // From {...}[...] syntax in IEEE 2017 @@ -261,7 +261,7 @@ private: } virtual void visit(AstPragma* nodep) override { - if (nodep->pragType() == AstPragmaType::HIER_BLOCK) { + if (nodep->pragType() == VPragmaType::HIER_BLOCK) { UASSERT_OBJ(m_modp, nodep, "HIER_BLOCK not under a module"); // If this is hierarchical mode which is to lib-create, // sub modules do not have hier_block meta comment in the source code. @@ -271,18 +271,18 @@ private: m_modp->hierBlock(v3Global.opt.hierarchical()); nodep->unlinkFrBack(); VL_DO_DANGLING(pushDeletep(nodep), nodep); - } else if (nodep->pragType() == AstPragmaType::PUBLIC_MODULE) { + } else if (nodep->pragType() == VPragmaType::PUBLIC_MODULE) { UASSERT_OBJ(m_modp, nodep, "PUBLIC_MODULE not under a module"); m_modp->modPublic(true); nodep->unlinkFrBack(); VL_DO_DANGLING(pushDeletep(nodep), nodep); - } else if (nodep->pragType() == AstPragmaType::PUBLIC_TASK) { + } else if (nodep->pragType() == VPragmaType::PUBLIC_TASK) { UASSERT_OBJ(m_ftaskp, nodep, "PUBLIC_TASK not under a task"); m_ftaskp->taskPublic(true); m_modp->modPublic(true); // Need to get to the task... nodep->unlinkFrBack(); VL_DO_DANGLING(pushDeletep(nodep), nodep); - } else if (nodep->pragType() == AstPragmaType::COVERAGE_BLOCK_OFF) { + } else if (nodep->pragType() == VPragmaType::COVERAGE_BLOCK_OFF) { if (!v3Global.opt.coverageLine()) { // No need for block statements; may optimize // better without nodep->unlinkFrBack(); @@ -544,7 +544,7 @@ public: // Recurses cells backwards, so we can pick up those things that propagate // from child cells up to the top module. -class LinkBotupVisitor final : public AstNVisitor { +class LinkBotupVisitor final : public VNVisitor { private: // STATE AstNodeModule* m_modp = nullptr; // Current module diff --git a/src/V3LinkResolve.h b/src/V3LinkResolve.h index 1e9c36bb4..606886385 100644 --- a/src/V3LinkResolve.h +++ b/src/V3LinkResolve.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3List.h b/src/V3List.h index c1af060f0..c5cb321cb 100644 --- a/src/V3List.h +++ b/src/V3List.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Localize.cpp b/src/V3Localize.cpp index 6b538c4c7..eaf8a5ea6 100644 --- a/src/V3Localize.cpp +++ b/src/V3Localize.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,7 +36,7 @@ //###################################################################### // LocalizeVisitor -class LocalizeVisitor final : public AstNVisitor { +class LocalizeVisitor final : public VNVisitor { private: // NODE STATE // AstVarScope::user1() -> Bool indicating VarScope is not optimizable. @@ -45,10 +45,10 @@ private: // AstVarScope::user3p() -> Set of CFuncs referencing this VarScope. (via m_accessors) // AstCFunc::user4p() -> Multimap of 'VarScope -> VarRefs that reference that VarScope' // in this function. (via m_references) - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; - const AstUser4InUse m_inuser4; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; + const VNUser4InUse m_inuser4; AstUser3Allocator> m_accessors; AstUser4Allocator> @@ -65,7 +65,7 @@ private: bool isOptimizable(AstVarScope* nodep) { return !nodep->user1() || // Not marked as not optimizable, or ... - (nodep->varp()->varType() == AstVarType::BLOCKTEMP + (nodep->varp()->varType() == VVarType::BLOCKTEMP && m_accessors(nodep).size() == 1); // .. a block temp used in a single CFunc } diff --git a/src/V3Localize.h b/src/V3Localize.h index c488a133d..1dce59c59 100644 --- a/src/V3Localize.h +++ b/src/V3Localize.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp index 11b712adb..79a73d4e3 100644 --- a/src/V3MergeCond.cpp +++ b/src/V3MergeCond.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -60,7 +60,7 @@ enum class Mergeable { NO_IMPURE // Tree cannot be merged because it contains an impure node }; -class CheckMergeableVisitor final : public AstNVisitor { +class CheckMergeableVisitor final : public VNVisitor { private: // STATE bool m_condAssign = false; // Does this tree contain an assignment to a condition variable?? @@ -109,30 +109,13 @@ public: } }; -class MarkVarsVisitor final : public AstNVisitor { -private: - // METHODS - VL_DEBUG_FUNC; // Declare debug() - - // VISITORS - virtual void visit(AstVarRef* nodep) override { nodep->varp()->user1(1); } - virtual void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } - -public: - // Remove marks from AstVars (clear user1) - static void clear() { AstNode::user1ClearTree(); } - - // Mark all AstVars referenced by setting user1 - void mark(AstNode* node) { iterate(node); } -}; - -class MergeCondVisitor final : public AstNVisitor { +class MergeCondVisitor final : public VNVisitor { private: // NODE STATE // AstVar::user1 -> Flag set for variables referenced by m_mgCondp // AstNode::user2 -> Flag marking node as included in merge because cheap to duplicate - const AstUser1InUse m_user1InUse; - const AstUser2InUse m_user2InUse; + const VNUser1InUse m_user1InUse; + const VNUser2InUse m_user2InUse; // STATE VDouble0 m_statMerges; // Statistic tracking @@ -146,7 +129,6 @@ private: uint32_t m_listLenght = 0; // Length of current list CheckMergeableVisitor m_checkMergeable; // Sub visitor for encapsulation & speed - MarkVarsVisitor m_markVars; // Sub visitor for encapsulation & speed // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -337,7 +319,7 @@ private: m_mgCondp = nullptr; m_mgLastp = nullptr; m_mgNextp = nullptr; - m_markVars.clear(); + AstNode::user1ClearTree(); // Clear marked variables AstNode::user2ClearTree(); // Merge recursively within the branches if (recursivep) { @@ -407,7 +389,8 @@ private: m_mgFirstp = nodep; m_mgCondp = condp; m_listLenght = 0; - m_markVars.mark(condp); + // Mark variable references in the condition + condp->foreach([](const AstVarRef* nodep) { nodep->varp()->user1(1); }); // Add any preceding nodes to the list that would allow us to extend the merge range for (;;) { AstNode* const backp = m_mgFirstp->backp(); @@ -521,10 +504,7 @@ private: public: // CONSTRUCTORS - explicit MergeCondVisitor(AstNetlist* nodep) { - m_markVars.clear(); - iterate(nodep); - } + explicit MergeCondVisitor(AstNetlist* nodep) { iterate(nodep); } virtual ~MergeCondVisitor() override { V3Stats::addStat("Optimizations, MergeCond merges", m_statMerges); V3Stats::addStat("Optimizations, MergeCond merged items", m_statMergedItems); diff --git a/src/V3MergeCond.h b/src/V3MergeCond.h index 4a3e9b29d..7772705dc 100644 --- a/src/V3MergeCond.h +++ b/src/V3MergeCond.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Name.cpp b/src/V3Name.cpp index 6d743dbf5..73e0a1839 100644 --- a/src/V3Name.cpp +++ b/src/V3Name.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,14 +30,14 @@ //###################################################################### // Name state, as a visitor of each AstNode -class NameVisitor final : public AstNVisitor { +class NameVisitor final : public VNVisitor { private: // NODE STATE // Cleared on Netlist // AstCell::user1() -> bool. Set true if already processed // AstScope::user1() -> bool. Set true if already processed // AstVar::user1() -> bool. Set true if already processed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE const AstNodeModule* m_modp = nullptr; diff --git a/src/V3Name.h b/src/V3Name.h index cc0d6b069..5f7a4b01a 100644 --- a/src/V3Name.h +++ b/src/V3Name.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Number.cpp b/src/V3Number.cpp index a476ab179..5c7493d69 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -1320,14 +1320,6 @@ V3Number& V3Number::opOr(const V3Number& lhs, const V3Number& rhs) { return *this; } -V3Number& V3Number::opChangeXor(const V3Number& lhs, const V3Number& rhs) { - NUM_ASSERT_OP_ARGS2(lhs, rhs); - NUM_ASSERT_LOGIC_ARGS2(lhs, rhs); - // 32 bit result - opEq(lhs, rhs); - return *this; -} - V3Number& V3Number::opXor(const V3Number& lhs, const V3Number& rhs) { // i op j, max(L(lhs),L(rhs)) bit return, careful need to X/Z extend. NUM_ASSERT_OP_ARGS2(lhs, rhs); diff --git a/src/V3Number.h b/src/V3Number.h index b0b1debe0..67cdab14e 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -23,6 +23,7 @@ #include "V3Error.h" #include "V3Hash.h" +#include #include #include #include @@ -421,7 +422,6 @@ public: V3Number& opPowSS(const V3Number& lhs, const V3Number& rhs); // Signed lhs, signed rhs V3Number& opPowUS(const V3Number& lhs, const V3Number& rhs); // Unsigned lhs, signed rhs V3Number& opAnd(const V3Number& lhs, const V3Number& rhs); - V3Number& opChangeXor(const V3Number& lhs, const V3Number& rhs); V3Number& opXor(const V3Number& lhs, const V3Number& rhs); V3Number& opOr(const V3Number& lhs, const V3Number& rhs); V3Number& opShiftR(const V3Number& lhs, const V3Number& rhs); diff --git a/src/V3Number_test.cpp b/src/V3Number_test.cpp index 91034ca7b..f7dc63484 100644 --- a/src/V3Number_test.cpp +++ b/src/V3Number_test.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -99,8 +99,9 @@ void test(const string& lhss, const string& op, const string& rhss, const string gotnum.opLogAnd(lhnum, rhnum); } else if (op == "||") { gotnum.opLogOr(lhnum, rhnum); - } else + } else { v3fatalSrc("Bad opcode: " << op); + } UINFO(0, "------- Test:\n" << " " << lhnum << " " << op << endl diff --git a/src/V3OptionParser.cpp b/src/V3OptionParser.cpp index 3192fac4a..4439ba53d 100644 --- a/src/V3OptionParser.cpp +++ b/src/V3OptionParser.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3OptionParser.h b/src/V3OptionParser.h index ab5d1ddc3..fc199264f 100644 --- a/src/V3OptionParser.h +++ b/src/V3OptionParser.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Options.cpp b/src/V3Options.cpp index d0068f95d..57f30b2d0 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -718,6 +718,10 @@ void V3Options::notify() { "--xml-only or --E option"); } + if (cdc()) { + cmdfl->v3warn(DEPRECATED, "Option --cdc is deprecated and is planned for removal"); + } + if (m_build && (m_gmake || m_cmake)) { cmdfl->v3error("--make cannot be used together with --build. Suggest see manual"); } @@ -1166,7 +1170,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char case 'l': m_oLife = flag; break; case 'm': m_oAssemble = flag; break; // n - case 'o': m_oConstBitOpTree = flag; break; // Can remove ~2022-01 when stable + case 'o': + m_oConstBitOpTree = flag; + break; // Can remove ~2022-01 when stable + // o will be used as an escape for a second character of optimization disables case 'p': m_public = !flag; break; // With -Op so flag=0, we want public on so few optimizations done @@ -1652,7 +1659,7 @@ void V3Options::showVersion(bool verbose) { if (!verbose) return; cout << endl; - cout << "Copyright 2003-2021 by Wilson Snyder. Verilator is free software; you can\n"; + cout << "Copyright 2003-2022 by Wilson Snyder. Verilator is free software; you can\n"; cout << "redistribute it and/or modify the Verilator internals under the terms of\n"; cout << "either the GNU Lesser General Public License Version 3 or the Perl Artistic\n"; cout << "License Version 2.0.\n"; diff --git a/src/V3Options.h b/src/V3Options.h index fb35022dc..e5bcc824e 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,7 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Global.h" +#include "V3Error.h" #include "V3LangCode.h" #include diff --git a/src/V3Order.cpp b/src/V3Order.cpp index aa90bf2a3..433082e68 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -82,7 +82,6 @@ #include "V3Ast.h" #include "V3AstUserAllocator.h" #include "V3Const.h" -#include "V3EmitCBase.h" #include "V3EmitV.h" #include "V3File.h" #include "V3Global.h" @@ -152,7 +151,7 @@ static bool domainsExclusive(const AstSenTree* fromp, const AstSenTree* top) { // Predicate returning true if the LHS of the given assignment is a signal marked as clocker static bool isClockerAssignment(AstNodeAssign* nodep) { - class Visitor final : public AstNVisitor { + class Visitor final : public VNVisitor { public: bool m_clkAss = false; // There is signals marked as clocker in the assignment private: @@ -203,7 +202,7 @@ void OrderGraph::loopsVertexCb(V3GraphVertex* vertexp) { // produce a CLKDATA warning if so. // -class OrderClkMarkVisitor final : public AstNVisitor { +class OrderClkMarkVisitor final : public VNVisitor { bool m_hasClk = false; // flag indicating whether there is clock signal on rhs bool m_inClocked = false; // Currently inside a sequential block bool m_newClkMarked; // Flag for deciding whether a new run is needed @@ -356,7 +355,7 @@ public: // OrderBuildVisitor builds the ordering graph of the entire netlist, and // removes any nodes that are no longer required once the graph is built -class OrderBuildVisitor final : public AstNVisitor { +class OrderBuildVisitor final : public VNVisitor { // TYPES enum VarUsage : uint8_t { VU_CON = 0x1, VU_GEN = 0x2 }; using VarVertexType = OrderUser::VarVertexType; @@ -364,8 +363,8 @@ class OrderBuildVisitor final : public AstNVisitor { // NODE STATE // AstVarScope::user1 -> OrderUser instance for variable (via m_orderUser) // AstVarScope::user2 -> VarUsage within logic blocks - const AstUser1InUse user1InUse; - const AstUser2InUse user2InUse; + const VNUser1InUse user1InUse; + const VNUser2InUse user2InUse; AstUser1Allocator m_orderUser; // STATE @@ -536,6 +535,22 @@ class OrderBuildVisitor final : public AstNVisitor { } } + // Roles of vertices: + // VarVertexType::STD: Data dependencies for combinational logic and delayed + // assignment updates (AssignPost). + // VarVertexType::POST: Ensures all sequential blocks reading a signal do so before + // any combinational or delayed assignments update that signal. + // VarVertexType::PORD: Ensures a _d = _q AssignPre is the first write of a _d, + // before any sequential blocks write to that _d. + // VarVertexType::PRE: This is an optimization. Try to ensure that a _d = _q + // AssignPre is the last read of a _q, after all reads of that + // _q by sequential logic. Note: The model is still correct if we + // cannot satisfy this due to other constraints. If this ordering + // is possible, then combined with the PORD constraint we get + // that all writes to _d are after all reads of a _q, which then + // allows us to eliminate the _d completely and assign to the _q + // directly (this is what V3LifePost does). + // Variable is produced if (gen) { // Update VarUsage @@ -644,6 +659,9 @@ class OrderBuildVisitor final : public AstNVisitor { virtual void visit(AstInitial* nodep) override { // iterateLogic(nodep); } + virtual void visit(AstInitialAutomatic* nodep) override { // + iterateLogic(nodep); + } virtual void visit(AstAlways* nodep) override { // iterateLogic(nodep); } @@ -1034,11 +1052,11 @@ public: //###################################################################### // OrderProcess class -class OrderProcess final : AstNDeleter { +class OrderProcess final : VNDeleter { // NODE STATE - // AstNodeModule::user3 -> int: Number of AstCFuncs created under this module - // AstNode::user4 -> Used by V3Const::constifyExpensiveEdit - const AstUser3InUse user3InUse; + // AstNode::user3 -> Used by loop reporting + // AstNode::user4 -> Used by V3Const::constifyExpensiveEdit + const VNUser3InUse user3InUse; // STATE OrderGraph& m_graph; // The ordering graph @@ -1055,6 +1073,7 @@ class OrderProcess final : AstNDeleter { friend class OrderMoveDomScope; V3List m_pomReadyDomScope; // List of ready domain/scope pairs, by loopId std::vector m_unoptflatVars; // Vector of variables in UNOPTFLAT loop + std::map, unsigned> m_funcNums; // Function ordinals // STATS std::array m_statCut; // Count of each edge type cut @@ -1097,16 +1116,14 @@ class OrderProcess final : AstNDeleter { string cfuncName(AstNodeModule* modp, AstSenTree* domainp, AstScope* scopep, AstNode* forWhatp) { - modp->user3Inc(); - const int funcnum = modp->user3(); - string name = (domainp->hasCombo() - ? "_combo" - : (domainp->hasInitial() - ? "_initial" - : (domainp->hasSettle() - ? "_settle" - : (domainp->isMulti() ? "_multiclk" : "_sequent")))); - name = name + "__" + scopep->nameDotless() + "__" + cvtToStr(funcnum); + string name = domainp->hasCombo() ? "_combo" + : domainp->hasInitial() ? "_initial" + : domainp->hasSettle() ? "_settle" + : domainp->isMulti() ? "_multiclk" + : "_sequent"; + name = name + "__" + scopep->nameDotless(); + const unsigned funcnum = m_funcNums.emplace(std::make_pair(modp, name), 0).first->second++; + name = name + "__" + cvtToStr(funcnum); if (v3Global.opt.profCFuncs()) { name += "__PROF__" + forWhatp->fileline()->profileFuncname(); } @@ -1828,8 +1845,7 @@ AstActive* OrderProcess::processMoveOneLogic(const OrderLogicVertex* lvertexp, newFuncpr->addStmtsp(nodep); if (v3Global.opt.outputSplitCFuncs()) { // Add in the number of nodes we're adding - const EmitCBaseCounterVisitor visitor{nodep}; - newStmtsr += visitor.count(); + newStmtsr += nodep->nodeCount(); } } diff --git a/src/V3Order.h b/src/V3Order.h index 13e762c14..13b82ad69 100644 --- a/src/V3Order.h +++ b/src/V3Order.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3OrderGraph.h b/src/V3OrderGraph.h index d60951ff8..2fb8c33ab 100644 --- a/src/V3OrderGraph.h +++ b/src/V3OrderGraph.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Os.cpp b/src/V3Os.cpp index 6e1417e4c..33d8e2a5b 100644 --- a/src/V3Os.cpp +++ b/src/V3Os.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -52,16 +52,16 @@ // These macros taken from gdbsupport/gdb_wait.h in binutils-gdb # ifndef WIFEXITED # ifdef __MINGW32__ -# define WIFEXITED(w) (((w) & 0xC0000000) == 0) -# define WEXITSTATUS(w) ((w) & ~0xC0000000) +# define WIFEXITED(w) (((w) & 0xC0000000) == 0) +# define WEXITSTATUS(w) ((w) & ~0xC0000000) # else -# define WIFEXITED(w) (((w) & 0377) == 0) -# define WEXITSTATUS(w) (((w) >> 8) & 0377) +# define WIFEXITED(w) (((w) & 0377) == 0) +# define WEXITSTATUS(w) (((w) >> 8) & 0377) # endif # endif #else # include -# include // Needed on FreeBSD for WIFEXITED +# include // Needed on FreeBSD for WIFEXITED # include // usleep #endif // clang-format on @@ -320,10 +320,9 @@ uint64_t V3Os::memUsageBytes() { FILE* fp = fopen(statmFilename, "r"); if (!fp) return 0; vluint64_t size, resident, share, text, lib, data, dt; // All in pages - const int items = fscanf(fp, - "%" VL_PRI64 "u %" VL_PRI64 "u %" VL_PRI64 "u %" VL_PRI64 - "u %" VL_PRI64 "u %" VL_PRI64 "u %" VL_PRI64 "u", - &size, &resident, &share, &text, &lib, &data, &dt); + const int items = fscanf( + fp, "%" SCNu64 " %" SCNu64 " %" SCNu64 " %" SCNu64 " %" SCNu64 " %" SCNu64 " %" SCNu64, + &size, &resident, &share, &text, &lib, &data, &dt); fclose(fp); if (VL_UNCOVERABLE(7 != items)) return 0; return (text + data) * getpagesize(); diff --git a/src/V3Os.h b/src/V3Os.h index 69c90e887..b1143587d 100644 --- a/src/V3Os.h +++ b/src/V3Os.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 936720932..cdb4ce9a2 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -226,8 +226,8 @@ class ParamProcessor final { // AstGenFor::user5() // bool True if processed // AstVar::user5() // bool True if constant propagated // AstCell::user5p() // string* Generate portion of hierarchical name - const AstUser4InUse m_inuser4; - const AstUser5InUse m_inuser5; + const VNUser4InUse m_inuser4; + const VNUser5InUse m_inuser5; // User1/2/3 used by constant function simulations // TYPES @@ -351,7 +351,7 @@ class ParamProcessor final { } return string("z") + cvtToStr(num); } - string moduleCalcName(AstNodeModule* srcModp, const string& longname) { + string moduleCalcName(const AstNodeModule* srcModp, const string& longname) { string newname = longname; if (longname.length() > 30) { const auto iter = m_longMap.find(longname); @@ -554,10 +554,15 @@ class ParamProcessor final { cellp->v3error("Exceeded maximum --module-recursion-depth of " << v3Global.opt.moduleRecursionDepth()); } - // Keep tree sorted by level + // Keep tree sorted by level. Append to end of sub-list at the same level. This is + // important because due to the way recursive modules are handled, different + // parametrizations of the same recursive module end up with the same level (which in + // itself is a bit unfortunate). Nevertheless, as a later parametrization must not be above + // an earlier parametrization of a recursive module, it is sufficient to add to the end of + // the sub-list to keep the modules topologically sorted. AstNodeModule* insertp = srcModp; while (VN_IS(insertp->nextp(), NodeModule) - && VN_AS(insertp->nextp(), NodeModule)->level() < newmodp->level()) { + && VN_AS(insertp->nextp(), NodeModule)->level() <= newmodp->level()) { insertp = VN_AS(insertp->nextp(), NodeModule); } insertp->addNextHere(newmodp); @@ -641,10 +646,11 @@ class ParamProcessor final { longnamer += "_" + paramSmallName(srcModp, modvarp) + paramValueNumber(exprp); any_overridesr = true; } else { + V3Const::constifyParamsEdit(pinp->exprp()); AstConst* const exprp = VN_CAST(pinp->exprp(), Const); const AstConst* const origp = VN_CAST(modvarp->valuep(), Const); if (!exprp) { - // if (debug()) pinp->dumpTree(cout, "error:"); + if (debug()) pinp->dumpTree(cout, "-nodes: "); pinp->v3error("Can't convert defparam value to constant: Param " << pinp->prettyNameQ() << " of " << nodep->prettyNameQ()); pinp->exprp()->replaceWith(new AstConst( @@ -834,7 +840,7 @@ public: //###################################################################### // Process parameter visitor -class ParamVisitor final : public AstNVisitor { +class ParamVisitor final : public VNVisitor { // STATE ParamProcessor m_processor; // De-parameterize a cell, build modules UnrollStateful m_unroller; // Loop unroller diff --git a/src/V3Param.h b/src/V3Param.h index abc07216f..4154aa96f 100644 --- a/src/V3Param.h +++ b/src/V3Param.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Parse.h b/src/V3Parse.h index f1638cdb1..b285030e8 100644 --- a/src/V3Parse.h +++ b/src/V3Parse.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index d26ade756..3f3d06909 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -152,14 +152,14 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name, AstNodeDType* dtypep = GRAMMARP->m_varDTypep; UINFO(5, " creVar " << name << " decl=" << GRAMMARP->m_varDecl << " io=" << GRAMMARP->m_varIO << " dt=" << (dtypep ? "set" : "") << endl); - if (GRAMMARP->m_varIO == VDirection::NONE && GRAMMARP->m_varDecl == AstVarType::PORT) { + if (GRAMMARP->m_varIO == VDirection::NONE && GRAMMARP->m_varDecl == VVarType::PORT) { // Just a port list with variable name (not v2k format); AstPort already created if (dtypep) fileline->v3warn(E_UNSUPPORTED, "Unsupported: Ranges ignored in port-lists"); return nullptr; } - if (GRAMMARP->m_varDecl == AstVarType::WREAL) { + if (GRAMMARP->m_varDecl == VVarType::WREAL) { // dtypep might not be null, might be implicit LOGIC before we knew better - dtypep = new AstBasicDType(fileline, AstBasicDTypeKwd::DOUBLE); + dtypep = new AstBasicDType(fileline, VBasicDTypeKwd::DOUBLE); } if (!dtypep) { // Created implicitly dtypep = new AstBasicDType(fileline, LOGIC_IMPLICIT); @@ -168,15 +168,15 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name, } // UINFO(0,"CREVAR "<ascii()<<" decl="<m_varDecl.ascii()<<" // io="<m_varIO.ascii()<m_varDecl; - if (type == AstVarType::UNKNOWN) { + VVarType type = GRAMMARP->m_varDecl; + if (type == VVarType::UNKNOWN) { if (GRAMMARP->m_varIO.isAny()) { - type = AstVarType::PORT; + type = VVarType::PORT; } else { fileline->v3fatalSrc("Unknown signal type declared: " << type.ascii()); } } - if (type == AstVarType::GENVAR) { + if (type == VVarType::GENVAR) { if (arrayp) fileline->v3error("Genvars may not be arrayed: " << name); } @@ -189,16 +189,16 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name, nodep->ansi(m_pinAnsi); nodep->declTyped(m_varDeclTyped); nodep->lifetime(m_varLifetime); - if (GRAMMARP->m_varDecl != AstVarType::UNKNOWN) nodep->combineType(GRAMMARP->m_varDecl); + if (GRAMMARP->m_varDecl != VVarType::UNKNOWN) nodep->combineType(GRAMMARP->m_varDecl); if (GRAMMARP->m_varIO != VDirection::NONE) { nodep->declDirection(GRAMMARP->m_varIO); nodep->direction(GRAMMARP->m_varIO); } - if (GRAMMARP->m_varDecl == AstVarType::SUPPLY0) { + if (GRAMMARP->m_varDecl == VVarType::SUPPLY0) { nodep->addNext(V3ParseGrammar::createSupplyExpr(fileline, nodep->name(), 0)); } - if (GRAMMARP->m_varDecl == AstVarType::SUPPLY1) { + if (GRAMMARP->m_varDecl == VVarType::SUPPLY1) { nodep->addNext(V3ParseGrammar::createSupplyExpr(fileline, nodep->name(), 1)); } if (VN_IS(dtypep, ParseTypeDType)) { @@ -271,8 +271,9 @@ string V3ParseGrammar::deQuote(FileLine* fileline, string text) { } else if (isalnum(*cp)) { fileline->v3error("Unknown escape sequence: \\" << *cp); break; - } else + } else { newtext += *cp; + } } } else if (*cp == '\\') { quoted = true; diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index ef3f69d63..00ee4a53c 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 3d6dae636..777e205cc 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2009-2021 by Wilson Snyder. This program is free software; you +// Copyright 2009-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -119,7 +119,7 @@ struct V3ParseBisonYYSType { V3ImportProperty iprop; VSigning::en signstate; V3ErrorCode::en errcodeen; - AstAttrType::en attrtypeen; + VAttrType::en attrtypeen; VLifetime::en lifetime; #include "V3Ast__gen_yystype.h" @@ -137,18 +137,18 @@ class V3ParseImp final { VInFilter* const m_filterp; // Reading filter V3ParseSym* m_symp; // Symbol table - V3Lexer* m_lexerp; // Current FlexLexer + V3Lexer* m_lexerp = nullptr; // Current FlexLexer static V3ParseImp* s_parsep; // Current THIS, bison() isn't class based - FileLine* m_lexFileline; // Filename/linenumber currently active for lexing + FileLine* m_lexFileline = nullptr; // Filename/linenumber currently active for lexing FileLine* m_bisonLastFileline; // Filename/linenumber of last token - bool m_inLibrary; // Currently reading a library vs. regular file - int m_lexKwdDepth; // Inside a `begin_keywords + bool m_inLibrary = false; // Currently reading a library vs. regular file + int m_lexKwdDepth = 0; // Inside a `begin_keywords int m_lexKwdLast; // Last LEX state in `begin_keywords VOptionBool m_unconnectedDrive; // Last unconnected drive - int m_lexPrevToken; // previous parsed token (for lexer) + int m_lexPrevToken = 0; // previous parsed token (for lexer) std::deque m_tokensAhead; // Tokens we parsed ahead of parser std::deque m_stringps; // Created strings for later cleanup @@ -156,7 +156,7 @@ class V3ParseImp final { std::deque m_lexLintState; // Current lint state for save/restore std::deque m_ppBuffers; // Preprocessor->lex buffer of characters to process - AstNode* m_tagNodep; // Points to the node to set to m_tag or nullptr to not set. + AstNode* m_tagNodep = nullptr; // Points to the node to set to m_tag or nullptr to not set. VTimescale m_timeLastUnit; // Last `timescale's unit public: @@ -293,13 +293,7 @@ public: : m_rootp{rootp} , m_filterp{filterp} , m_symp{parserSymp} { - m_lexFileline = nullptr; - m_lexerp = nullptr; - m_inLibrary = false; - m_lexKwdDepth = 0; m_lexKwdLast = stateVerilogRecent(); - m_lexPrevToken = 0; - m_tagNodep = nullptr; m_timeLastUnit = v3Global.opt.timeDefaultUnit(); } ~V3ParseImp(); diff --git a/src/V3ParseLex.cpp b/src/V3ParseLex.cpp index 79a9a3438..2ab9d95b9 100644 --- a/src/V3ParseLex.cpp +++ b/src/V3ParseLex.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ParseSym.h b/src/V3ParseSym.h index f6291fb58..4da0c735c 100644 --- a/src/V3ParseSym.h +++ b/src/V3ParseSym.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2009-2021 by Wilson Snyder. This program is free software; you +// Copyright 2009-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -26,6 +26,7 @@ #include "V3SymTable.h" #include +#include //###################################################################### // Symbol table for parsing @@ -39,7 +40,7 @@ private: static int s_anonNum; // Number of next anonymous object (parser use only) VSymGraph m_syms; // Graph of symbol tree VSymEnt* m_symTableNextId = nullptr; // Symbol table for next lexer lookup (parser use only) - VSymEnt* m_symCurrentp; // Active symbol table for additions/lookups + VSymEnt* m_symCurrentp = nullptr; // Active symbol table for additions/lookups std::vector m_sympStack; // Stack of upper nodes with pending symbol tables public: diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index 8895c6cd8..d7b23942a 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -876,7 +876,7 @@ public: class PartParallelismEst final { // MEMBERS - const V3Graph* m_graphp; // Mtask-containing graph + const V3Graph* const m_graphp; // Mtask-containing graph // Total cost of evaluating the whole graph. // The ratio of m_totalGraphCost to longestCpCost gives us an estimate @@ -1108,7 +1108,7 @@ private: }; // MEMBERS - V3Graph* m_mtasksp; // Mtask graph + V3Graph* const m_mtasksp; // Mtask graph uint32_t m_scoreLimit; // Sloppy score allowed when picking merges uint32_t m_scoreLimitBeforeRescore = 0xffffffff; // Next score rescore at unsigned m_mergesSinceRescore = 0; // Merges since last rescore @@ -1698,7 +1698,7 @@ const GraphWay* PartContraction::s_shortestWaywardCpInclusiveWay = nullptr; // Scan node, indicate whether it contains a call to a DPI imported // routine. -class DpiImportCallVisitor final : public AstNVisitor { +class DpiImportCallVisitor final : public VNVisitor { private: bool m_hasDpiHazard = false; // Found a DPI import call. bool m_tracingCall = false; // Iterating into a CCall to a CFunc @@ -1827,7 +1827,7 @@ private: using Olv2MTaskMap = std::unordered_map; // MEMBERS - V3Graph* m_mtasksp; // Mtask graph + V3Graph* const m_mtasksp; // Mtask graph Olv2MTaskMap m_olv2mtask; // Map OrderLogicVertex to LogicMTask who wraps it unsigned m_mergesDone = 0; // Number of MTasks merged. For stats only. public: @@ -2565,7 +2565,7 @@ void V3Partition::go(V3Graph* mtasksp) { { // The V3InstrCount within LogicMTask will set user5 on each AST // node, to assert that we never count any node twice. - const AstUser5InUse inUser5; + const VNUser5InUse inUser5; Vx2MTaskMap vx2mtask; for (V3GraphVertex* vxp = m_fineDepsGraphp->verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { @@ -2909,8 +2909,8 @@ static void addMTaskToFunction(const ThreadSchedule& schedule, const uint32_t th // state variable and wait to be notified. const string name = "__Vm_mtaskstate_" + cvtToStr(mtaskp->id()); AstBasicDType* const mtaskStateDtypep - = v3Global.rootp()->typeTablep()->findBasicDType(fl, AstBasicDTypeKwd::MTASKSTATE); - AstVar* const varp = new AstVar(fl, AstVarType::MODULETEMP, name, mtaskStateDtypep); + = v3Global.rootp()->typeTablep()->findBasicDType(fl, VBasicDTypeKwd::MTASKSTATE); + AstVar* const varp = new AstVar(fl, VVarType::MODULETEMP, name, mtaskStateDtypep); varp->valuep(new AstConst(fl, nDependencies)); varp->protect(false); // Do not protect as we still have references in AstText modp->addStmtp(varp); @@ -3001,9 +3001,9 @@ static const std::vector createThreadFunctions(const ThreadSchedule& // Create the fake "final" mtask state variable AstBasicDType* const mtaskStateDtypep - = v3Global.rootp()->typeTablep()->findBasicDType(fl, AstBasicDTypeKwd::MTASKSTATE); + = v3Global.rootp()->typeTablep()->findBasicDType(fl, VBasicDTypeKwd::MTASKSTATE); AstVar* const varp - = new AstVar(fl, AstVarType::MODULETEMP, "__Vm_mtaskstate_final", mtaskStateDtypep); + = new AstVar(fl, VVarType::MODULETEMP, "__Vm_mtaskstate_final", mtaskStateDtypep); varp->valuep(new AstConst(fl, funcps.size())); varp->protect(false); // Do not protect as we still have references in AstText modp->addStmtp(varp); diff --git a/src/V3Partition.h b/src/V3Partition.h index 8d22d740a..d6155a852 100644 --- a/src/V3Partition.h +++ b/src/V3Partition.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -24,6 +24,7 @@ #include "V3OrderGraph.h" #include +#include class LogicMTask; using Vx2MTaskMap = std::unordered_map; @@ -36,7 +37,7 @@ using Vx2MTaskMap = std::unordered_map; class V3Partition final { // MEMBERS - V3Graph* m_fineDepsGraphp; // Fine-grained dependency graph + V3Graph* const m_fineDepsGraphp; // Fine-grained dependency graph public: // CONSTRUCTORS explicit V3Partition(V3Graph* fineDepsGraphp) diff --git a/src/V3PartitionGraph.h b/src/V3PartitionGraph.h index d4518bb23..e32a759e2 100644 --- a/src/V3PartitionGraph.h +++ b/src/V3PartitionGraph.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PreLex.h b/src/V3PreLex.h index 3eeda4fa4..804b29e86 100644 --- a/src/V3PreLex.h +++ b/src/V3PreLex.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2000-2021 by Wilson Snyder. This program is free software; you +// Copyright 2000-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -129,7 +129,7 @@ void yy_delete_buffer(YY_BUFFER_STATE b); class VPreStream final { public: FileLine* m_curFilelinep; // Current processing point (see also m_tokFilelinep) - V3PreLex* m_lexp; // Lexer, for resource tracking + V3PreLex* const m_lexp; // Lexer, for resource tracking std::deque m_buffers; // Buffer of characters to process int m_ignNewlines = 0; // Ignore multiline newlines bool m_eof = false; // "EOF" buffer @@ -155,7 +155,7 @@ enum class Enctype : uint8_t { UUENCODE, BASE64, QUOTE_PRINTABLE, RAW, ERR }; class V3PreLex final { public: // Used only by V3PreLex.cpp and V3PreProc.cpp - V3PreProcImp* m_preimpp; // Preprocessor lexor belongs to + V3PreProcImp* const m_preimpp; // Preprocessor lexor belongs to std::stack m_streampStack; // Stack of processing files int m_streamDepth = 0; // Depth of stream processing YY_BUFFER_STATE m_bufferState; // Flex state diff --git a/src/V3PreLex.l b/src/V3PreLex.l index bb591ba9e..c53a675eb 100644 --- a/src/V3PreLex.l +++ b/src/V3PreLex.l @@ -5,7 +5,7 @@ * ************************************************************************** * - * Copyright 2003-2021 by Wilson Snyder. This program is free software; you + * Copyright 2003-2022 by Wilson Snyder. This program is free software; you * can redistribute it and/or modify it under the terms of either the * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index d1786aecb..7301d6b1e 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2000-2021 by Wilson Snyder. This program is free software; you +// Copyright 2000-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PreProc.h b/src/V3PreProc.h index 6af036d3b..17b8d202f 100644 --- a/src/V3PreProc.h +++ b/src/V3PreProc.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2000-2021 by Wilson Snyder. This program is free software; you +// Copyright 2000-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -22,6 +22,7 @@ #include "V3Error.h" #include "V3FileLine.h" +#include "V3Global.h" #include #include diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp index ff50c8e0e..6d64c4b7f 100644 --- a/src/V3PreShell.cpp +++ b/src/V3PreShell.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PreShell.h b/src/V3PreShell.h index 97198899d..7e26f940f 100644 --- a/src/V3PreShell.h +++ b/src/V3PreShell.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp index 68cad721f..7501cd456 100644 --- a/src/V3Premit.cpp +++ b/src/V3Premit.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -37,64 +37,18 @@ constexpr int STATIC_CONST_MIN_WIDTH = 256; // Minimum size to extract to static constant -//###################################################################### -// Structure for global state - -class PremitAssignVisitor final : public AstNVisitor { -private: - // NODE STATE - // AstVar::user3() // bool; occurs on LHS of current assignment - const AstUser3InUse m_inuser3; - - // STATE - bool m_noopt = false; // Disable optimization of variables in this block - - // METHODS - VL_DEBUG_FUNC; // Declare debug() - - // VISITORS - virtual void visit(AstNodeAssign* nodep) override { - // AstNode::user3ClearTree(); // Implied by AstUser3InUse - // LHS first as fewer varrefs - iterateAndNextNull(nodep->lhsp()); - // Now find vars marked as lhs - iterateAndNextNull(nodep->rhsp()); - } - virtual void visit(AstVarRef* nodep) override { - // it's LHS var is used so need a deep temporary - if (nodep->access().isWriteOrRW()) { - nodep->varp()->user3(true); - } else { - if (nodep->varp()->user3()) { - if (!m_noopt) UINFO(4, "Block has LHS+RHS var: " << nodep << endl); - m_noopt = true; - } - } - } - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - explicit PremitAssignVisitor(AstNodeAssign* nodep) { - UINFO(4, " PremitAssignVisitor on " << nodep << endl); - iterate(nodep); - } - virtual ~PremitAssignVisitor() override = default; - bool noOpt() const { return m_noopt; } -}; - //###################################################################### // Premit state, as a visitor of each AstNode -class PremitVisitor final : public AstNVisitor { +class PremitVisitor final : public VNVisitor { private: // NODE STATE // AstNodeMath::user() -> bool. True if iterated already // AstShiftL::user2() -> bool. True if converted to conditional // AstShiftR::user2() -> bool. True if converted to conditional - // *::user3() -> See PremitAssignVisitor - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; + // *::user3() -> Used when visiting AstNodeAssign + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; // STATE AstCFunc* m_cfuncp = nullptr; // Current block @@ -155,7 +109,7 @@ private: } else if (m_inTracep) { m_inTracep->addPrecondsp(newp); } else if (m_stmtp) { - AstNRelinker linker; + VNRelinker linker; m_stmtp->unlinkFrBack(&linker); newp->addNext(m_stmtp); linker.relink(newp); @@ -167,7 +121,7 @@ private: void createDeepTemp(AstNode* nodep, bool noSubst) { if (nodep->user1SetOnce()) return; // Only add another assignment for this node - AstNRelinker relinker; + VNRelinker relinker; nodep->unlinkFrBack(&relinker); FileLine* const fl = nodep->fileline(); @@ -185,7 +139,7 @@ private: ++m_extractedToConstPool; } else { // Keep as local temporary. Name based on hash of node for output stability. - varp = new AstVar(fl, AstVarType::STMTTEMP, m_tempNames.get(nodep), nodep->dtypep()); + varp = new AstVar(fl, VVarType::STMTTEMP, m_tempNames.get(nodep), nodep->dtypep()); m_cfuncp->addInitsp(varp); // Put assignment before the referencing statement insertBeforeStmt(new AstAssign(fl, new AstVarRef(fl, varp, VAccess::WRITE), nodep)); @@ -231,7 +185,17 @@ private: virtual void visit(AstNodeAssign* nodep) override { startStatement(nodep); { - const bool noopt = PremitAssignVisitor(nodep).noOpt(); + bool noopt = false; + { + const VNUser3InUse user3InUse; + nodep->lhsp()->foreach([](const AstVarRef* refp) { + if (refp->access().isWriteOrRW()) refp->varp()->user3(true); + }); + nodep->rhsp()->foreach([&noopt](const AstVarRef* refp) { + if (refp->access().isReadOnly() && refp->varp()->user3()) noopt = true; + }); + } + if (noopt && !nodep->user1()) { nodep->user1(true); // Need to do this even if not wide, as e.g. a select may be on a wide operator @@ -276,7 +240,7 @@ private: // C operator's width must be < maximum shift which is // based on Verilog width && nodep->width() < (1LL << nodep->rhsp()->widthMin())) { - AstNRelinker replaceHandle; + VNRelinker replaceHandle; nodep->unlinkFrBack(&replaceHandle); AstNode* constzerop; const int m1value diff --git a/src/V3Premit.h b/src/V3Premit.h index cfeb48fe2..fe13743ed 100644 --- a/src/V3Premit.h +++ b/src/V3Premit.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp index 67280e92c..c89d9ce5c 100644 --- a/src/V3ProtectLib.cpp +++ b/src/V3ProtectLib.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -28,7 +28,7 @@ //###################################################################### // ProtectLib top-level visitor -class ProtectVisitor final : public AstNVisitor { +class ProtectVisitor final : public VNVisitor { private: AstVFile* m_vfilep = nullptr; // DPI-enabled Verilog wrapper AstCFile* m_cfilep = nullptr; // C implementation of DPI functions @@ -410,9 +410,9 @@ private: + "_protectlib_trace(void* vhandlep__V, void* tfp, int levels, " "int options) {\n"); castPtr(fl, txtp); - txtp->addText( - fl, - /**/ "handlep__V->trace(static_cast(tfp), levels, options);\n"); + txtp->addText(fl, + /**/ "handlep__V->trace(static_cast<" + v3Global.opt.traceClassBase() + + "C*>(tfp), levels, options);\n"); txtp->addText(fl, "}\n\n"); } @@ -471,7 +471,7 @@ private: static void addLocalVariable(AstTextBlock* textp, AstVar* varp, const char* suffix) { AstVar* const newVarp - = new AstVar(varp->fileline(), AstVarType::VAR, varp->name() + suffix, varp->dtypep()); + = new AstVar(varp->fileline(), VVarType::VAR, varp->name() + suffix, varp->dtypep()); textp->addNodep(newVarp); } diff --git a/src/V3ProtectLib.h b/src/V3ProtectLib.h index 7f2028141..6055311b2 100644 --- a/src/V3ProtectLib.h +++ b/src/V3ProtectLib.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,9 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" - //============================================================================ class V3ProtectLib final { diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index c4821b87e..88aa10198 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -27,17 +27,18 @@ #include "config_build.h" #include "verilatedos.h" +#include "V3Ast.h" #include "V3Randomize.h" //###################################################################### // Visitor that marks classes needing a randomize() method -class RandomizeMarkVisitor final : public AstNVisitor { +class RandomizeMarkVisitor final : public VNVisitor { private: // NODE STATE // Cleared on Netlist // AstClass::user1() -> bool. Set true to indicate needs randomize processing - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; using DerivedSet = std::unordered_set; using BaseToDerivedMap = std::unordered_map; @@ -112,14 +113,14 @@ public: //###################################################################### // Visitor that defines a randomize method where needed -class RandomizeVisitor final : public AstNVisitor { +class RandomizeVisitor final : public VNVisitor { private: // NODE STATE // Cleared on Netlist // AstClass::user1() -> bool. Set true to indicate needs randomize processing // AstEnumDType::user2() -> AstVar*. Pointer to table with enum values - // AstUser1InUse m_inuser1; (Allocated for use in RandomizeMarkVisitor) - const AstUser2InUse m_inuser2; + // VNUser1InUse m_inuser1; (Allocated for use in RandomizeMarkVisitor) + const VNUser2InUse m_inuser2; // STATE size_t m_enumValueTabCount = 0; // Number of tables with enum values created @@ -136,7 +137,7 @@ private: AstInitArray* const initp = new AstInitArray(nodep->fileline(), vardtypep, nullptr); v3Global.rootp()->typeTablep()->addTypesp(vardtypep); AstVar* const varp - = new AstVar(nodep->fileline(), AstVarType::MODULETEMP, + = new AstVar(nodep->fileline(), VVarType::MODULETEMP, "__Venumvaltab_" + cvtToStr(m_enumValueTabCount++), vardtypep); varp->isConst(true); varp->isStatic(true); @@ -182,7 +183,7 @@ private: auto* const randp = new AstRand(fl, nullptr, false); auto* const moddivp = new AstModDiv(fl, randp, new AstConst(fl, enumDtp->itemCount())); - randp->dtypep(varrefp->findBasicDType(AstBasicDTypeKwd::UINT32)); + randp->dtypep(varrefp->findBasicDType(VBasicDTypeKwd::UINT32)); moddivp->dtypep(enumDtp); valp = new AstArraySel(fl, tabRefp, moddivp); } else { @@ -264,7 +265,7 @@ AstFunc* V3Randomize::newRandomizeFunc(AstClass* nodep) { if (!funcp) { auto* const dtypep = nodep->findBitDType(32, 32, VSigning::SIGNED); // IEEE says int return of 0/1 - auto* const fvarp = new AstVar(nodep->fileline(), AstVarType::MEMBER, "randomize", dtypep); + auto* const fvarp = new AstVar(nodep->fileline(), VVarType::MEMBER, "randomize", dtypep); fvarp->lifetime(VLifetime::AUTOMATIC); fvarp->funcLocal(true); fvarp->funcReturn(true); diff --git a/src/V3Randomize.h b/src/V3Randomize.h index 9cb4df8de..29ea2b6b7 100644 --- a/src/V3Randomize.h +++ b/src/V3Randomize.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,7 +20,9 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Ast.h" +class AstClass; +class AstFunc; +class AstNetlist; class V3Randomize final { public: diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp index edf144d16..360f38769 100644 --- a/src/V3Reloop.cpp +++ b/src/V3Reloop.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -41,11 +41,11 @@ //###################################################################### -class ReloopVisitor final : public AstNVisitor { +class ReloopVisitor final : public VNVisitor { private: // NODE STATE // AstCFunc::user1p -> Var* for temp var, 0=not set yet - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE VDouble0 m_statReloops; // Statistic tracking @@ -71,7 +71,7 @@ private: AstVar* varp = VN_AS(cfuncp->user1p(), Var); if (!varp) { const string newvarname = string("__Vilp"); - varp = new AstVar(fl, AstVarType::STMTTEMP, newvarname, VFlagLogicPacked(), 32); + varp = new AstVar(fl, VVarType::STMTTEMP, newvarname, VFlagLogicPacked(), 32); UASSERT_OBJ(cfuncp, fl, "Assignment not under a function"); cfuncp->addInitsp(varp); cfuncp->user1p(varp); diff --git a/src/V3Reloop.h b/src/V3Reloop.h index 4a3302adb..c94cc30e9 100644 --- a/src/V3Reloop.h +++ b/src/V3Reloop.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index 5a288cde2..4d8280514 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,13 +36,13 @@ //###################################################################### // Scope class functions -class ScopeVisitor final : public AstNVisitor { +class ScopeVisitor final : public VNVisitor { private: // NODE STATE // AstVar::user1p -> AstVarScope replacement for this variable // AstTask::user2p -> AstTask*. Replacement task - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; // TYPES // These cannot be unordered unless make a specialized hashing pair (gcc-8) @@ -320,7 +320,7 @@ public: //###################################################################### // Scope cleanup -- remove unused activates -class ScopeCleanupVisitor final : public AstNVisitor { +class ScopeCleanupVisitor final : public VNVisitor { private: // STATE AstScope* m_scopep = nullptr; // Current scope we are building diff --git a/src/V3Scope.h b/src/V3Scope.h index ef754c534..391810df2 100644 --- a/src/V3Scope.h +++ b/src/V3Scope.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Scoreboard.cpp b/src/V3Scoreboard.cpp index f265322ba..78d466596 100644 --- a/src/V3Scoreboard.cpp +++ b/src/V3Scoreboard.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Scoreboard.h b/src/V3Scoreboard.h index 4e68d9f8c..7130e7284 100644 --- a/src/V3Scoreboard.h +++ b/src/V3Scoreboard.h @@ -13,7 +13,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -29,8 +29,9 @@ #include "V3Error.h" -#include +#include #include +#include #include //###################################################################### @@ -70,7 +71,7 @@ public: // MEMBERS typename KeySet::iterator m_keyIt; typename Val2Keys::iterator m_valIt; - SortByValueMap* m_sbvmp; + SortByValueMap* const m_sbvmp; bool m_end = true; // At the end() // CONSTRUCTORS diff --git a/src/V3SenTree.h b/src/V3SenTree.h index 2cc62d06b..c140580a0 100644 --- a/src/V3SenTree.h +++ b/src/V3SenTree.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,51 +31,11 @@ // Collect SenTrees under the entire scope // And provide functions to find/add a new one -class SenTreeSet final { - // Hash table of sensitive blocks. -private: - // TYPES - struct HashSenTree { - size_t operator()(const AstSenTree* kp) const { - return V3Hasher::uncachedHash(kp).value(); - } - }; - - struct EqSenTree { - bool operator()(const AstSenTree* ap, const AstSenTree* bp) const { - return ap->sameTree(bp); - } - }; - - // MEMBERS - using Set = std::unordered_set; - Set m_trees; // Set of sensitive blocks, for folding. - -public: - // CONSTRUCTORS - SenTreeSet() = default; - - // METHODS - void add(AstSenTree* nodep) { m_trees.insert(nodep); } - - AstSenTree* find(AstSenTree* likep) { - AstSenTree* resultp = nullptr; - const auto it = m_trees.find(likep); - if (it != m_trees.end()) resultp = *it; - return resultp; - } - - void clear() { m_trees.clear(); } - -private: - VL_UNCOPYABLE(SenTreeSet); -}; - class SenTreeFinder final { private: // STATE AstTopScope* const m_topScopep; // Top scope to add global SenTrees to - SenTreeSet m_trees; // Set of global SenTrees + std::unordered_set> m_trees; // Set of global SenTrees VL_UNCOPYABLE(SenTreeFinder); @@ -87,25 +47,26 @@ public: explicit SenTreeFinder(AstNetlist* netlistp) : m_topScopep{netlistp->topScopep()} { // Gather existing global SenTrees - for (AstNode* nodep = m_topScopep->senTreesp(); nodep; nodep = nodep->nextp()) { - m_trees.add(VN_AS(nodep, SenTree)); + for (AstSenTree* senTreep = m_topScopep->senTreesp(); senTreep; + senTreep = VN_AS(senTreep->nextp(), SenTree)) { + m_trees.emplace(*senTreep); } } // METHODS - // Return a global AstSenTree that matches given SenTree. + // Return a global AstSenTree equivalent to the given senTreep. // If no such global AstSenTree exists create one and add it to the stored AstTopScope. AstSenTree* getSenTree(AstSenTree* senTreep) { - AstSenTree* treep = m_trees.find(senTreep); - if (!treep) { - // Not found, form a new one - treep = senTreep->cloneTree(false); - m_topScopep->addSenTreep(treep); - UINFO(8, " New SENTREE " << treep << endl); - m_trees.add(treep); - } - return treep; + auto it = m_trees.find(*senTreep); + // If match found, return it. + if (it != m_trees.end()) return &(*it).get(); + + // Not found, create a new one + AstSenTree* const newSenTreep = senTreep->cloneTree(false); + m_topScopep->addSenTreep(newSenTreep); + m_trees.emplace(*newSenTreep); + return newSenTreep; } // Return the global combinational AstSenTree. diff --git a/src/V3Simulate.h b/src/V3Simulate.h index d4afec168..9262e1ed3 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -42,6 +42,9 @@ #include #include +#include +#include +#include #include //============================================================================ @@ -52,8 +55,8 @@ class SimStackNode final { public: // MEMBERS - AstFuncRef* m_funcp; - V3TaskConnects* m_tconnects; + AstFuncRef* const m_funcp; + V3TaskConnects* const m_tconnects; // CONSTRUCTORS SimStackNode(AstFuncRef* funcp, V3TaskConnects* tconnects) : m_funcp{funcp} @@ -61,7 +64,7 @@ public: ~SimStackNode() = default; }; -class SimulateVisitor VL_NOT_FINAL : public AstNVisitor { +class SimulateVisitor VL_NOT_FINAL : public VNVisitor { // Simulate a node tree, returning value of variables // Two major operating modes: // Test the tree to see if it is conformant @@ -72,9 +75,9 @@ class SimulateVisitor VL_NOT_FINAL : public AstNVisitor { private: // NODE STATE // Cleared on each always/assignw - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; // Checking: // AstVar(Scope)::user1() -> VarUsage. Set true to indicate tracking as lvalue/rvalue @@ -753,7 +756,9 @@ private: virtual void visit(AstNodeAssign* nodep) override { if (jumpingOver(nodep)) return; if (!optimizable()) return; // Accelerate - if (VN_IS(nodep, AssignDly)) { + if (VN_IS(nodep, AssignForce)) { + clearOptimizable(nodep, "Force"); + } else if (VN_IS(nodep, AssignDly)) { if (m_anyAssignComb) clearOptimizable(nodep, "Mix of dly/non-dly assigns"); m_anyAssignDly = true; m_inDlyAssign = true; @@ -975,6 +980,13 @@ private: VL_DANGLING(funcp); // Make sure we've sized the function funcp = nodep->taskp(); UASSERT_OBJ(funcp, nodep, "Not linked"); + if (funcp->recursive()) { + // Because we attach values to nodes rather then making a stack, this is a mess + // When we do support this, we need a stack depth limit of 1K or something, + // and the t_func_recurse_param_bad.v test should check that limit's error message + clearOptimizable(funcp, "Unsupported: Recursive constant functions"); + return; + } // Apply function call values to function V3TaskConnects tconnects = V3Task::taskConnects(nodep, nodep->taskp()->stmtsp()); // Must do this in two steps, eval all params, then apply them @@ -1098,12 +1110,12 @@ private: if (m_params) { AstConst* const textp = fetchConst(nodep->fmtp()); switch (nodep->displayType()) { - case AstDisplayType::DT_DISPLAY: // FALLTHRU - case AstDisplayType::DT_INFO: v3warn(USERINFO, textp->name()); break; - case AstDisplayType::DT_ERROR: v3warn(USERERROR, textp->name()); break; - case AstDisplayType::DT_WARNING: v3warn(USERWARN, textp->name()); break; - case AstDisplayType::DT_FATAL: v3warn(USERFATAL, textp->name()); break; - case AstDisplayType::DT_WRITE: // FALLTHRU + case VDisplayType::DT_DISPLAY: // FALLTHRU + case VDisplayType::DT_INFO: v3warn(USERINFO, textp->name()); break; + case VDisplayType::DT_ERROR: v3warn(USERERROR, textp->name()); break; + case VDisplayType::DT_WARNING: v3warn(USERWARN, textp->name()); break; + case VDisplayType::DT_FATAL: v3warn(USERFATAL, textp->name()); break; + case VDisplayType::DT_WRITE: // FALLTHRU default: clearOptimizable(nodep, "Unexpected display type"); } } diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp index bd2c9c2a9..a70aabde1 100644 --- a/src/V3Slice.cpp +++ b/src/V3Slice.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -44,13 +44,13 @@ //************************************************************************* -class SliceVisitor final : public AstNVisitor { +class SliceVisitor final : public VNVisitor { // NODE STATE // Cleared on netlist // AstNodeAssign::user1() -> bool. True if find is complete // AstNodeUniop::user1() -> bool. True if find is complete // AstArraySel::user1p() -> AstVarRef. The VarRef that the final ArraySel points to - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE AstNode* m_assignp = nullptr; // Assignment we are under @@ -196,12 +196,12 @@ class SliceVisitor final : public AstNVisitor { logp = clonep; } else { switch (nodep->type()) { - case AstType::atEq: // FALLTHRU - case AstType::atEqCase: + case VNType::atEq: // FALLTHRU + case VNType::atEqCase: logp = new AstLogAnd(nodep->fileline(), logp, clonep); break; - case AstType::atNeq: // FALLTHRU - case AstType::atNeqCase: + case VNType::atNeq: // FALLTHRU + case VNType::atNeqCase: logp = new AstLogOr(nodep->fileline(), logp, clonep); break; default: diff --git a/src/V3Slice.h b/src/V3Slice.h index cbc544ad3..4c65f5e8c 100644 --- a/src/V3Slice.h +++ b/src/V3Slice.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Split.cpp b/src/V3Split.cpp index e8140ebf9..bd3355fb5 100644 --- a/src/V3Split.cpp +++ b/src/V3Split.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -235,17 +235,17 @@ public: //###################################################################### // Split class functions -class SplitReorderBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class SplitReorderBaseVisitor VL_NOT_FINAL : public VNVisitor { private: // NODE STATE // AstVarScope::user1p -> Var SplitNodeVertex* for usage var, 0=not set yet // AstVarScope::user2p -> Var SplitNodeVertex* for delayed assignment var, 0=not set yet // Ast*::user3p -> Statement SplitLogicVertex* (temporary only) // Ast*::user4 -> Current ordering number (reorderBlock usage) - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; - const AstUser4InUse m_inuser4; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; + const VNUser4InUse m_inuser4; protected: // STATE @@ -254,14 +254,11 @@ protected: SplitPliVertex* m_pliVertexp; // Element specifying PLI ordering V3Graph m_graph; // Scoreboard of var usages/dependencies bool m_inDly; // Inside ASSIGNDLY - VDouble0 m_statSplits; // Statistic tracking // CONSTRUCTORS public: SplitReorderBaseVisitor() { scoreboardClear(); } - virtual ~SplitReorderBaseVisitor() override { - V3Stats::addStat("Optimizations, Split always", m_statSplits); - } + virtual ~SplitReorderBaseVisitor() override = default; // METHODS protected: @@ -543,7 +540,7 @@ protected: if (leaveAlone) { UINFO(6, " No changes\n"); } else { - AstNRelinker replaceHandle; // Where to add the list + VNRelinker replaceHandle; // Where to add the list AstNode* newListp = nullptr; for (auto it = rankMap.cbegin(); it != rankMap.cend(); ++it) { AstNode* const nextp = it->second; @@ -623,7 +620,7 @@ private: using ColorSet = std::unordered_set; using AlwaysVec = std::vector; -class IfColorVisitor final : public AstNVisitor { +class IfColorVisitor final : public VNVisitor { // MEMBERS ColorSet m_colors; // All colors in the original always block @@ -681,7 +678,7 @@ private: VL_UNCOPYABLE(IfColorVisitor); }; -class EmitSplitVisitor final : public AstNVisitor { +class EmitSplitVisitor final : public VNVisitor { // MEMBERS const AstAlways* const m_origAlwaysp; // Block that *this will split const IfColorVisitor* const m_ifColorp; // Digest of results of prior coloring @@ -793,22 +790,56 @@ private: VL_UNCOPYABLE(EmitSplitVisitor); }; -class RemovePlaceholdersVisitor final : public AstNVisitor { - std::unordered_set m_removeSet; // placeholders to be removed -public: - explicit RemovePlaceholdersVisitor(AstNode* nodep) { - iterate(nodep); - for (AstNode* np : m_removeSet) { - np->unlinkFrBack(); // Without next - VL_DO_DANGLING(np->deleteTree(), np); +class RemovePlaceholdersVisitor final : public VNVisitor { + // MEMBERS + bool m_isPure = true; + int m_emptyAlways = 0; + + // CONSTRUCTORS + RemovePlaceholdersVisitor() = default; + virtual ~RemovePlaceholdersVisitor() override = default; + + // VISITORS + virtual void visit(AstSplitPlaceholder* nodep) override { pushDeletep(nodep->unlinkFrBack()); } + virtual void visit(AstNodeIf* nodep) override { + VL_RESTORER(m_isPure); + m_isPure = true; + iterateChildren(nodep); + if (!nodep->ifsp() && !nodep->elsesp() && m_isPure) pushDeletep(nodep->unlinkFrBack()); + } + virtual void visit(AstAlways* nodep) override { + VL_RESTORER(m_isPure); + m_isPure = true; + iterateChildren(nodep); + if (m_isPure) { + bool emptyOrCommentOnly = true; + for (AstNode* bodysp = nodep->bodysp(); bodysp; bodysp = bodysp->nextp()) { + // If this always block contains only AstComment, remove here. + // V3Gate will remove anyway. + if (!VN_IS(bodysp, Comment)) { + emptyOrCommentOnly = false; + break; + } + } + if (emptyOrCommentOnly) { + pushDeletep(nodep->unlinkFrBack()); + ++m_emptyAlways; + } } } - virtual ~RemovePlaceholdersVisitor() override = default; - virtual void visit(AstSplitPlaceholder* nodep) override { m_removeSet.insert(nodep); } - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } + virtual void visit(AstNode* nodep) override { + m_isPure &= nodep->isPure(); + iterateChildren(nodep); // must visit regardless of m_isPure to remove placeholders + } -private: VL_UNCOPYABLE(RemovePlaceholdersVisitor); + +public: + static int exec(AstAlways* nodep) { + RemovePlaceholdersVisitor visitor; + visitor.iterate(nodep); + return visitor.m_emptyAlways; + } }; class SplitVisitor final : public SplitReorderBaseVisitor { @@ -820,6 +851,7 @@ private: // AstNodeIf* whose condition we're currently visiting const AstNode* m_curIfConditional = nullptr; + VDouble0 m_statSplits; // Statistic tracking // CONSTRUCTORS public: @@ -834,14 +866,17 @@ public: for (AlwaysVec::iterator addme = it->second.begin(); addme != it->second.end(); ++addme) { origp->addNextHere(*addme); - RemovePlaceholdersVisitor{*addme}; + const int numRemoved = RemovePlaceholdersVisitor::exec(*addme); + m_statSplits -= numRemoved; } origp->unlinkFrBack(); // Without next VL_DO_DANGLING(origp->deleteTree(), origp); } } - virtual ~SplitVisitor() override = default; + virtual ~SplitVisitor() override { + V3Stats::addStat("Optimizations, Split always", m_statSplits); + } // METHODS protected: @@ -944,7 +979,7 @@ protected: // Counting original always blocks rather than newly-split // always blocks makes it a little easier to use this stat to // check the result of the t_alw_split test: - ++m_statSplits; + m_statSplits += ifColor.colors().size() - 1; // -1 for the original always // Visit through the original always block one more time, // and emit the split always blocks into m_replaceBlocks: diff --git a/src/V3Split.h b/src/V3Split.h index 1fd5f5fb0..4fd6960eb 100644 --- a/src/V3Split.h +++ b/src/V3Split.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3SplitAs.cpp b/src/V3SplitAs.cpp index 1ff583f70..caea1a33a 100644 --- a/src/V3SplitAs.cpp +++ b/src/V3SplitAs.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,7 +33,7 @@ //###################################################################### -class SplitAsBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class SplitAsBaseVisitor VL_NOT_FINAL : public VNVisitor { public: // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -128,7 +128,7 @@ class SplitAsVisitor final : public SplitAsBaseVisitor { private: // NODE STATE // AstAlways::user() -> bool. True if already processed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE VDouble0 m_statSplits; // Statistic tracking diff --git a/src/V3SplitAs.h b/src/V3SplitAs.h index a0004c4e0..b959c709e 100644 --- a/src/V3SplitAs.h +++ b/src/V3SplitAs.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index 4697a6dda..a4197d74d 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -127,7 +127,7 @@ struct SplitVarImpl { // NODE STATE // AstNodeModule::user1() -> Block number counter for generating unique names - const AstUser1InUse m_user1InUse; // Only used in SplitUnpackedVarVisitor + const VNUser1InUse m_user1InUse; // Only used in SplitUnpackedVarVisitor static AstNodeAssign* newAssign(FileLine* fileline, AstNode* lhsp, AstNode* rhsp, const AstVar* varp) { @@ -141,7 +141,7 @@ struct SplitVarImpl { // These check functions return valid pointer to the reason text if a variable cannot be split. // Check if a var type can be split - static const char* cannotSplitVarTypeReason(AstVarType type) { + static const char* cannotSplitVarTypeReason(VVarType type) { // Only SplitUnpackedVarVisitor can split WREAL. SplitPackedVarVisitor cannot. const bool ok = type == type.VAR || type == type.WIRE || type == type.PORT || type == type.WREAL; @@ -217,6 +217,8 @@ struct SplitVarImpl { insertBeginCore(ap, stmtp, modp); } else if (AstInitial* const ap = VN_CAST(backp, Initial)) { insertBeginCore(ap, stmtp, modp); + } else if (auto* const ap = VN_CAST(backp, Initial)) { + insertBeginCore(ap, stmtp, modp); } } @@ -357,7 +359,7 @@ public: void add(AstVarRef* nodep) { m_refs.insert(nodep); } void add(AstSel* nodep) { m_sels.insert(nodep); } void remove(AstNode* nodep) { - struct Visitor : public AstNVisitor { + struct Visitor : public VNVisitor { RefsInModule& m_parent; virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } virtual void visit(AstVar* nodep) override { m_parent.m_vars.erase(nodep); } @@ -371,7 +373,7 @@ public: } v(*this); v.iterate(nodep); } - void visit(AstNVisitor* visitor) { + void visit(VNVisitor* visitor) { for (AstVar* const varp : m_vars) visitor->iterate(varp); for (AstSel* const selp : m_sels) { // If m_refs includes VarRef from ArraySel, remove it @@ -395,7 +397,7 @@ public: using SplitVarRefsMap = std::map; -class SplitUnpackedVarVisitor final : public AstNVisitor, public SplitVarImpl { +class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl { using VarSet = std::set; VarSet m_foundTargetVar; UnpackRefMap m_refs; @@ -435,12 +437,12 @@ class SplitUnpackedVarVisitor final : public AstNVisitor, public SplitVarImpl { iterate(nodep); } } - void pushDeletep(AstNode* nodep) { // overriding AstNVisitor::pusDeletep() + void pushDeletep(AstNode* nodep) { // overriding VNVisitor::pusDeletep() UASSERT_OBJ(m_modp, nodep, "Must not nullptr"); m_refsForPackedSplit[m_modp].remove(nodep); - AstNVisitor::pushDeletep(nodep); + VNVisitor::pushDeletep(nodep); } - AstVar* newVar(FileLine* fl, AstVarType type, const std::string& name, AstNodeDType* dtp) { + AstVar* newVar(FileLine* fl, VVarType type, const std::string& name, AstNodeDType* dtp) { AstVar* const varp = new AstVar{fl, type, name, dtp}; UASSERT_OBJ(m_modp, varp, "Must not nullptr"); m_refsForPackedSplit[m_modp].add(varp); @@ -617,7 +619,7 @@ class SplitUnpackedVarVisitor final : public AstNVisitor, public SplitVarImpl { // variable can be added. insertBeginIfNecessary(assignp, m_modp); } - AstVar* const varp = newVar(fl, AstVarType::VAR, name, dtypep); + AstVar* const varp = newVar(fl, VVarType::VAR, name, dtypep); // Variable will be registered in the caller side. UINFO(3, varp->prettyNameQ() << " is created lsb:" << dtypep->lo() << " msb:" << dtypep->hi() << "\n"); @@ -699,7 +701,7 @@ class SplitUnpackedVarVisitor final : public AstNVisitor, public SplitVarImpl { // Unpacked array is traced as var(idx), not var[idx]. const std::string name = varp->name() + AstNode::encodeName('(' + cvtToStr(i + dtypep->lo()) + ')'); - AstVar* const newp = newVar(varp->fileline(), AstVarType::VAR, name, subTypep); + AstVar* const newp = newVar(varp->fileline(), VVarType::VAR, name, subTypep); newp->propagateAttrFrom(varp); // If varp is an IO, varp will remain and will be traced. newp->trace(!varp->isIO() && varp->isTrace()); @@ -958,7 +960,7 @@ public: } }; -class SplitPackedVarVisitor final : public AstNVisitor, public SplitVarImpl { +class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { AstNetlist* const m_netp; const AstNodeModule* m_modp = nullptr; // Current module (just for log) int m_numSplit = 0; // Total number of split variables @@ -1089,11 +1091,11 @@ class SplitPackedVarVisitor final : public AstNVisitor, public SplitVarImpl { AstBasicDType* dtypep; switch (basicp->keyword()) { - case AstBasicDTypeKwd::BIT: + case VBasicDTypeKwd::BIT: dtypep = new AstBasicDType{varp->subDTypep()->fileline(), VFlagBitPacked(), newvar.bitwidth()}; break; - case AstBasicDTypeKwd::LOGIC: + case VBasicDTypeKwd::LOGIC: dtypep = new AstBasicDType{varp->subDTypep()->fileline(), VFlagLogicPacked(), newvar.bitwidth()}; break; @@ -1101,7 +1103,7 @@ class SplitPackedVarVisitor final : public AstNVisitor, public SplitVarImpl { } dtypep->rangep(new AstRange{ varp->fileline(), VNumRange{newvar.msb(), newvar.lsb(), basicp->littleEndian()}}); - newvar.varp(new AstVar{varp->fileline(), AstVarType::VAR, name, dtypep}); + newvar.varp(new AstVar{varp->fileline(), VVarType::VAR, name, dtypep}); newvar.varp()->propagateAttrFrom(varp); newvar.varp()->funcLocal(varp->isFuncLocal() || varp->isFuncReturn()); // Enable this line to trace split variable directly: diff --git a/src/V3SplitVar.h b/src/V3SplitVar.h index b952f8f5a..1e0f494f4 100644 --- a/src/V3SplitVar.h +++ b/src/V3SplitVar.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Stats.cpp b/src/V3Stats.cpp index 172c1b642..4eeda8e53 100644 --- a/src/V3Stats.cpp +++ b/src/V3Stats.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,7 +30,7 @@ //###################################################################### // Stats class functions -class StatsVisitor final : public AstNVisitor { +class StatsVisitor final : public VNVisitor { private: // NODE STATE/TYPES @@ -48,7 +48,7 @@ private: bool m_tracingCall; // Iterating into a CCall to a CFunc std::vector m_statTypeCount; // Nodes of given type - VDouble0 m_statAbove[AstType::_ENUM_END][AstType::_ENUM_END]; // Nodes of given type + VDouble0 m_statAbove[VNType::_ENUM_END][VNType::_ENUM_END]; // Nodes of given type std::array m_statPred; // Nodes of given type VDouble0 m_statInstr; // Instruction count VDouble0 m_statInstrFast; // Instruction count, non-slow() eval functions only @@ -214,7 +214,7 @@ public: m_instrs = 0; m_tracingCall = false; // Initialize arrays - m_statTypeCount.resize(AstType::_ENUM_END); + m_statTypeCount.resize(VNType::_ENUM_END); // Process iterate(nodep); } @@ -247,19 +247,19 @@ public: } } // Node types - for (int type = 0; type < AstType::_ENUM_END; type++) { + for (int type = 0; type < VNType::_ENUM_END; type++) { const double count = double(m_statTypeCount.at(type)); if (count != 0.0) { - V3Stats::addStat(m_stage, string("Node count, ") + AstType(type).ascii(), count); + V3Stats::addStat(m_stage, string("Node count, ") + VNType(type).ascii(), count); } } - for (int type = 0; type < AstType::_ENUM_END; type++) { - for (int type2 = 0; type2 < AstType::_ENUM_END; type2++) { + for (int type = 0; type < VNType::_ENUM_END; type++) { + for (int type2 = 0; type2 < VNType::_ENUM_END; type2++) { const double count = double(m_statAbove[type][type2]); if (count != 0.0) { V3Stats::addStat(m_stage, - (string("Node pairs, ") + AstType(type).ascii() + "_" - + AstType(type2).ascii()), + (string("Node pairs, ") + VNType(type).ascii() + "_" + + VNType(type2).ascii()), count); } } diff --git a/src/V3Stats.h b/src/V3Stats.h index 77831e151..f8bfb6231 100644 --- a/src/V3Stats.h +++ b/src/V3Stats.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp index 2a7a66987..86dfe15f7 100644 --- a/src/V3StatsReport.cpp +++ b/src/V3StatsReport.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3String.cpp b/src/V3String.cpp index b76043fd4..dcdb0a042 100644 --- a/src/V3String.cpp +++ b/src/V3String.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3String.h b/src/V3String.h index e028561f3..fd349f9ae 100644 --- a/src/V3String.h +++ b/src/V3String.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp index 0c8c426a9..ff8122533 100644 --- a/src/V3Subst.cpp +++ b/src/V3Subst.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,7 +36,7 @@ //###################################################################### // Common debugging baseclass -class SubstBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class SubstBaseVisitor VL_NOT_FINAL : public VNVisitor { public: VL_DEBUG_FUNC; // Declare debug() }; @@ -117,7 +117,7 @@ public: m_words[word].m_complex = true; } void assignComplex() { m_whole.m_complex = true; } - void consumeWhole() { //==consumeComplex as we don't know the difference + void consumeWhole() { // ==consumeComplex as we don't know the difference m_whole.m_use = true; } void consumeWord(int word) { @@ -227,8 +227,8 @@ private: // Passed to SubstUseVisitor // AstVar::user1p -> SubstVar* for usage var, 0=not set yet // AstVar::user2 -> int step number for last assignment, 0=not set yet - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; // STATE std::vector m_entryps; // Nodes to delete when we are finished diff --git a/src/V3Subst.h b/src/V3Subst.h index a4a8a8b91..7dbc2d335 100644 --- a/src/V3Subst.h +++ b/src/V3Subst.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3SymTable.h b/src/V3SymTable.h index 160e9cc57..a594a4541 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -26,9 +26,11 @@ #include "V3String.h" #include -#include #include +#include #include +#include +#include class VSymGraph; class VSymEnt; diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index 465d53fdc..4032a0622 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -11,7 +11,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -28,21 +28,21 @@ #include "V3Graph.h" #include "V3TSP.h" +#include #include #include #include -#include #include #include -#include #include #include +#include //###################################################################### // Support classes namespace V3TSP { -static unsigned edgeIdNext = 0; +static uint32_t edgeIdNext = 0; static void selfTestStates(); static void selfTestString(); @@ -73,6 +73,8 @@ public: // TYPES using Vertex = TspVertexTmpl; + enum VertexState : uint32_t { CLEAR = 0, MST_VISITED = 1, UNMATCHED_ODD = 2 }; + // MEMBERS std::unordered_map m_vertices; // T_Key to Vertex lookup map @@ -94,7 +96,10 @@ public: // a matched pairs of opposite-directional edges to represent // each non-directional edge: void addEdge(const T_Key& from, const T_Key& to, int cost) { +#if VL_DEBUG // Hot, so only in debug UASSERT(from != to, "Adding edge would form a loop"); + UASSERT(cost >= 0, "Negative weight edge"); +#endif Vertex* const fp = findVertex(from); Vertex* const tp = findVertex(to); @@ -102,12 +107,20 @@ public: // The only time we may create duplicate edges is when // combining the MST with the perfect-matched pairs, // and in that case, we want to permit duplicate edges. - const unsigned edgeId = ++V3TSP::edgeIdNext; + const uint32_t edgeId = ++V3TSP::edgeIdNext; - // Record the 'id' which identifies a single bidir edge - // in the user field of each V3GraphEdge: - (new V3GraphEdge(this, fp, tp, cost))->user(edgeId); - (new V3GraphEdge(this, tp, fp, cost))->user(edgeId); + // We want to be able to compare edges quickly for a total + // ordering, so pre-compute a sorting key and store it in + // the edge user field. We also want easy access to the 'id' + // which uniquely identifies a single bidir edge. Luckily we + // can do both efficiently. + const uint64_t userValue = (static_cast(cost) << 32) | edgeId; + (new V3GraphEdge(this, fp, tp, cost))->user(userValue); + (new V3GraphEdge(this, tp, fp, cost))->user(userValue); + } + + inline static uint32_t getEdgeId(const V3GraphEdge* edgep) { + return static_cast(edgep->user()); } bool empty() const { return m_vertices.empty(); } @@ -118,100 +131,121 @@ public: return vertices; } - class EdgeCmp final { - // Provides a deterministic compare for outgoing V3GraphEdge's - // to be used in Prim's algorithm below. Also used in the - // perfectMatching() routine. - public: - // CONSTRUCTORS - EdgeCmp() = default; - // METHODS - bool operator()(const V3GraphEdge* ap, const V3GraphEdge* bp) { - const int aCost = ap->weight(); - const int bCost = bp->weight(); - // Sort first on cost, lowest cost edges first: - if (aCost < bCost) return true; - if (bCost < aCost) return false; - // Costs are equal. Compare edgeId's which should be unique. - return ap->user() < bp->user(); - } +private: + // We will keep sorted lists of edges as vectors + using EdgeList = std::vector; - private: - VL_UNCOPYABLE(EdgeCmp); + inline static bool edgeCmp(const V3GraphEdge* ap, const V3GraphEdge* bp) { + // We pre-computed these when adding the edge to sort first by cost, then by identity + return ap->user() > bp->user(); + } + + struct EdgeListCmp final { + bool operator()(const EdgeList* ap, const EdgeList* bp) const { + // Simply compare heads + return edgeCmp(bp->back(), ap->back()); + } }; - static Vertex* castVertexp(V3GraphVertex* vxp) { return dynamic_cast(vxp); } + inline static Vertex* castVertexp(V3GraphVertex* vxp) { return static_cast(vxp); } +public: // From *this, populate *mstp with the minimum spanning tree. // *mstp must be initially empty. void makeMinSpanningTree(TspGraphTmpl* mstp) { UASSERT(mstp->empty(), "Output graph must start empty"); // Use Prim's algorithm to efficiently construct the MST. - std::unordered_set visited_set; - EdgeCmp cmp; - using PendingEdgeSet = std::set; - // This is the set of pending edges from visited to unvisited - // nodes. - PendingEdgeSet pendingEdges(cmp); - - vluint32_t vertCount = 0; + uint32_t vertCount = 0; for (V3GraphVertex* vxp = verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { mstp->addVertex(castVertexp(vxp)->key()); vertCount++; } - // Choose an arbitrary start vertex and visit it; - // all incident edges from this vertex go into a pending edge set. - Vertex* const start_vertexp = castVertexp(verticesBeginp()); - visited_set.insert(start_vertexp); - for (V3GraphEdge* edgep = start_vertexp->outBeginp(); edgep; edgep = edgep->outNextp()) { - pendingEdges.insert(edgep); - } + // Allocate storage for per vertex edge lists up front. + std::vector allocatedEdgeLists{vertCount}; + + // Index of vertex in visitation order (used for indexing allocatedEdgeLists) + uint32_t vertIdx = 0; + + // We keep pending edges as a sorted set of sorted vectors. This allows us to find the + // lowest cost edge quickly, while also reducing the cost of inserting batches of new + // edges, which is what we need in this algorithm. + std::set pendingEdgeListps; + + const auto visit = [&](V3GraphVertex* vtxp) { +#ifdef VL_DEBUG // Very hot, so only in debug + UASSERT(vtxp->user() == VertexState::CLEAR, "Vertex visited twice"); +#endif + // Mark vertex as visited + vtxp->user(VertexState::MST_VISITED); + // Allocate new edge list + EdgeList* const newEdgesp = &allocatedEdgeLists[vertIdx++]; + // Gather out edges of this vertex + for (V3GraphEdge* edgep = vtxp->outBeginp(); edgep; edgep = edgep->outNextp()) { + // Don't add edges leading to vertices we already visited. This is a highly + // connected graph, so this greatly reduces the cost of maintaining the pending + // set. + if (edgep->top()->user() == VertexState::MST_VISITED) continue; + newEdgesp->push_back(edgep); + } + // If no relevant out edges, then we are done + if (newEdgesp->empty()) return; + // Sort new edge list + std::sort(newEdgesp->begin(), newEdgesp->end(), edgeCmp); + // Add edge list to pending set + pendingEdgeListps.insert(newEdgesp); + }; + + // To start, choose an arbitrary vertex and visit it. + visit(verticesBeginp()); // Repeatedly find the least costly edge in the pending set. // If it connects to an unvisited node, visit that node and update // the pending edge set. If it connects to an already visited node, // discard it and repeat again. - unsigned edges_made = 0; - while (!pendingEdges.empty()) { - const auto firstIt = pendingEdges.cbegin(); - const V3GraphEdge* bestEdgep = *firstIt; - pendingEdges.erase(firstIt); + while (!pendingEdgeListps.empty()) { + // Grab lowest cost edge list + auto it = pendingEdgeListps.begin(); - // bestEdgep->fromp() should be already seen - Vertex* const from_vertexp = castVertexp(bestEdgep->fromp()); - UASSERT(visited_set.find(from_vertexp) != visited_set.end(), "Can't find vertex"); + // Grab lowest cost edge + EdgeList* const bestEdgeListp = *it; + const V3GraphEdge* const bestEdgep = bestEdgeListp->back(); - // If the neighbor is not yet visited, visit it and add its edges - // to the pending set. + // Remove the lowest cost edge list. We will remove its lowest cost element, and either + // we are done with (if it had a single element) it in which case it will be discarded, + // or the cost of the new head element might be different, so we will need to re-insert + // it in the right place. In either case, it needs to be removed. + pendingEdgeListps.erase(it); + + // If the lowest cost edge list is not a singleton list, then pop the lowest cost + // edge and re-insert the remaining edge list into the pending set. + if (bestEdgeListp->size() > 1) { + bestEdgeListp->pop_back(); + pendingEdgeListps.insert(bestEdgeListp); + } + + // Grab the target vertex Vertex* const neighborp = castVertexp(bestEdgep->top()); - if (visited_set.find(neighborp) == visited_set.end()) { - const int bestCost = bestEdgep->weight(); - UINFO(6, "bestCost = " << bestCost << " from " << from_vertexp->key() << " to " - << neighborp->key() << endl); + + // If the neighbour is not yet visited + if (neighborp->user() == VertexState::CLEAR) { + // Visit it + visit(neighborp); // Create the edge in our output MST graph - mstp->addEdge(from_vertexp->key(), neighborp->key(), bestCost); - edges_made++; + Vertex* const from_vertexp = castVertexp(bestEdgep->fromp()); + mstp->addEdge(from_vertexp->key(), neighborp->key(), bestEdgep->weight()); - // Mark this vertex as visited - visited_set.insert(neighborp); - - // Update the pending edges with new edges - for (V3GraphEdge* edgep = neighborp->outBeginp(); edgep; - edgep = edgep->outNextp()) { - pendingEdges.insert(edgep); - } - } else { - UINFO(6, - "Discarding edge to already-visited neighbor " << neighborp->key() << endl); +#if VL_DEBUG // Very hot loop, so only in debug + UASSERT(from_vertexp->user() == MST_VISITED, + "bestEdgep->fromp() should be already seen"); +#endif } } - UASSERT(edges_made + 1 == vertCount, "Algorithm failed"); - UASSERT(visited_set.size() == vertCount, "Algorithm failed"); + UASSERT(vertIdx == vertCount, "Should have visited all vertices"); } // Populate *outp with a minimal perfect matching of *this. @@ -219,16 +253,14 @@ public: void perfectMatching(const std::vector& oddKeys, TspGraphTmpl* outp) { UASSERT(outp->empty(), "Output graph must start empty"); - std::list odds = keysToVertexList(oddKeys); - std::unordered_set unmatchedOdds; - using VertexListIt = typename std::list::iterator; - for (VertexListIt it = odds.begin(); it != odds.end(); ++it) { - outp->addVertex((*it)->key()); - unmatchedOdds.insert(*it); - } - + const std::list& odds = keysToVertexList(oddKeys); UASSERT(odds.size() % 2 == 0, "number of odd-order nodes should be even"); + for (Vertex* const vtxp : odds) { + outp->addVertex(vtxp->key()); + vtxp->user(VertexState::UNMATCHED_ODD); + } + // TODO: The true Chrisofides algorithm calls for minimum-weight // perfect matching. Instead, we have a simple greedy algorithm // which might get close to the minimum, maybe, with luck? @@ -241,46 +273,54 @@ public: // ----- - // Reuse the comparator from Prim's routine. The logic is the same - // here. Note that the two V3GraphEdge's representing a single - // bidir edge will collide in the pendingEdges set here, but this - // is OK, we'll ignore the direction on the edge anyway. - EdgeCmp cmp; - using PendingEdgeSet = std::set; - PendingEdgeSet pendingEdges(cmp); + // Gather and sort all edges. We use a vector then sort, because this is faster than a + // sorted set. Reuse the comparator from Prim's routine (note it a 'greater', not a + // 'lesser' comparator). The logic is the same here. + // + // Note that there are two V3GraphEdge's representing a single bidir edge. While we could + // just add both to the pending list and get the same result, we will only add one (based + // on fast pointer comparison - this still yields deterministic results), in order to + // reduce the size of the working set. + std::vector pendingEdges; - for (VertexListIt it = odds.begin(); it != odds.end(); ++it) { - for (V3GraphEdge* edgep = (*it)->outBeginp(); edgep; edgep = edgep->outNextp()) { - pendingEdges.insert(edgep); + for (Vertex* const fromp : odds) { + for (V3GraphEdge* edgep = fromp->outBeginp(); edgep; edgep = edgep->outNextp()) { + Vertex* const top = castVertexp(edgep->top()); + // There are two edges (in both directions) between these two vertices. Keep one. + if (fromp > top) continue; + // We only care about edges between the odd-order vertices + if (top->user() != VertexState::UNMATCHED_ODD) continue; + // Add to candidate list + pendingEdges.push_back(edgep); } } + // Sort reverse iterators. This yields ascending order with a 'greater' comparator. + std::sort(pendingEdges.rbegin(), pendingEdges.rend(), edgeCmp); + // Iterate over all edges, in order from low to high cost. // For any edge whose ends are both odd-order vertices which // haven't been matched yet, match them. - for (typename PendingEdgeSet::iterator it = pendingEdges.begin(); it != pendingEdges.end(); - ++it) { - Vertex* const fromp = castVertexp((*it)->fromp()); - Vertex* const top = castVertexp((*it)->top()); - if ((unmatchedOdds.find(fromp) != unmatchedOdds.end()) - && (unmatchedOdds.find(top) != unmatchedOdds.end())) { - outp->addEdge(fromp->key(), top->key(), (*it)->weight()); - unmatchedOdds.erase(fromp); - unmatchedOdds.erase(top); + for (V3GraphEdge* const edgep : pendingEdges) { + Vertex* const fromp = castVertexp(edgep->fromp()); + Vertex* const top = castVertexp(edgep->top()); + if (fromp->user() == VertexState::UNMATCHED_ODD + && top->user() == VertexState::UNMATCHED_ODD) { + outp->addEdge(fromp->key(), top->key(), edgep->weight()); + fromp->user(VertexState::CLEAR); + top->user(VertexState::CLEAR); } } - UASSERT(unmatchedOdds.empty(), "Algorithm should have processed all vertices"); } void combineGraph(const TspGraphTmpl& g) { - std::unordered_set edges_done; + std::unordered_set edges_done; for (V3GraphVertex* vxp = g.verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { const Vertex* const fromp = castVertexp(vxp); for (V3GraphEdge* edgep = fromp->outBeginp(); edgep; edgep = edgep->outNextp()) { const Vertex* const top = castVertexp(edgep->top()); - if (edges_done.find(edgep->user()) == edges_done.end()) { + if (edges_done.insert(getEdgeId(edgep)).second) { addEdge(fromp->key(), top->key(), edgep->weight()); - edges_done.insert(edgep->user()); } } } @@ -298,7 +338,7 @@ public: // Look for an arbitrary edge we've not yet marked for (V3GraphEdge* edgep = cur_vertexp->outBeginp(); edgep; edgep = edgep->outNextp()) { - const vluint32_t edgeId = edgep->user(); + const vluint32_t edgeId = getEdgeId(edgep); if (markedEdgesp->end() == markedEdgesp->find(edgeId)) { // This edge is not yet marked, so follow it. markedEdgesp->insert(edgeId); @@ -322,7 +362,7 @@ public: recursed = false; // Look for an arbitrary edge at vxp we've not yet marked for (V3GraphEdge* edgep = vxp->outBeginp(); edgep; edgep = edgep->outNextp()) { - const vluint32_t edgeId = edgep->user(); + const vluint32_t edgeId = getEdgeId(edgep); if (markedEdgesp->end() == markedEdgesp->find(edgeId)) { UINFO(6, "Recursing.\n"); findEulerTourRecurse(markedEdgesp, vxp, sortedOutp); @@ -348,7 +388,7 @@ public: os << " " << tspvp->key() << '\n'; for (V3GraphEdge* edgep = tspvp->outBeginp(); edgep; edgep = edgep->outNextp()) { const Vertex* const neighborp = castVertexp(edgep->top()); - os << " has edge " << edgep->user() << " to " << neighborp->key() << '\n'; + os << " has edge " << getEdgeId(edgep) << " to " << neighborp->key() << '\n'; } } } diff --git a/src/V3TSP.h b/src/V3TSP.h index 956fb97d2..8df9a2f2f 100644 --- a/src/V3TSP.h +++ b/src/V3TSP.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -23,6 +23,8 @@ #include "V3Error.h" +#include + namespace V3TSP { // Perform a "Traveling Salesman Problem" optimizing sort // on any type you like -- so long as inherits from TspStateBase. diff --git a/src/V3Table.cpp b/src/V3Table.cpp index 95aaa2390..3233e39fe 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -144,7 +144,7 @@ public: //###################################################################### // Table class functions -class TableVisitor final : public AstNVisitor { +class TableVisitor final : public VNVisitor { private: // NODE STATE // Cleared on each always/assignw @@ -247,7 +247,7 @@ private: // We will need a table index variable, create it here. AstVar* const indexVarp - = new AstVar(fl, AstVarType::BLOCKTEMP, "__Vtableidx" + cvtToStr(m_modTables), + = new AstVar(fl, VVarType::BLOCKTEMP, "__Vtableidx" + cvtToStr(m_modTables), VFlagBitPacked(), m_inWidthBits); m_modp->addStmtp(indexVarp); AstVarScope* const indexVscp = new AstVarScope(indexVarp->fileline(), m_scopep, indexVarp); diff --git a/src/V3Table.h b/src/V3Table.h index a5574294a..3051a690e 100644 --- a/src/V3Table.h +++ b/src/V3Table.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Task.cpp b/src/V3Task.cpp index b9aa8ebc7..217a58e1f 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -91,15 +91,15 @@ public: //###################################################################### -class TaskStateVisitor final : public AstNVisitor { +class TaskStateVisitor final : public VNVisitor { private: // NODE STATE // Output: // AstNodeFTask::user3p // AstScope* this FTask is under // AstNodeFTask::user4p // GraphFTaskVertex* this FTask is under // AstVar::user4p // GraphFTaskVertex* this variable is declared in - const AstUser3InUse m_inuser3; - const AstUser4InUse m_inuser4; + const VNUser3InUse m_inuser3; + const VNUser4InUse m_inuser4; // TYPES using VarToScopeMap = std::map, AstVarScope*>; @@ -112,7 +112,7 @@ private: AstClass* m_classp = nullptr; // Current class V3Graph m_callGraph; // Task call graph TaskBaseVertex* m_curVxp; // Current vertex we're adding to - std::vector m_initialps; // Initial blocks to move + std::vector m_initialps; // Initial blocks to move public: // METHODS @@ -140,7 +140,10 @@ public: getFTaskVertex(nodep)->cFuncp(cfuncp); } void checkPurity(AstNodeFTask* nodep) { checkPurity(nodep, getFTaskVertex(nodep)); } + +private: void checkPurity(AstNodeFTask* nodep, TaskBaseVertex* vxp) { + if (nodep->recursive()) return; // Impure, but no warning if (!vxp->pure()) { nodep->v3warn( IMPURE, "Unsupported: External variable referenced by non-inlined function/task: " @@ -156,8 +159,6 @@ public: checkPurity(nodep, static_cast(edgep->top())); } } - -private: TaskFTaskVertex* getFTaskVertex(AstNodeFTask* nodep) { if (!nodep->user4p()) nodep->user4p(new TaskFTaskVertex(&m_callGraph, nodep)); return static_cast(nodep->user4u().toGraphVertex()); @@ -209,6 +210,7 @@ private: m_curVxp = getFTaskVertex(nodep); if (nodep->dpiImport()) m_curVxp->noInline(true); if (nodep->classMethod()) m_curVxp->noInline(true); // Until V3Task supports it + if (nodep->recursive()) m_curVxp->noInline(true); if (nodep->isConstructor()) { m_curVxp->noInline(true); m_ctorp = nodep; @@ -219,7 +221,7 @@ private: } } virtual void visit(AstPragma* nodep) override { - if (nodep->pragType() == AstPragmaType::NO_INLINE_TASK) { + if (nodep->pragType() == VPragmaType::NO_INLINE_TASK) { // Just mark for the next steps, and we're done with it. m_curVxp->noInline(true); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); @@ -246,7 +248,7 @@ private: iterateChildren(nodep); } UASSERT_OBJ(m_ctorp, nodep, "class constructor missing"); // LinkDot always makes it - for (AstInitial* initialp : m_initialps) { + for (AstInitialAutomatic* initialp : m_initialps) { if (AstNode* const newp = initialp->bodysp()) { newp->unlinkFrBackWithNext(); if (!m_ctorp->stmtsp()) { @@ -261,7 +263,7 @@ private: m_ctorp = nullptr; m_classp = nullptr; } - virtual void visit(AstInitial* nodep) override { + virtual void visit(AstInitialAutomatic* nodep) override { m_initialps.push_back(nodep); iterateChildren(nodep); } @@ -284,41 +286,6 @@ public: VL_UNCOPYABLE(TaskStateVisitor); }; -//###################################################################### - -class TaskRelinkVisitor final : public AstNVisitor { - // Replace varrefs with new var pointer -private: - // NODE STATE - // Input: - // AstVar::user2p // AstVarScope* to replace varref with - - // VISITORS - virtual void visit(AstVarRef* nodep) override { - // Similar code in V3Inline - if (nodep->varp()->user2p()) { // It's being converted to an alias. - UINFO(9, - " relinkVar " << cvtToHex(nodep->varp()->user2p()) << " " << nodep << endl); - AstVarScope* const newvscp = VN_AS(nodep->varp()->user2p(), VarScope); - UASSERT_OBJ(newvscp, nodep, "not linked"); - nodep->varScopep(newvscp); - nodep->varp(nodep->varScopep()->varp()); - nodep->name(nodep->varp()->name()); - } - iterateChildren(nodep); - } - - //-------------------- - virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - explicit TaskRelinkVisitor(AstBegin* nodep) { // Passed temporary tree - iterate(nodep); - } - virtual ~TaskRelinkVisitor() override = default; -}; - //###################################################################### // DPI related utility functions @@ -340,7 +307,7 @@ struct TaskDpiUtils { static bool dpiToInternalFrStmt(AstVar* portp, const string& frName, string& frstmt, string& ket) { ket.clear(); - if (portp->basicp() && portp->basicp()->keyword() == AstBasicDTypeKwd::CHANDLE) { + if (portp->basicp() && portp->basicp()->keyword() == VBasicDTypeKwd::CHANDLE) { frstmt = "VL_CVT_VP_Q(" + frName; ket = ")"; } else if ((portp->basicp() && portp->basicp()->isDpiPrimitive())) { @@ -363,52 +330,19 @@ struct TaskDpiUtils { } }; -//###################################################################### -// Gather non-local variables written by an AstCFunc - -class TaskGatherWrittenVisitor final : public AstNVisitor { - // NODE STATE - // AstVarScope::user5 -> Already considered variable - const AstUser5InUse m_user5InUse; - - std::vector m_writtenVariables; // Variables written - - virtual void visit(AstVarRef* nodep) override { - if (nodep->access().isReadOnly()) return; // Ignore read reference - AstVarScope* const varScopep = nodep->varScopep(); - if (varScopep->user5()) return; // Ignore already processed variable - varScopep->user5(true); // Mark as already processed - // Note: We are ignoring function locals as they should not be referenced anywhere outside - // of the enclosing AstCFunc, and therefore they are irrelevant for code ordering. This is - // simply an optimization to avoid adding useless nodes to the ordering graph in V3Order. - if (varScopep->varp()->isFuncLocal()) return; - m_writtenVariables.push_back(varScopep); - } - virtual void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } - - explicit TaskGatherWrittenVisitor(AstNode* nodep) { iterate(nodep); } - -public: - // Gather all written non-local variables - static const std::vector gather(AstCFunc* funcp) { - const TaskGatherWrittenVisitor visitor{funcp}; - return std::move(visitor.m_writtenVariables); - } -}; - //###################################################################### // Task state, as a visitor of each AstNode -class TaskVisitor final : public AstNVisitor { +class TaskVisitor final : public VNVisitor { private: // NODE STATE // Each module: // AstNodeFTask::user1 // True if its been expanded // Each funccall - // to TaskRelinkVisitor: + // to 'relink' function: // AstVar::user2p // AstVarScope* to replace varref with - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; // TYPES enum InsertMode : uint8_t { @@ -432,17 +366,16 @@ private: VL_DEBUG_FUNC; // Declare debug() AstVarScope* createFuncVar(AstCFunc* funcp, const string& name, AstVar* examplep) { - AstVar* const newvarp - = new AstVar(funcp->fileline(), AstVarType::BLOCKTEMP, name, examplep); + AstVar* const newvarp = new AstVar(funcp->fileline(), VVarType::BLOCKTEMP, name, examplep); newvarp->funcLocal(true); funcp->addInitsp(newvarp); AstVarScope* const newvscp = new AstVarScope(funcp->fileline(), m_scopep, newvarp); m_scopep->addVarp(newvscp); return newvscp; } - AstVarScope* createInputVar(AstCFunc* funcp, const string& name, AstBasicDTypeKwd kwd) { - AstVar* const newvarp = new AstVar(funcp->fileline(), AstVarType::BLOCKTEMP, name, - funcp->findBasicDType(kwd)); + AstVarScope* createInputVar(AstCFunc* funcp, const string& name, VBasicDTypeKwd kwd) { + AstVar* const newvarp + = new AstVar(funcp->fileline(), VVarType::BLOCKTEMP, name, funcp->findBasicDType(kwd)); newvarp->funcLocal(true); newvarp->direction(VDirection::INPUT); funcp->addArgsp(newvarp); @@ -460,7 +393,7 @@ private: // We choose to do it under whichever called this function, which results // in more cache locality. AstVar* const newvarp - = new AstVar{invarp->fileline(), AstVarType::BLOCKTEMP, name, invarp}; + = new AstVar{invarp->fileline(), VVarType::BLOCKTEMP, name, invarp}; newvarp->funcLocal(false); newvarp->propagateAttrFrom(invarp); m_modp->addStmtp(newvarp); @@ -470,6 +403,18 @@ private: } } + // Replace varrefs with new var pointer + void relink(AstNode* nodep) { + nodep->foreachAndNext([](AstVarRef* refp) { + if (refp->varp()->user2p()) { // It's being converted to an alias. + AstVarScope* const newvscp = VN_AS(refp->varp()->user2p(), VarScope); + refp->varScopep(newvscp); + refp->varp(refp->varScopep()->varp()); + refp->name(refp->varp()->name()); + } + }); + } + AstNode* createInlinedFTask(AstNodeFTaskRef* refp, const string& namePrefix, AstVarScope* outvscp) { // outvscp is the variable for functions only, if nullptr, it's a task @@ -580,13 +525,7 @@ private: refp->taskp()->fvarp()->user2p(outvscp); } // Replace variable refs - // Iteration requires a back, so put under temporary node - { - AstBegin* const tempp = new AstBegin(beginp->fileline(), "[EditWrapper]", beginp); - const TaskRelinkVisitor visitor{tempp}; - tempp->stmtsp()->unlinkFrBackWithNext(); - VL_DO_DANGLING(tempp->deleteTree(), tempp); - } + relink(beginp); // if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-iotask: "); return beginp; @@ -727,6 +666,24 @@ private: return new AstCStmt(portp->fileline(), stmt); } + void unlinkAndClone(AstNodeFTask* funcp, AstNode* nodep, bool withNext) { + UASSERT_OBJ(nodep, funcp, "null in function object clone"); + VNRelinker relinkHandle; + if (withNext) { + nodep->unlinkFrBackWithNext(&relinkHandle); + } else { + nodep->unlinkFrBack(&relinkHandle); + } + if (funcp->recursive()) { + // Recursive functions require the original argument list to + // still be live for linking purposes. + // The old function gets clone, so that node pointers are mostly + // retained through the V3Task transformations + AstNode* const newp = nodep->cloneTree(withNext); + relinkHandle.relink(newp); + } + } + static AstNode* createAssignInternalToDpi(AstVar* portp, bool isPtr, const string& frSuffix, const string& toSuffix) { const string stmt = V3Task::assignInternalToDpi(portp, isPtr, frSuffix, toSuffix); @@ -1105,7 +1062,7 @@ private: // This flag is set any time a DPI export is invoked, and cleared at the end of eval. FileLine* const fl = m_topScopep->fileline(); AstVar* const varp - = new AstVar{fl, AstVarType::VAR, "__Vdpi_export_trigger", VFlagBitPacked{}, 1}; + = new AstVar{fl, VVarType::VAR, "__Vdpi_export_trigger", VFlagBitPacked{}, 1}; m_topScopep->scopep()->modp()->addStmtp(varp); dpiExportTriggerp = new AstVarScope{fl, m_topScopep->scopep(), varp}; m_topScopep->scopep()->addVarp(dpiExportTriggerp); @@ -1150,7 +1107,7 @@ private: if (ftaskNoInline || nodep->dpiExport()) { portp->funcReturn(false); // Converting return to 'outputs' } - portp->unlinkFrBack(); + unlinkAndClone(nodep, portp, false); rtnvarp = portp; rtnvarp->funcLocal(true); rtnvarp->name(rtnvarp->name() @@ -1233,9 +1190,9 @@ private: } if (nodep->dpiContext()) { // First three args go to dpiContext call - createInputVar(cfuncp, "__Vscopep", AstBasicDTypeKwd::SCOPEPTR); - createInputVar(cfuncp, "__Vfilenamep", AstBasicDTypeKwd::CHARPTR); - createInputVar(cfuncp, "__Vlineno", AstBasicDTypeKwd::INT); + createInputVar(cfuncp, "__Vscopep", VBasicDTypeKwd::SCOPEPTR); + createInputVar(cfuncp, "__Vfilenamep", VBasicDTypeKwd::CHARPTR); + createInputVar(cfuncp, "__Vlineno", VBasicDTypeKwd::INT); } if (nodep->dpiExport()) { @@ -1261,7 +1218,7 @@ private: } else { if (portp->isIO()) { // Move it to new function - portp->unlinkFrBack(); + unlinkAndClone(nodep, portp, false); portp->funcLocal(true); cfuncp->addArgsp(portp); } else { @@ -1283,10 +1240,21 @@ private: if (rtnvarp) cfuncp->addArgsp(rtnvarp); // Move body - AstNode* const bodysp = nodep->stmtsp(); + AstNode* bodysp = nodep->stmtsp(); if (bodysp) { - bodysp->unlinkFrBackWithNext(); - cfuncp->addStmtsp(bodysp); + unlinkAndClone(nodep, bodysp, true); + AstBegin* const tempp = new AstBegin{nodep->fileline(), "[EditWrapper]", bodysp}; + VL_DANGLING(bodysp); + // If we cloned due to recursion, now need to rip out the ports + // (that remained in place) then got cloned + for (AstNode *nextp, *stmtp = tempp->stmtsp(); stmtp; stmtp = nextp) { + nextp = stmtp->nextp(); + if (AstVar* const portp = VN_CAST(stmtp, Var)) { + if (portp->isIO()) portp->unlinkFrBack(); + } + } + if (tempp->stmtsp()) cfuncp->addStmtsp(tempp->stmtsp()->unlinkFrBackWithNext()); + VL_DO_DANGLING(tempp->deleteTree(), tempp); } if (nodep->dpiImport()) bodyDpiImportFunc(nodep, rtnvscp, cfuncp, dpiFuncp); @@ -1296,18 +1264,30 @@ private: rtnvscp->fileline(), new AstVarRef(rtnvscp->fileline(), rtnvscp, VAccess::READ))); } // Replace variable refs - // Iteration requires a back, so put under temporary node - { - AstBegin* const tempp = new AstBegin(cfuncp->fileline(), "[EditWrapper]", cfuncp); - const TaskRelinkVisitor visitor{tempp}; - tempp->stmtsp()->unlinkFrBackWithNext(); - VL_DO_DANGLING(tempp->deleteTree(), tempp); - } + relink(cfuncp); if (cfuncp->dpiExportImpl()) { // Mark all non-local variables written by the DPI exported function as being updated // by DPI exports. This ensures correct ordering and change detection later. - const std::vector writtenps = TaskGatherWrittenVisitor::gather(cfuncp); + + // Gather non-local variables written by the exported function + std::vector writtenps; + { + const VNUser5InUse user5InUse; // AstVarScope::user5 -> Already added variable + cfuncp->foreach([&writtenps](AstVarRef* refp) { + if (refp->access().isReadOnly()) return; // Ignore read reference + AstVarScope* const varScopep = refp->varScopep(); + if (varScopep->user5()) return; // Ignore already added variable + varScopep->user5(true); // Mark as already added + // Note: We are ignoring function locals as they should not be referenced + // anywhere outside of the enclosing AstCFunc, and therefore they are + // irrelevant for code ordering. This is simply an optimization to avoid adding + // useless nodes to the ordering graph in V3Order. + if (varScopep->varp()->isFuncLocal()) return; + writtenps.push_back(varScopep); + }); + } + if (!writtenps.empty()) { AstVarScope* const dpiExportTriggerp = makeDpiExporTrigger(); FileLine* const fl = cfuncp->fileline(); @@ -1456,7 +1436,7 @@ private: if (visitp) iterateAndNextNull(visitp); } virtual void visit(AstNodeFTask* nodep) override { - UINFO(4, " Inline " << nodep << endl); + UINFO(4, " visitFTask " << nodep << endl); VL_RESTORER(m_insMode); VL_RESTORER(m_insStmtp); m_insMode = IM_BEFORE; @@ -1751,9 +1731,9 @@ string V3Task::assignInternalToDpi(AstVar* portp, bool isPtr, const string& frSu } } else { const bool isChandle - = portp->basicp() && portp->basicp()->keyword() == AstBasicDTypeKwd::CHANDLE; + = portp->basicp() && portp->basicp()->keyword() == VBasicDTypeKwd::CHANDLE; const bool isString - = portp->basicp() && portp->basicp()->keyword() == AstBasicDTypeKwd::STRING; + = portp->basicp() && portp->basicp()->keyword() == VBasicDTypeKwd::STRING; const string idx = portp->name() + "__Vidx"; stmt = "for (size_t " + idx + " = 0; " + idx + " < " + cvtToStr(unpackSize) + "; ++" + idx + ") "; diff --git a/src/V3Task.h b/src/V3Task.h index 162801f16..33e11512d 100644 --- a/src/V3Task.h +++ b/src/V3Task.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -23,6 +23,7 @@ #include "V3Error.h" #include "V3Ast.h" +#include #include //============================================================================ diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp index 4c1ade6c0..477d97d2e 100644 --- a/src/V3Trace.cpp +++ b/src/V3Trace.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -162,10 +162,10 @@ private: // AstVarScope::user1() // V3GraphVertex* for this node // AstCCall::user2() // bool; walked next list for other ccalls // Ast*::user3() // TraceActivityVertex* for this node - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; - // AstUser4InUse In V3Hasher via V3DupFinder + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; + // VNUser4InUse In V3Hasher via V3DupFinder // STATE AstNodeModule* m_topModp = nullptr; // Module to add variables to @@ -448,7 +448,7 @@ private: AstNodeDType* const newArrDtp = new AstUnpackArrayDType(flp, newScalarDtp, newArange); v3Global.rootp()->typeTablep()->addTypesp(newArrDtp); AstVar* const newvarp - = new AstVar(flp, AstVarType::MODULETEMP, "__Vm_traceActivity", newArrDtp); + = new AstVar(flp, VVarType::MODULETEMP, "__Vm_traceActivity", newArrDtp); m_topModp->addStmtp(newvarp); AstVarScope* const newvscp = new AstVarScope(flp, m_topScopep, newvarp); m_topScopep->addVarp(newvscp); @@ -591,7 +591,7 @@ private: AstTraceInc* const incp = new AstTraceInc(declp->fileline(), declp, /* full: */ true); subFuncp->addStmtsp(incp); - subStmts += EmitCBaseCounterVisitor(incp).count(); + subStmts += incp->nodeCount(); // Track partitioning nCodes += declp->codeInc(); @@ -659,7 +659,7 @@ private: ifp = new AstIf(flp, condp, nullptr, nullptr); if (!always) ifp->branchPred(VBranchPred::BP_UNLIKELY); subFuncp->addStmtsp(ifp); - subStmts += EmitCBaseCounterVisitor(ifp).count(); + subStmts += ifp->nodeCount(); prevActSet = &actSet; } @@ -667,7 +667,7 @@ private: AstTraceInc* const incp = new AstTraceInc(declp->fileline(), declp, /* full: */ false, baseCode); ifp->addIfsp(incp); - subStmts += EmitCBaseCounterVisitor(incp).count(); + subStmts += incp->nodeCount(); // Track partitioning nCodes += declp->codeInc(); diff --git a/src/V3Trace.h b/src/V3Trace.h index 209ea7582..db130e69c 100644 --- a/src/V3Trace.h +++ b/src/V3Trace.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index db1d60667..5859ff819 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -29,6 +29,62 @@ #include "V3EmitCBase.h" #include "V3Stats.h" +#include +#include +#include +#include + +//###################################################################### +// Utility class to emit path adjustments + +class PathAdjustor final { + FileLine* const m_flp; // FileLine used for created nodes + std::function m_emit; // Function called with adjustment statements + std::vector m_stack{""}; // Stack of current paths + + static constexpr char SEPARATOR = ' '; + +public: + explicit PathAdjustor(FileLine* flp, std::function emit) + : m_flp{flp} + , m_emit{emit} {} + + // Emit Prefix adjustments until the current path is 'newPath' + void adjust(const string& newPath) { + // Move up to enclosing path + unsigned toPop = 0; + while (!VString::startsWith(newPath, m_stack.back())) { + ++toPop; + m_stack.pop_back(); + } + if (toPop) m_emit(new AstTracePopNamePrefix{m_flp, toPop}); + // Move down, one path element at a time + if (newPath != m_stack.back()) { + const string& extraPrefix = newPath.substr(m_stack.back().size()); + size_t begin = 0; + while (true) { + const size_t end = extraPrefix.find(SEPARATOR, begin); + if (end == string::npos) break; + const string& extra = extraPrefix.substr(begin, end + 1 - begin); + m_emit(new AstTracePushNamePrefix{m_flp, extra}); + m_stack.push_back(m_stack.back() + extra); + begin = end + 1; + } + const string& extra = extraPrefix.substr(begin); + if (!extra.empty()) { + m_emit(new AstTracePushNamePrefix{m_flp, extra + SEPARATOR}); + m_stack.push_back(m_stack.back() + extra); + } + } + } + + // Emit Prefix adjustments to unwind the path back to its original state + void unwind() { + const unsigned toPop = m_stack.size() - 1; + if (toPop) m_emit(new AstTracePopNamePrefix{m_flp, toPop}); + } +}; + //###################################################################### // TraceDecl state, as a visitor of each AstNode @@ -37,15 +93,38 @@ private: // NODE STATE // STATE - AstScope* const m_topScopep = v3Global.rootp()->topScopep()->scopep(); // The top AstScope - AstCFunc* m_initFuncp = nullptr; // Trace function being built - AstCFunc* m_initSubFuncp = nullptr; // Trace function being built (under m_init) - int m_initSubStmts = 0; // Number of statements in function - int m_funcNum = 0; // Function number being built - const AstVarScope* m_traVscp = nullptr; // Signal being trace constructed - AstNode* m_traValuep = nullptr; // Signal being traced's value to trace in it - string m_traShowname; // Signal being traced's component name - bool m_interface = false; // Currently tracing an interface + AstTopScope* const m_topScopep; // The singleton AstTopScope + const AstScope* m_currScopep = nullptr; // Current scope being visited + + std::vector m_topFuncps; // Top level trace initialization functions + std::vector m_subFuncps; // Trace sub functions for this scope + int m_topFuncSize = 0; // Size of the top function currently being built + int m_subFuncSize = 0; // Size of the sub function currently being built + const int m_funcSizeLimit // Maximum size of a function + = v3Global.opt.outputSplitCTrace() ? v3Global.opt.outputSplitCTrace() + : std::numeric_limits::max(); + // Trace init sub functions to invoke for path names in the hierarchy. Note path names and + // AstScope instances are not one to one due to the presence of AstIntfRef. + std::map> m_scopeSubFuncps; + + struct Signal final { + AstVarScope* m_vscp; // AstVarScope being traced (non const to allow copy during sorting) + std::string m_path; // Path to enclosing module in hierarchy + std::string m_name; // Name of signal + Signal(AstVarScope* vscp) + : m_vscp{vscp} { + // Compute path in hierarchy and signal name + const string& vcdName = AstNode::vcdName(vscp->varp()->name()); + const size_t pos = vcdName.rfind(' '); + const size_t pathLen = pos == string::npos ? 0 : pos + 1; + m_path = vcdName.substr(0, pathLen); + m_name = vcdName.substr(pathLen); + } + }; + std::vector m_signals; // Signals under current scope + AstVarScope* m_traVscp = nullptr; // Current AstVarScope we are constructing AstTraceDecls for + AstNode* m_traValuep = nullptr; // Value expression for current signal + string m_traName; // Name component for current signal VDouble0 m_statSigs; // Statistic tracking VDouble0 m_statIgnSigs; // Statistic tracking @@ -69,38 +148,44 @@ private: return nullptr; } - AstCFunc* newCFunc(const string& name) { - FileLine* const flp = m_topScopep->fileline(); - AstCFunc* const funcp = new AstCFunc(flp, name, m_topScopep); - string argTypes = v3Global.opt.traceClassBase() + "* tracep"; - if (m_interface) argTypes += ", int scopet, const char* scopep"; - funcp->argTypes(argTypes); + AstCFunc* newCFunc(FileLine* flp, const string& name) { + AstScope* const topScopep = m_topScopep->scopep(); + AstCFunc* const funcp = new AstCFunc{flp, name, topScopep}; + funcp->argTypes(v3Global.opt.traceClassBase() + "* tracep"); funcp->isTrace(true); funcp->isStatic(false); funcp->isLoose(true); funcp->slow(true); - m_topScopep->addActivep(funcp); - UINFO(5, " Newfunc " << funcp << endl); + topScopep->addActivep(funcp); return funcp; } - void callCFuncSub(AstCFunc* basep, AstCFunc* funcp, AstIntfRef* irp) { - AstCCall* const callp = new AstCCall(funcp->fileline(), funcp); - if (irp) { - callp->argTypes("tracep, VLT_TRACE_SCOPE_INTERFACE"); - callp->addArgsp(irp->unlinkFrBack()); - } else { - callp->argTypes("tracep"); + + void addToTopFunc(AstNodeStmt* stmtp) { + if (m_topFuncSize > m_funcSizeLimit || m_topFuncps.empty()) { + m_topFuncSize = 0; + // + const string n = cvtToStr(m_topFuncps.size()); + const string name{"trace_init_top__" + n}; + AstCFunc* const funcp = newCFunc(m_topScopep->fileline(), name); + m_topFuncps.push_back(funcp); } - basep->addStmtsp(callp); + m_topFuncps.back()->addStmtsp(stmtp); + m_topFuncSize += stmtp->nodeCount(); } - AstCFunc* newCFuncSub(AstCFunc* basep) { - FileLine* const fl = basep->fileline(); - const string name = "trace_init_sub_" + cvtToStr(m_funcNum++); - AstCFunc* const funcp = newCFunc(name); - funcp->addInitsp(new AstCStmt(fl, "const int c = vlSymsp->__Vm_baseCode;\n")); - funcp->addInitsp(new AstCStmt(fl, "if (false && tracep && c) {} // Prevent unused\n")); - if (!m_interface) callCFuncSub(basep, funcp, nullptr); - return funcp; + + void addToSubFunc(AstNodeStmt* stmtp) { + if (m_subFuncSize > m_funcSizeLimit || m_subFuncps.empty()) { + m_subFuncSize = 0; + // + FileLine* const flp = m_currScopep->fileline(); + const string n = cvtToStr(m_subFuncps.size()); + const string name{"trace_init_sub__" + m_currScopep->nameDotless() + "__" + n}; + AstCFunc* const funcp = newCFunc(flp, name); + funcp->addInitsp(new AstCStmt{flp, "const int c = vlSymsp->__Vm_baseCode;\n"}); + m_subFuncps.push_back(funcp); + } + m_subFuncps.back()->addStmtsp(stmtp); + m_subFuncSize += stmtp->nodeCount(); } std::string getScopeChar(VltTraceScope sct) { return std::string(1, (char)(0x80 + sct)); } @@ -114,114 +199,124 @@ private: } else if (const AstBasicDType* const bdtypep = m_traValuep->dtypep()->basicp()) { bitRange = bdtypep->nrange(); } - AstTraceDecl* const declp - = new AstTraceDecl(m_traVscp->fileline(), m_traShowname, m_traVscp->varp(), - m_traValuep->cloneTree(true), bitRange, arrayRange, m_interface); - UINFO(9, "Decl " << declp << endl); - - if (!m_interface && v3Global.opt.outputSplitCTrace() - && m_initSubStmts > v3Global.opt.outputSplitCTrace()) { - m_initSubFuncp = newCFuncSub(m_initFuncp); - m_initSubStmts = 0; - } - - m_initSubFuncp->addStmtsp(declp); - m_initSubStmts += EmitCBaseCounterVisitor(declp).count(); + addToSubFunc(new AstTraceDecl{m_traVscp->fileline(), m_traName, m_traVscp->varp(), + m_traValuep->cloneTree(false), bitRange, arrayRange}); } + void addIgnore(const char* why) { ++m_statIgnSigs; - m_initSubFuncp->addStmtsp(new AstComment( - m_traVscp->fileline(), "Tracing: " + m_traShowname + " // Ignored: " + why, true)); + addToSubFunc(new AstComment{m_traVscp->fileline(), + "Tracing: " + m_traName + " // Ignored: " + why, true}); } // VISITORS - virtual void visit(AstTopScope* nodep) override { - // Create the trace init function - m_initFuncp = newCFunc("trace_init_top"); - // Create initial sub function - m_initSubFuncp = newCFuncSub(m_initFuncp); - // And find variables - iterateChildren(nodep); - } virtual void visit(AstScope* nodep) override { - const AstCell* const cellp = nodep->aboveCellp(); - if (cellp && VN_IS(cellp->modp(), Iface)) { - AstCFunc* const origSubFunc = m_initSubFuncp; - int origSubStmts = m_initSubStmts; - { - m_interface = true; - m_initSubFuncp = newCFuncSub(origSubFunc); - string scopeName = nodep->prettyName(); - const size_t lastDot = scopeName.find_last_of('.'); - UASSERT_OBJ(lastDot != string::npos, nodep, - "Expected an interface scope name to have at least one dot"); - scopeName = scopeName.substr(0, lastDot + 1); - const size_t scopeLen = scopeName.length(); + UASSERT_OBJ(!m_currScopep, nodep, "Should not nest"); + UASSERT_OBJ(m_subFuncps.empty(), nodep, "Should not nest"); + UASSERT_OBJ(m_signals.empty(), nodep, "Should not nest"); + UASSERT_OBJ(!m_traVscp, nodep, "Should not nest"); + UASSERT_OBJ(m_traName.empty(), nodep, "Should not nest"); - AstIntfRef* nextIrp = cellp->intfRefp(); - // While instead of for loop because interface references will - // be unlinked as we go - while (nextIrp) { - AstIntfRef* const irp = nextIrp; - nextIrp = VN_AS(irp->nextp(), IntfRef); + FileLine* const flp = nodep->fileline(); + m_currScopep = nodep; - const string irpName = irp->prettyName(); - if (scopeLen > irpName.length()) continue; - const string intfScopeName = irpName.substr(0, scopeLen); - if (scopeName != intfScopeName) continue; - callCFuncSub(origSubFunc, m_initSubFuncp, irp); - ++origSubStmts; - } - iterateChildren(nodep); - } - m_initSubFuncp = origSubFunc; - m_initSubStmts = origSubStmts; - m_interface = false; - } else { - iterateChildren(nodep); + // Gather all signals under this AstScope + iterateChildrenConst(nodep); + + // If nothing to trace in this scope, then job done + if (m_signals.empty()) { + m_currScopep = nullptr; + return; } - } - virtual void visit(AstVarScope* nodep) override { - iterateChildren(nodep); - // Prefilter - things that get through this if will either get - // traced or get a comment as to why not traced. - // Generally this equation doesn't need updating, instead use - // varp->isTrace() and/or vscIgnoreTrace. - if ((!nodep->varp()->isTemp() || nodep->varp()->isTrace()) - && !nodep->varp()->isClassMember() && !nodep->varp()->isFuncLocal()) { - UINFO(5, " vsc " << nodep << endl); - const AstVar* const varp = nodep->varp(); - const AstScope* const scopep = nodep->scopep(); - // Compute show name - // This code assumes SPTRACEVCDC_VERSION >= 1330; - // it uses spaces to separate hierarchy components. - if (m_interface) { - m_traShowname = AstNode::vcdName(varp->name()); - } else { - m_traShowname = AstNode::vcdName(scopep->name() + " " + varp->name()); - if (m_traShowname.substr(0, 4) == "TOP ") m_traShowname.erase(0, 4); - } - UASSERT_OBJ(m_initSubFuncp, nodep, "nullptr"); - m_traVscp = nodep; - if (const char* const ignoreReasonp = vscIgnoreTrace(nodep)) { + // Sort signals, first by enclosing instance, then by source location, then by name + std::stable_sort(m_signals.begin(), m_signals.end(), [](const Signal& a, const Signal& b) { + if (const int cmp = a.m_path.compare(b.m_path)) return cmp < 0; + const FileLine* const aflp = a.m_vscp->fileline(); + const FileLine* const bflp = b.m_vscp->fileline(); + if (const int cmp = aflp->operatorCompare(*bflp)) return cmp < 0; + return a.m_name < b.m_name; + }); + + // Build trace initialization functions for this AstScope + PathAdjustor pathAdjustor{flp, [&](AstNodeStmt* stmtp) { addToSubFunc(stmtp); }}; + for (const Signal& signal : m_signals) { + // Adjust name prefix based on path in hierarchy + pathAdjustor.adjust(signal.m_path); + + // Build AstTraceDecl for this signal + m_traVscp = signal.m_vscp; + m_traName = signal.m_name; + if (const char* const ignoreReasonp = vscIgnoreTrace(m_traVscp)) { addIgnore(ignoreReasonp); } else { ++m_statSigs; - if (nodep->valuep()) { - m_traValuep = nodep->valuep()->cloneTree(true); + if (AstNode* const valuep = m_traVscp->valuep()) { + m_traValuep = valuep->cloneTree(false); } else { - m_traValuep = new AstVarRef(nodep->fileline(), nodep, VAccess::READ); + m_traValuep = new AstVarRef{m_traVscp->fileline(), m_traVscp, VAccess::READ}; } - // Recurse into data type of the signal; the visitors will call addTraceDecl() - iterate(varp->dtypep()->skipRefToEnump()); + // Recurse into data type of the signal. The visit methods will add AstTraceDecls. + iterate(m_traVscp->varp()->dtypep()->skipRefToEnump()); // Cleanup - if (m_traValuep) VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr); + if (m_traValuep) VL_DO_DANGLING(m_traValuep->deleteTree(), m_traValuep); } - m_traVscp = nullptr; - m_traShowname = ""; } + pathAdjustor.unwind(); + m_traVscp = nullptr; + m_traName.clear(); + UASSERT_OBJ(!m_traValuep, nodep, "Should have been deleted"); + m_signals.clear(); + + // Add sub functions to m_scopeSubFuncps + const AstCell* const cellp = nodep->aboveCellp(); + if (cellp && VN_IS(cellp->modp(), Iface)) { + string scopeName = nodep->prettyName(); + const size_t lastDot = scopeName.find_last_of('.'); + UASSERT_OBJ(lastDot != string::npos, nodep, + "Expected an interface scope name to have at least one dot"); + scopeName = scopeName.substr(0, lastDot + 1); + const size_t scopeLen = scopeName.length(); + + for (AstIntfRef *irp = cellp->intfRefp(), *nextIrp; irp; irp = nextIrp) { + nextIrp = VN_AS(irp->nextp(), IntfRef); + + const string irpName = irp->prettyName(); + if (scopeLen > irpName.length()) continue; + const string intfScopeName = irpName.substr(0, scopeLen); + if (scopeName != intfScopeName) continue; + + string scopeName = AstNode::vcdName(irp->name()); + if (scopeName.substr(0, 4) == "TOP ") scopeName.erase(0, 4); + scopeName += getScopeChar(VLT_TRACE_SCOPE_INTERFACE) + ' '; + m_scopeSubFuncps.emplace(scopeName, m_subFuncps); + + VL_DO_DANGLING(irp->unlinkFrBack(), irp); + } + + m_subFuncps.clear(); + } else { + string scopeName = AstNode::vcdName(nodep->name()) + ' '; + if (VString::startsWith(scopeName, "TOP ")) scopeName.erase(0, 4); + m_scopeSubFuncps.emplace(scopeName, std::move(m_subFuncps)); + } + + m_currScopep = nullptr; } + virtual void visit(AstVarScope* nodep) override { + UASSERT_OBJ(m_currScopep, nodep, "AstVarScope not under AstScope"); + + // Prefilter - things that get added to m_vscps will either get traced or get a comment as + // to why they are not traced. Generally these conditions doesn't need updating, instead + // use varp->isTrace() and/or vscIgnoreTrace. + if (nodep->varp()->isTemp() && !nodep->varp()->isTrace()) return; + if (nodep->varp()->isClassMember()) return; + if (nodep->varp()->isFuncLocal()) return; + + // Add to traced signal list + m_signals.emplace_back(nodep); + } + // VISITORS - Data types when tracing virtual void visit(AstConstDType* nodep) override { if (m_traVscp) iterate(nodep->subDTypep()->skipRefToEnump()); @@ -247,20 +342,20 @@ private: } } else { // Unroll now, as have no other method to get right signal names + FileLine* const flp = nodep->fileline(); AstNodeDType* const subtypep = nodep->subDTypep()->skipRefToEnump(); + VL_RESTORER(m_traName); + addToSubFunc(new AstTracePushNamePrefix{flp, m_traName}); for (int i = nodep->lo(); i <= nodep->hi(); ++i) { - VL_RESTORER(m_traShowname); VL_RESTORER(m_traValuep); - { - m_traShowname += string("[") + cvtToStr(i) + string("]"); - m_traValuep = new AstArraySel( - nodep->fileline(), m_traValuep->cloneTree(true), i - nodep->lo()); - - m_traValuep->dtypep(subtypep); - iterate(subtypep); - VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr); - } + m_traName = string{"["} + cvtToStr(i) + string{"]"}; + m_traValuep = m_traValuep->cloneTree(false); + m_traValuep = new AstArraySel{flp, m_traValuep, i - nodep->lo()}; + m_traValuep->dtypep(subtypep); + iterate(subtypep); + VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr); } + addToSubFunc(new AstTracePopNamePrefix{flp, 1}); } } } @@ -272,20 +367,21 @@ private: // a much faster way to trace addTraceDecl(VNumRange(), nodep->width()); } else { + FileLine* const flp = nodep->fileline(); AstNodeDType* const subtypep = nodep->subDTypep()->skipRefToEnump(); + VL_RESTORER(m_traName); + addToSubFunc(new AstTracePushNamePrefix{flp, m_traName}); for (int i = nodep->lo(); i <= nodep->hi(); ++i) { - VL_RESTORER(m_traShowname); VL_RESTORER(m_traValuep); - { - m_traShowname += string("[") + cvtToStr(i) + string("]"); - m_traValuep - = new AstSel(nodep->fileline(), m_traValuep->cloneTree(true), - (i - nodep->lo()) * subtypep->width(), subtypep->width()); - m_traValuep->dtypep(subtypep); - iterate(subtypep); - VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr); - } + m_traName = string{"["} + cvtToStr(i) + string{"]"}; + const int lsb = (i - nodep->lo()) * subtypep->width(); + m_traValuep = m_traValuep->cloneTree(false); + m_traValuep = new AstSel{flp, m_traValuep, lsb, subtypep->width()}; + m_traValuep->dtypep(subtypep); + iterate(subtypep); + VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr); } + addToSubFunc(new AstTracePopNamePrefix{flp, 1}); } } } @@ -299,31 +395,30 @@ private: } else if (!nodep->packed()) { addIgnore("Unsupported: Unpacked struct/union"); } else { + FileLine* const flp = nodep->fileline(); + const bool isStruct = VN_IS(nodep, StructDType); // Otherwise union + VL_RESTORER(m_traName); + string prefix{m_traName}; + prefix += isStruct ? getScopeChar(VLT_TRACE_SCOPE_STRUCT) // Mark scope type + : getScopeChar(VLT_TRACE_SCOPE_UNION); + addToSubFunc(new AstTracePushNamePrefix{flp, prefix + ' '}); for (const AstMemberDType* itemp = nodep->membersp(); itemp; itemp = VN_AS(itemp->nextp(), MemberDType)) { AstNodeDType* const subtypep = itemp->subDTypep()->skipRefToEnump(); - VL_RESTORER(m_traShowname); - VL_RESTORER(m_traValuep); - { - if (VN_IS(nodep, StructDType)) { - // Mark scope as a struct by setting the last char to 0x80 + the - // fstScopeType - m_traShowname += getScopeChar(VLT_TRACE_SCOPE_STRUCT) + " " - + itemp->prettyName(); - - m_traValuep - = new AstSel(nodep->fileline(), m_traValuep->cloneTree(true), - itemp->lsb(), subtypep->width()); - m_traValuep->dtypep(subtypep); - iterate(subtypep); - VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr); - } else { // Else union, replicate fields - m_traShowname - += getScopeChar(VLT_TRACE_SCOPE_UNION) + " " + itemp->prettyName(); - iterate(subtypep); - } + m_traName = itemp->prettyName(); + if (isStruct) { + VL_RESTORER(m_traValuep); + m_traValuep = m_traValuep->cloneTree(false); + m_traValuep + = new AstSel{flp, m_traValuep, itemp->lsb(), subtypep->width()}; + m_traValuep->dtypep(subtypep); + iterate(subtypep); + VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr); + } else { // Else union, replicate fields + iterate(subtypep); } } + addToSubFunc(new AstTracePopNamePrefix{flp, 1}); } } } @@ -348,7 +443,48 @@ private: public: // CONSTRUCTORS - explicit TraceDeclVisitor(AstNetlist* nodep) { iterate(nodep); } + explicit TraceDeclVisitor(AstNetlist* nodep) + : m_topScopep{nodep->topScopep()} { + FileLine* const flp = nodep->fileline(); + + // Iterate modules to build per scope initialization sub functions + iterateAndNextConstNull(nodep->modulesp()); + UASSERT_OBJ(m_subFuncps.empty(), nodep, "Should have been emptied"); + + // Build top level trace initialization functions + PathAdjustor pathAdjustor{flp, [&](AstNodeStmt* stmtp) { addToTopFunc(stmtp); }}; + for (const auto& item : m_scopeSubFuncps) { + // Adjust name prefix based on path in hierarchy + pathAdjustor.adjust(item.first); + + // Call all sub functions for this path + for (AstCFunc* const subFuncp : item.second) { + AstCCall* const callp = new AstCCall{flp, subFuncp}; + callp->argTypes("tracep"); + addToTopFunc(callp); + } + } + pathAdjustor.unwind(); + + // Ensure a top function exists, in case there was nothing to trace at all + if (m_topFuncps.empty()) addToTopFunc(new AstComment{flp, "Empty"}); + + // Create single top level function, if more than one exists + if (m_topFuncps.size() > 1) { + AstCFunc* const topFuncp = newCFunc(flp, ""); + for (AstCFunc* funcp : m_topFuncps) { + AstCCall* const callp = new AstCCall{flp, funcp}; + callp->argTypes("tracep"); + topFuncp->addStmtsp(callp); + } + m_topFuncps.clear(); + m_topFuncps.push_back(topFuncp); + } + + // Set name of top level function + AstCFunc* const topFuncp = m_topFuncps.front(); + topFuncp->name("trace_init_top"); + } virtual ~TraceDeclVisitor() override { V3Stats::addStat("Tracing, Traced signals", m_statSigs); V3Stats::addStat("Tracing, Ignored signals", m_statIgnSigs); diff --git a/src/V3TraceDecl.h b/src/V3TraceDecl.h index f60f05f9a..2f2c7cb3b 100644 --- a/src/V3TraceDecl.h +++ b/src/V3TraceDecl.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp index d57adf971..d09acd272 100644 --- a/src/V3Tristate.cpp +++ b/src/V3Tristate.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -51,7 +51,10 @@ // // Note 1800-2012 adds user defined resolution functions. This suggests // long term this code should be scoped-based and resolve all nodes at once -// rather than hierarchically. +// rather than hierarchically. If/when that is done, make sure to avoid +// duplicating vars and logic that is common between each instance of a +// module. +// //************************************************************************* #include "config_build.h" @@ -69,7 +72,7 @@ //###################################################################### -class TristateBaseVisitor VL_NOT_FINAL : public AstNVisitor { +class TristateBaseVisitor VL_NOT_FINAL : public VNVisitor { public: // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -119,7 +122,7 @@ public: class TristateGraph final { // NODE STATE // AstVar::user5p -> TristateVertex* for variable being built - // AstUser5InUse m_inuser5; // In visitor below + // VNUser5InUse m_inuser5; // In visitor below // TYPES public: @@ -235,10 +238,10 @@ public: } if (debug() >= 9) m_graph.dumpDotFilePrefixed("tri_pos__" + nodep->name()); } - void setTristate(AstNode* nodep) { makeVertex(nodep)->isTristate(true); } void associate(AstNode* fromp, AstNode* top) { new V3GraphEdge(&m_graph, makeVertex(fromp), makeVertex(top), 1); } + void setTristate(AstNode* nodep) { makeVertex(nodep)->isTristate(true); } bool isTristate(AstNode* nodep) { const TristateVertex* const vertexp = reinterpret_cast(nodep->user5p()); return vertexp && vertexp->isTristate(); @@ -327,11 +330,11 @@ class TristateVisitor final : public TristateBaseVisitor { // See TristateGraph: // AstVar::user5p -> TristateVertex* for variable being built // AstStmt*::user5p -> TristateVertex* for this statement - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; - const AstUser3InUse m_inuser3; - const AstUser4InUse m_inuser4; - const AstUser5InUse m_inuser5; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; + const VNUser3InUse m_inuser3; + const VNUser4InUse m_inuser4; + const VNUser5InUse m_inuser5; // TYPES using RefVec = std::vector; @@ -347,7 +350,7 @@ class TristateVisitor final : public TristateBaseVisitor { // AstNodeModule* m_modp = nullptr; // Current module AstCell* m_cellp = nullptr; // current cell - VarMap m_lhsmap; // LHS driver map + VarMap m_lhsmap; // Tristate left-hand-side driver map int m_unique = 0; bool m_alhs = false; // On LHS of assignment const AstNode* m_logicp = nullptr; // Current logic being built @@ -362,67 +365,60 @@ class TristateVisitor final : public TristateBaseVisitor { if (m_alhs) o += "alhs "; return o; } + void modAddStmtp(AstNode* nodep, AstNode* newp) { + if (!m_modp) { + nodep->v3warn(E_UNSUPPORTED, + "Unsupported: Creating tristate signal not underneath a module: " + << nodep->prettyNameQ()); + } else { + m_modp->addStmtp(newp); + } + } void associateLogic(AstNode* fromp, AstNode* top) { if (m_logicp) m_tgraph.associate(fromp, top); } + AstConst* newAllZerosOrOnes(AstNode* nodep, bool ones) { + V3Number num{nodep, nodep->width()}; + if (ones) num.setAllBits1(); + AstConst* const newp = new AstConst{nodep->fileline(), num}; + return newp; + } AstNode* getEnp(AstNode* nodep) { - // checks if user1p() is null, and if so, adds a constant output - // enable driver of all 1's. Otherwise returns the user1p() data. if (!nodep->user1p()) { - V3Number num(nodep, nodep->width()); - num.setAllBits1(); - AstNode* const enp = new AstConst(nodep->fileline(), num); - nodep->user1p(enp); + // There's no select being built yet, so add what will become a + // constant output enable driver of all 1's + nodep->user1p(newAllZerosOrOnes(nodep, true)); } + // Otherwise return the previous output enable return nodep->user1p(); } - AstVar* getCreateEnVarp(AstVar* invarp) { // Return the master __en for the specified input variable if (!invarp->user1p()) { - AstVar* const newp = new AstVar(invarp->fileline(), AstVarType::MODULETEMP, + AstVar* const newp = new AstVar(invarp->fileline(), VVarType::MODULETEMP, invarp->name() + "__en", invarp); UINFO(9, " newenv " << newp << endl); - if (!m_modp) { - invarp->v3warn(E_UNSUPPORTED, - "Unsupported: Creating tristate signal not underneath a module: " - << invarp->prettyNameQ()); - } else { - m_modp->addStmtp(newp); - } + modAddStmtp(invarp, newp); invarp->user1p(newp); // find envar given invarp } return VN_AS(invarp->user1p(), Var); } - AstVar* getCreateOutVarp(AstVar* invarp) { // Return the master __out for the specified input variable if (!invarp->user4p()) { - AstVar* const newp = new AstVar(invarp->fileline(), AstVarType::MODULETEMP, + AstVar* const newp = new AstVar(invarp->fileline(), VVarType::MODULETEMP, invarp->name() + "__out", invarp); UINFO(9, " newout " << newp << endl); - if (!m_modp) { - invarp->v3warn(E_UNSUPPORTED, - "Unsupported: Creating tristate signal not underneath a module: " - << invarp->prettyNameQ()); - } else { - m_modp->addStmtp(newp); - } + modAddStmtp(invarp, newp); invarp->user4p(newp); // find outvar given invarp } return VN_AS(invarp->user4p(), Var); } - AstVar* getCreateUnconnVarp(AstNode* fromp, AstNodeDType* dtypep) { - AstVar* const newp = new AstVar(fromp->fileline(), AstVarType::MODULETEMP, + AstVar* const newp = new AstVar(fromp->fileline(), VVarType::MODULETEMP, "__Vtriunconn" + cvtToStr(m_unique++), dtypep); UINFO(9, " newunc " << newp << endl); - if (!m_modp) { - newp->v3warn(E_UNSUPPORTED, - "Unsupported: Creating tristate signal not underneath a module"); - } else { - m_modp->addStmtp(newp); - } + modAddStmtp(newp, newp); return newp; } @@ -490,20 +486,18 @@ class TristateVisitor final : public TristateBaseVisitor { if (m_tgraph.isTristate(varp)) { const auto it = m_lhsmap.find(varp); if (it == m_lhsmap.end()) { - // set output enable to always be off on this assign - // statement so that this var is floating + // This variable is floating, set output enable to + // always be off on this assign UINFO(8, " Adding driver to var " << varp << endl); - AstConst* const constp = new AstConst( - varp->fileline(), AstConst::WidthedValue(), varp->width(), 0); + AstConst* const constp = newAllZerosOrOnes(varp, false); AstVarRef* const varrefp = new AstVarRef(varp->fileline(), varp, VAccess::WRITE); AstNode* const newp = new AstAssignW(varp->fileline(), varrefp, constp); UINFO(9, " newoev " << newp << endl); - varrefp->user1p(new AstConst(varp->fileline(), AstConst::WidthedValue(), - varp->width(), 0)); + varrefp->user1p(newAllZerosOrOnes(varp, false)); nodep->addStmtp(newp); mapInsertLhsVarRef(varrefp); // insertTristates will convert - // // to a varref to the __out# variable + // // to a varref to the __out# variable } } } @@ -516,133 +510,124 @@ class TristateVisitor final : public TristateBaseVisitor { ++nextit; AstVar* const invarp = it->first; const RefVec* const refsp = it->second; - // Figure out if this var needs tristate expanded. - if (!m_tgraph.isTristate(invarp)) { - // This var has no tristate logic, so we leave it alone. - UINFO(8, " NO TRISTATE ON:" << invarp << endl); - m_lhsmap.erase(invarp); - VL_DO_DANGLING(delete refsp, refsp); - continue; - } - - ++m_statTriSigs; - m_tgraph.didProcess(invarp); - UINFO(8, " TRISTATE EXPANDING:" << invarp << endl); - - // If the lhs var is a port, then we need to create ports for - // the output (__out) and output enable (__en) signals. The - // original port gets converted to an input. Don't tristate expand - // if this is the top level so that we can force the final - // tristate resolution at the top. - AstVar* envarp = nullptr; - AstVar* outvarp = nullptr; // __out - AstVar* lhsp = invarp; // Variable to assign drive-value to ( or __out) - if (!nodep->isTop() && invarp->isIO()) { - // This var becomes an input - invarp->varType2In(); // convert existing port to type input - // Create an output port (__out) - outvarp = getCreateOutVarp(invarp); - outvarp->varType2Out(); - lhsp = outvarp; // Must assign to __out, not to normal input signal - UINFO(9, " TRISTATE propagates up with " << lhsp << endl); - // Create an output enable port (__en) - // May already be created if have foo === 1'bz somewhere - envarp = getCreateEnVarp(invarp); - envarp->varType2Out(); - // - outvarp->user1p(envarp); - outvarp->user3p(invarp->user3p()); // AstPull* propagation - if (invarp->user3p()) UINFO(9, "propagate pull to " << outvarp << endl); - } else if (invarp->user1p()) { - envarp = VN_AS(invarp->user1p(), Var); // From CASEEQ, foo === 1'bz - } - - AstNode* orp = nullptr; - AstNode* enp = nullptr; - AstNode* undrivenp = nullptr; - - // loop through the lhs drivers to build the driver resolution logic - for (auto refp : *refsp) { - const int w = lhsp->width(); - - // create the new lhs driver for this var - AstVar* const newlhsp = new AstVar(lhsp->fileline(), AstVarType::MODULETEMP, - lhsp->name() + "__out" + cvtToStr(m_unique), - VFlagBitPacked(), w); // 2-state ok; sep enable - UINFO(9, " newout " << newlhsp << endl); - nodep->addStmtp(newlhsp); - refp->varp(newlhsp); // assign the new var to the varref - refp->name(newlhsp->name()); - - // create a new var for this drivers enable signal - AstVar* const newenp = new AstVar(lhsp->fileline(), AstVarType::MODULETEMP, - lhsp->name() + "__en" + cvtToStr(m_unique++), - VFlagBitPacked(), w); // 2-state ok - UINFO(9, " newenp " << newenp << endl); - nodep->addStmtp(newenp); - - AstNode* const enassp = new AstAssignW( - refp->fileline(), new AstVarRef(refp->fileline(), newenp, VAccess::WRITE), - getEnp(refp)); - UINFO(9, " newass " << enassp << endl); - nodep->addStmtp(enassp); - - // now append this driver to the driver logic. - AstNode* const ref1p = new AstVarRef(refp->fileline(), newlhsp, VAccess::READ); - AstNode* const ref2p = new AstVarRef(refp->fileline(), newenp, VAccess::READ); - AstNode* const andp = new AstAnd(refp->fileline(), ref1p, ref2p); - - // or this to the others - orp = (!orp) ? andp : new AstOr(refp->fileline(), orp, andp); - - if (envarp) { - AstNode* const ref3p = new AstVarRef(refp->fileline(), newenp, VAccess::READ); - enp = (!enp) ? ref3p : new AstOr(ref3p->fileline(), enp, ref3p); - } - AstNode* const tmp = new AstNot( - newenp->fileline(), new AstVarRef(newenp->fileline(), newenp, VAccess::READ)); - undrivenp = ((!undrivenp) ? tmp : new AstAnd(refp->fileline(), tmp, undrivenp)); - } - if (!undrivenp) { // No drivers on the bus - V3Number ones(invarp, lhsp->width()); - ones.setAllBits1(); - undrivenp = new AstConst(invarp->fileline(), ones); - } - if (!outvarp) { - // This is the final resolution of the tristate, so we apply - // the pull direction to any undriven pins. - V3Number pull(invarp, lhsp->width()); - const AstPull* const pullp = static_cast(lhsp->user3p()); - if (pullp && pullp->direction() == 1) { - pull.setAllBits1(); - UINFO(9, "Has pullup " << pullp << endl); - } else { - pull.setAllBits0(); // Default pull direction is down. - } - undrivenp = new AstAnd(invarp->fileline(), undrivenp, - new AstConst(invarp->fileline(), pull)); - orp = new AstOr(invarp->fileline(), orp, undrivenp); + if (m_tgraph.isTristate(invarp)) { + insertTristatesSignal(nodep, invarp, refsp); } else { - VL_DO_DANGLING(undrivenp->deleteTree(), undrivenp); + UINFO(8, " NO TRISTATE ON:" << invarp << endl); } - if (envarp) { - nodep->addStmtp(new AstAssignW( - enp->fileline(), new AstVarRef(envarp->fileline(), envarp, VAccess::WRITE), - enp)); - } - // __out (child) or (parent) = drive-value expression - AstNode* const assp = new AstAssignW( - lhsp->fileline(), new AstVarRef(lhsp->fileline(), lhsp, VAccess::WRITE), orp); - assp->user2(U2_BOTH); // Don't process further; already resolved - if (debug() >= 9) assp->dumpTree(cout, "-lhsp-eqn: "); - nodep->addStmtp(assp); // Delete the map and vector list now that we have expanded it. m_lhsmap.erase(invarp); VL_DO_DANGLING(delete refsp, refsp); } } + void insertTristatesSignal(AstNodeModule* nodep, AstVar* const invarp, + const RefVec* const refsp) { + UINFO(8, " TRISTATE EXPANDING:" << invarp << endl); + ++m_statTriSigs; + m_tgraph.didProcess(invarp); + + // If the lhs var is a port, then we need to create ports for + // the output (__out) and output enable (__en) signals. The + // original port gets converted to an input. Don't tristate expand + // if this is the top level so that we can force the final + // tristate resolution at the top. + AstVar* envarp = nullptr; + AstVar* outvarp = nullptr; // __out + AstVar* lhsp = invarp; // Variable to assign drive-value to ( or __out) + if (!nodep->isTop() && invarp->isIO()) { + // This var becomes an input + invarp->varType2In(); // convert existing port to type input + // Create an output port (__out) + outvarp = getCreateOutVarp(invarp); + outvarp->varType2Out(); + lhsp = outvarp; // Must assign to __out, not to normal input signal + UINFO(9, " TRISTATE propagates up with " << lhsp << endl); + // Create an output enable port (__en) + // May already be created if have foo === 1'bz somewhere + envarp = getCreateEnVarp(invarp); // direction will be sen in visit(AstPin*) + // + outvarp->user1p(envarp); + outvarp->user3p(invarp->user3p()); // AstPull* propagation + if (invarp->user3p()) UINFO(9, "propagate pull to " << outvarp << endl); + } else if (invarp->user1p()) { + envarp = VN_AS(invarp->user1p(), Var); // From CASEEQ, foo === 1'bz + } + + AstNode* orp = nullptr; + AstNode* enp = nullptr; + AstNode* undrivenp = nullptr; + + // loop through the lhs drivers to build the driver resolution logic + for (auto refp : *refsp) { + const int w = lhsp->width(); + + // create the new lhs driver for this var + AstVar* const newlhsp = new AstVar(lhsp->fileline(), VVarType::MODULETEMP, + lhsp->name() + "__out" + cvtToStr(m_unique), + VFlagBitPacked(), w); // 2-state ok; sep enable + UINFO(9, " newout " << newlhsp << endl); + nodep->addStmtp(newlhsp); + refp->varp(newlhsp); // assign the new var to the varref + refp->name(newlhsp->name()); + + // create a new var for this drivers enable signal + AstVar* const newenp = new AstVar(lhsp->fileline(), VVarType::MODULETEMP, + lhsp->name() + "__en" + cvtToStr(m_unique++), + VFlagBitPacked(), w); // 2-state ok + UINFO(9, " newenp " << newenp << endl); + nodep->addStmtp(newenp); + + AstNode* const enassp = new AstAssignW( + refp->fileline(), new AstVarRef(refp->fileline(), newenp, VAccess::WRITE), + getEnp(refp)); + UINFO(9, " newass " << enassp << endl); + nodep->addStmtp(enassp); + + // now append this driver to the driver logic. + AstNode* const ref1p = new AstVarRef(refp->fileline(), newlhsp, VAccess::READ); + AstNode* const ref2p = new AstVarRef(refp->fileline(), newenp, VAccess::READ); + AstNode* const andp = new AstAnd(refp->fileline(), ref1p, ref2p); + + // or this to the others + orp = (!orp) ? andp : new AstOr(refp->fileline(), orp, andp); + + if (envarp) { + AstNode* const ref3p = new AstVarRef(refp->fileline(), newenp, VAccess::READ); + enp = (!enp) ? ref3p : new AstOr(ref3p->fileline(), enp, ref3p); + } + AstNode* const tmp = new AstNot( + newenp->fileline(), new AstVarRef(newenp->fileline(), newenp, VAccess::READ)); + undrivenp = ((!undrivenp) ? tmp : new AstAnd(refp->fileline(), tmp, undrivenp)); + } + if (!undrivenp) { // No drivers on the bus + undrivenp = newAllZerosOrOnes(invarp, true); + } + if (!outvarp) { + // This is the final pre-forced resolution of the tristate, so we apply + // the pull direction to any undriven pins. + V3Number pull(invarp, lhsp->width()); + const AstPull* const pullp = static_cast(lhsp->user3p()); + bool pull1 = pullp && pullp->direction() == 1; // Else default is down + undrivenp + = new AstAnd{invarp->fileline(), undrivenp, newAllZerosOrOnes(invarp, pull1)}; + orp = new AstOr(invarp->fileline(), orp, undrivenp); + } else { + VL_DO_DANGLING(undrivenp->deleteTree(), undrivenp); + } + if (envarp) { + nodep->addStmtp(new AstAssignW( + enp->fileline(), new AstVarRef(envarp->fileline(), envarp, VAccess::WRITE), enp)); + } + // __out (child) or (parent) = drive-value expression + AstNode* const assp = new AstAssignW( + lhsp->fileline(), new AstVarRef(lhsp->fileline(), lhsp, VAccess::WRITE), orp); + assp->user2(U2_BOTH); // Don't process further; already resolved + if (debug() >= 9) assp->dumpTree(cout, "-lhsp-eqn: "); + nodep->addStmtp(assp); + } + // VISITORS virtual void visit(AstConst* nodep) override { UINFO(9, dbgState() << nodep << endl); @@ -897,15 +882,15 @@ class TristateVisitor final : public TristateBaseVisitor { void visitAssign(AstNodeAssign* nodep) { if (m_graphing) { if (nodep->user2() & U2_GRAPHING) return; - nodep->user2(U2_GRAPHING); + VL_RESTORER(m_logicp); m_logicp = nodep; + nodep->user2(U2_GRAPHING); iterateAndNextNull(nodep->rhsp()); m_alhs = true; iterateAndNextNull(nodep->lhsp()); m_alhs = false; associateLogic(nodep->rhsp(), nodep); associateLogic(nodep, nodep->lhsp()); - m_logicp = nullptr; } else { if (nodep->user2() & U2_NONGRAPH) { return; // Iterated here, or created assignment to ignore @@ -1024,7 +1009,7 @@ class TristateVisitor final : public TristateBaseVisitor { AstVar* const envarp = getCreateEnVarp(varrefp->varp()); // If any drops, we need to add in the count of Zs (from __en) UINFO(4, " COUNTBITS('z)-> " << nodep << endl); - AstNRelinker relinkHandle; + VNRelinker relinkHandle; nodep->unlinkFrBack(&relinkHandle); AstNode* newp = new AstCountOnes( nodep->fileline(), new AstVarRef(nodep->fileline(), envarp, VAccess::READ)); @@ -1063,11 +1048,11 @@ class TristateVisitor final : public TristateBaseVisitor { nodep->v3warn(E_UNSUPPORTED, "Unsupported pullup/down (weak driver) construct."); } else { if (m_graphing) { - varrefp->access(VAccess::WRITE); + VL_RESTORER(m_logicp); m_logicp = nodep; + varrefp->access(VAccess::WRITE); m_tgraph.setTristate(nodep); associateLogic(nodep, varrefp->varp()); - m_logicp = nullptr; } else { // Replace any pullup/pulldowns with assignw logic and set the // direction of the pull in the user3() data on the var. Given @@ -1089,13 +1074,13 @@ class TristateVisitor final : public TristateBaseVisitor { void iteratePinGuts(AstPin* nodep) { if (m_graphing) { + VL_RESTORER(m_logicp); m_logicp = nodep; if (nodep->exprp()) { associateLogic(nodep->exprp(), nodep); associateLogic(nodep, nodep->exprp()); } iterateChildren(nodep); - m_logicp = nullptr; } else { // All heavy lifting completed in graph visitor. if (nodep->exprp()) m_tgraph.didProcess(nodep); @@ -1173,10 +1158,14 @@ class TristateVisitor final : public TristateBaseVisitor { // Create the output enable pin, connect to new signal AstNode* enrefp; { - AstVar* const enVarp = new AstVar(nodep->fileline(), AstVarType::MODULETEMP, + AstVar* const enVarp = new AstVar(nodep->fileline(), VVarType::MODULETEMP, nodep->name() + "__en" + cvtToStr(m_unique++), VFlagBitPacked(), enModVarp->width()); - enModVarp->direction(VDirection::INPUT); + if (inDeclProcessing) { // __en(from-resolver-const) or __en(from-resolver-wire) + enModVarp->varType2In(); + } else { + enModVarp->varType2Out(); + } UINFO(9, " newenv " << enVarp << endl); AstPin* const enpinp = new AstPin(nodep->fileline(), nodep->pinNum(), @@ -1399,10 +1388,10 @@ class TristateVisitor final : public TristateBaseVisitor { } virtual void visit(AstCell* nodep) override { + VL_RESTORER(m_cellp); m_cellp = nodep; m_alhs = false; iterateChildren(nodep); - m_cellp = nullptr; } virtual void visit(AstNetlist* nodep) override { iterateChildrenBackwards(nodep); } diff --git a/src/V3Tristate.h b/src/V3Tristate.h index ffbe63602..c820a1f2a 100644 --- a/src/V3Tristate.h +++ b/src/V3Tristate.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp index 9ff4fa592..dc8283469 100644 --- a/src/V3Undriven.cpp +++ b/src/V3Undriven.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you +// Copyright 2004-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -39,7 +39,7 @@ class UndrivenVarEntry final { // MEMBERS - AstVar* m_varp; // Variable this tracks + AstVar* const m_varp; // Variable this tracks std::vector m_wholeFlags; // Used/Driven on whole vector std::vector m_bitFlags; // Used/Driven on each subbit @@ -49,9 +49,9 @@ class UndrivenVarEntry final { public: // CONSTRUCTORS - explicit UndrivenVarEntry(AstVar* varp) { // Construction for when a var is used + explicit UndrivenVarEntry(AstVar* varp) + : m_varp(varp) { // Construction for when a var is used UINFO(9, "create " << varp << endl); - m_varp = varp; m_wholeFlags.resize(FLAGS_PER_BIT); for (int i = 0; i < FLAGS_PER_BIT; i++) m_wholeFlags[i] = false; m_bitFlags.resize(varp->width() * FLAGS_PER_BIT); @@ -235,21 +235,22 @@ public: //###################################################################### // Undriven state, as a visitor of each AstNode -class UndrivenVisitor final : public AstNVisitor { +class UndrivenVisitor final : public VNVisitor { private: // NODE STATE // Netlist: // AstVar::user1p -> UndrivenVar* for usage var, 0=not set yet - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // Each always: // AstNode::user2p -> UndrivenVar* for usage var, 0=not set yet - const AstUser2InUse m_inuser2; + const VNUser2InUse m_inuser2; // STATE std::array, 3> m_entryps; // Nodes to delete when finished bool m_inBBox = false; // In black box; mark as driven+used bool m_inContAssign = false; // In continuous assignment bool m_inProcAssign = false; // In procedural assignment + bool m_inInoutPin = false; // Connected to pin that is inout const AstNodeFTask* m_taskp = nullptr; // Current task const AstAlways* m_alwaysCombp = nullptr; // Current always if combo, otherwise nullptr @@ -374,7 +375,13 @@ private: } entryp->drivenWhole(); } - if (m_inBBox || nodep->access().isReadOrRW() || fdrv) entryp->usedWhole(); + if (m_inBBox || nodep->access().isReadOrRW() + || fdrv + // Inouts have only isWrite set, as we don't have more + // information and operating on module boundry, treat as + // both read and writing + || m_inInoutPin) + entryp->usedWhole(); } } @@ -430,6 +437,11 @@ private: iterateChildren(nodep); } } + virtual void visit(AstPin* nodep) override { + VL_RESTORER(m_inInoutPin); + m_inInoutPin = nodep->modVarp()->isInoutish(); + iterateChildren(nodep); + } // Until we support tables, primitives will have undriven and unused I/Os virtual void visit(AstPrimitive*) override {} diff --git a/src/V3Undriven.h b/src/V3Undriven.h index 98ddc041b..059581f3b 100644 --- a/src/V3Undriven.h +++ b/src/V3Undriven.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3UniqueNames.h b/src/V3UniqueNames.h index f33c86a12..34d83b8e1 100644 --- a/src/V3UniqueNames.h +++ b/src/V3UniqueNames.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2021 by Wilson Snyder. This program is free software; you +// Copyright 2005-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index 59b9ac0d0..d71317e58 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -42,21 +42,22 @@ //###################################################################### -class UnknownVisitor final : public AstNVisitor { +class UnknownVisitor final : public VNVisitor { private: // NODE STATE // Cleared on Netlist // AstSel::user() -> bool. Set true if already processed // AstArraySel::user() -> bool. Set true if already processed // AstNode::user2p() -> AstIf* Inserted if assignment for conditional - const AstUser1InUse m_inuser1; - const AstUser2InUse m_inuser2; + const VNUser1InUse m_inuser1; + const VNUser2InUse m_inuser2; // STATE AstNodeModule* m_modp = nullptr; // Current module AstAssignW* m_assignwp = nullptr; // Current assignment AstAssignDly* m_assigndlyp = nullptr; // Current assignment bool m_constXCvt = false; // Convert X's + bool m_allowXUnique = true; // Allow unique assignments VDouble0 m_statUnkVars; // Statistic tracking V3UniqueNames m_lvboundNames; // For generating unique temporary variable names V3UniqueNames m_xrandNames; // For generating unique temporary variable names @@ -110,14 +111,14 @@ private: // Saves us teaching V3Const how to optimize, and it won't be needed again. if (const AstIf* const ifp = VN_AS(prep->user2p(), If)) { UASSERT_OBJ(!needDly, prep, "Should have already converted to non-delay"); - AstNRelinker replaceHandle; + VNRelinker replaceHandle; AstNode* const earliercondp = ifp->condp()->unlinkFrBack(&replaceHandle); AstNode* const newp = new AstLogAnd(condp->fileline(), condp, earliercondp); UINFO(4, "Edit BOUNDLVALUE " << newp << endl); replaceHandle.relink(newp); } else { AstVar* const varp - = new AstVar(fl, AstVarType::MODULETEMP, m_lvboundNames.get(prep), prep->dtypep()); + = new AstVar(fl, VVarType::MODULETEMP, m_lvboundNames.get(prep), prep->dtypep()); m_modp->addStmtp(varp); AstNode* const abovep = prep->backp(); // Grab above point before we replace 'prep' prep->replaceWith(new AstVarRef(fl, varp, VAccess::WRITE)); @@ -141,9 +142,12 @@ private: UINFO(4, " MOD " << nodep << endl); VL_RESTORER(m_modp); VL_RESTORER(m_constXCvt); + VL_RESTORER(m_allowXUnique); { m_modp = nodep; m_constXCvt = true; + // Class X randomization causes Vxrand in strange places, so disable + if (VN_IS(nodep, Class)) m_allowXUnique = false; m_lvboundNames.reset(); m_xrandNames.reset(); iterateChildren(nodep); @@ -272,13 +276,13 @@ private: UINFO(4, " COUNTBITS(" << dropop[0] << dropop[1] << dropop[2] << " " << nodep << endl); AstNode* nonXp = nullptr; - if (!dropop[0]) + if (!dropop[0]) { nonXp = nodep->rhsp(); - else if (!dropop[1]) + } else if (!dropop[1]) { nonXp = nodep->thsp(); - else if (!dropop[2]) + } else if (!dropop[2]) { nonXp = nodep->fhsp(); - else { // Was all X-s + } else { // Was all X-s UINFO(4, " COUNTBITS('x)->0 " << nodep << endl); AstConst* const newp = new AstConst(nodep->fileline(), AstConst::BitFalse()); nodep->replaceWith(newp); @@ -310,7 +314,7 @@ private: numb1.opBitsOne(nodep->num()); V3Number numbx(nodep, nodep->width()); numbx.opBitsXZ(nodep->num()); - if (v3Global.opt.xAssign() != "unique") { + if (!m_allowXUnique || v3Global.opt.xAssign() != "unique") { // All X bits just become 0; fastest simulation, but not nice V3Number numnew(nodep, numb1.width()); if (v3Global.opt.xAssign() == "1") { @@ -327,10 +331,11 @@ private: // We use the special XTEMP type so it doesn't break pure functions UASSERT_OBJ(m_modp, nodep, "X number not under module"); AstVar* const newvarp - = new AstVar(nodep->fileline(), AstVarType::XTEMP, m_xrandNames.get(nodep), + = new AstVar(nodep->fileline(), VVarType::XTEMP, m_xrandNames.get(nodep), VFlagLogicPacked(), nodep->width()); + newvarp->lifetime(VLifetime::STATIC); ++m_statUnkVars; - AstNRelinker replaceHandle; + VNRelinker replaceHandle; nodep->unlinkFrBack(&replaceHandle); AstNodeVarRef* const newref1p = new AstVarRef(nodep->fileline(), newvarp, VAccess::READ); @@ -386,7 +391,7 @@ private: VL_DO_DANGLING(condp->deleteTree(), condp); } else if (!lvalue) { // SEL(...) -> COND(LTE(bit<=maxmsb), ARRAYSEL(...), {width{1'bx}}) - AstNRelinker replaceHandle; + VNRelinker replaceHandle; nodep->unlinkFrBack(&replaceHandle); V3Number xnum(nodep, nodep->width()); xnum.setAllBitsX(); @@ -445,7 +450,7 @@ private: // Making a scalar would break if we're making an array && !VN_IS(nodep->dtypep()->skipRefp(), NodeArrayDType)) { // ARRAYSEL(...) -> COND(LT(bitunlinkFrBack(&replaceHandle); V3Number xnum(nodep, nodep->width()); if (nodep->isString()) { @@ -462,7 +467,7 @@ private: iterate(newp); } else if (!lvalue) { // Mid-multidimension read, just use zero // ARRAYSEL(...) -> ARRAYSEL(COND(LT(bitbitp()->unlinkFrBack(&replaceHandle); AstNode* const newp = new AstCondBound( bitp->fileline(), condp, bitp, diff --git a/src/V3Unknown.h b/src/V3Unknown.h index 0ad1a942c..792eed1ea 100644 --- a/src/V3Unknown.h +++ b/src/V3Unknown.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,7 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; //============================================================================ diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp index 22b14570f..429708301 100644 --- a/src/V3Unroll.cpp +++ b/src/V3Unroll.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -39,7 +39,7 @@ //###################################################################### // Unroll state, as a visitor of each AstNode -class UnrollVisitor final : public AstNVisitor { +class UnrollVisitor final : public VNVisitor { private: // STATE AstVar* m_forVarp; // Iterator variable diff --git a/src/V3Unroll.h b/src/V3Unroll.h index 91776df3e..91c5b3386 100644 --- a/src/V3Unroll.h +++ b/src/V3Unroll.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3VariableOrder.cpp b/src/V3VariableOrder.cpp index bf6d9c505..8c6d91edd 100644 --- a/src/V3VariableOrder.cpp +++ b/src/V3VariableOrder.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -78,7 +78,7 @@ unsigned VarTspSorter::s_serialNext = 0; class VariableOrder final { // NODE STATE // AstVar::user1() -> attributes, via m_attributes - const AstUser1InUse m_user1InUse; // AstVar + const VNUser1InUse m_user1InUse; // AstVar struct VarAttributes { uint32_t stratum; // Roughly equivalent to alignment requirement, to avoid padding diff --git a/src/V3VariableOrder.h b/src/V3VariableOrder.h index 0b84c9894..e83b65af0 100644 --- a/src/V3VariableOrder.h +++ b/src/V3VariableOrder.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Waiver.h b/src/V3Waiver.h index cff1df336..2203cc52b 100644 --- a/src/V3Waiver.h +++ b/src/V3Waiver.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Width.cpp b/src/V3Width.cpp index d8ab99fce..743f641a4 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -101,9 +101,17 @@ std::ostream& operator<<(std::ostream& str, const Determ& rhs) { return str << s_det[rhs]; } -enum Castable : uint8_t { UNSUPPORTED, COMPATIBLE, DYNAMIC_ENUM, DYNAMIC_CLASS, INCOMPATIBLE }; +enum Castable : uint8_t { + UNSUPPORTED, + COMPATIBLE, + ENUM_EXPLICIT, + ENUM_IMPLICIT, + DYNAMIC_CLASS, + INCOMPATIBLE +}; std::ostream& operator<<(std::ostream& str, const Castable& rhs) { - static const char* const s_det[] = {"UNSUP", "COMPAT", "DYN_ENUM", "DYN_CLS", "INCOMPAT"}; + static const char* const s_det[] + = {"UNSUP", "COMPAT", "ENUM_EXP", "ENUM_IMP", "DYN_CLS", "INCOMPAT"}; return str << s_det[rhs]; } @@ -172,7 +180,7 @@ std::ostream& operator<<(std::ostream& str, const WidthVP* vup) { //###################################################################### class WidthClearVisitor final { - // Rather than a AstNVisitor, can just quickly touch every node + // Rather than a VNVisitor, can just quickly touch every node void clearWidthRecurse(AstNode* nodep) { for (; nodep; nodep = nodep->nextp()) { nodep->didWidth(false); @@ -195,10 +203,10 @@ public: //###################################################################### -class WidthVisitor final : public AstNVisitor { +class WidthVisitor final : public VNVisitor { private: // TYPES - using TableMap = std::map, AstVar*>; + using TableMap = std::map, AstVar*>; using PatVecMap = std::map; // STATE @@ -216,6 +224,8 @@ private: std::map m_queueDTypeIndexed; // Queues with given index type + static constexpr int ENUM_LOOKUP_BITS = 16; // Maximum # bits to make enum lookup table + // ENUMS enum ExtendRule : uint8_t { EXTEND_EXP, // Extend if expect sign and node signed, e.g. node=y in ADD(x,y), "x + y" @@ -1327,34 +1337,34 @@ private: if (nodep->dimp()) userIterateAndNext(nodep->dimp(), WidthVP(SELF, BOTH).p()); // Don't iterate children, don't want to lose VarRef. switch (nodep->attrType()) { - case AstAttrType::VAR_BASE: - case AstAttrType::MEMBER_BASE: - case AstAttrType::ENUM_BASE: + case VAttrType::VAR_BASE: + case VAttrType::MEMBER_BASE: + case VAttrType::ENUM_BASE: // Soon to be handled in V3LinkWidth SEL generation, under attrp() and newSubLsbOf break; - case AstAttrType::DIM_DIMENSIONS: - case AstAttrType::DIM_UNPK_DIMENSIONS: { + case VAttrType::DIM_DIMENSIONS: + case VAttrType::DIM_UNPK_DIMENSIONS: { UASSERT_OBJ(nodep->fromp() && nodep->fromp()->dtypep(), nodep, "Unsized expression"); const std::pair dim = nodep->fromp()->dtypep()->dimensions(true); - const int val = (nodep->attrType() == AstAttrType::DIM_UNPK_DIMENSIONS - ? dim.second - : (dim.first + dim.second)); + const int val + = (nodep->attrType() == VAttrType::DIM_UNPK_DIMENSIONS ? dim.second + : (dim.first + dim.second)); nodep->replaceWith(new AstConst(nodep->fileline(), AstConst::Signed32(), val)); VL_DO_DANGLING(nodep->deleteTree(), nodep); break; } - case AstAttrType::DIM_BITS: - case AstAttrType::DIM_HIGH: - case AstAttrType::DIM_INCREMENT: - case AstAttrType::DIM_LEFT: - case AstAttrType::DIM_LOW: - case AstAttrType::DIM_RIGHT: - case AstAttrType::DIM_SIZE: { + case VAttrType::DIM_BITS: + case VAttrType::DIM_HIGH: + case VAttrType::DIM_INCREMENT: + case VAttrType::DIM_LEFT: + case VAttrType::DIM_LOW: + case VAttrType::DIM_RIGHT: + case VAttrType::DIM_SIZE: { UASSERT_OBJ(nodep->fromp() && nodep->fromp()->dtypep(), nodep, "Unsized expression"); AstNodeDType* const dtypep = nodep->fromp()->dtypep(); if (VN_IS(dtypep, QueueDType)) { switch (nodep->attrType()) { - case AstAttrType::DIM_SIZE: { + case VAttrType::DIM_SIZE: { AstNode* const newp = new AstCMethodHard( nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size", nullptr); newp->dtypeSetSigned32(); @@ -1364,15 +1374,15 @@ private: VL_DO_DANGLING(nodep->deleteTree(), nodep); break; } - case AstAttrType::DIM_LEFT: - case AstAttrType::DIM_LOW: { + case VAttrType::DIM_LEFT: + case VAttrType::DIM_LOW: { AstNode* const newp = new AstConst(nodep->fileline(), AstConst::Signed32(), 0); nodep->replaceWith(newp); VL_DO_DANGLING(nodep->deleteTree(), nodep); break; } - case AstAttrType::DIM_RIGHT: - case AstAttrType::DIM_HIGH: { + case VAttrType::DIM_RIGHT: + case VAttrType::DIM_HIGH: { AstNode* const sizep = new AstCMethodHard( nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size", nullptr); sizep->dtypeSetSigned32(); @@ -1385,14 +1395,14 @@ private: VL_DO_DANGLING(nodep->deleteTree(), nodep); break; } - case AstAttrType::DIM_INCREMENT: { + case VAttrType::DIM_INCREMENT: { AstNode* const newp = new AstConst(nodep->fileline(), AstConst::Signed32(), -1); nodep->replaceWith(newp); VL_DO_DANGLING(nodep->deleteTree(), nodep); break; } - case AstAttrType::DIM_BITS: { + case VAttrType::DIM_BITS: { nodep->v3warn(E_UNSUPPORTED, "Unsupported: $bits for queue"); break; } @@ -1428,17 +1438,15 @@ private: UASSERT_OBJ(nodep->fromp() && dtypep, nodep, "Unsized expression"); AstVar* const varp = dimensionVarp(dtypep, nodep->attrType(), msbdim); AstNode* const dimp = nodep->dimp()->unlinkFrBack(); - AstVarRef* const varrefp - = new AstVarRef(nodep->fileline(), varp, VAccess::READ); - varrefp->classOrPackagep(v3Global.rootp()->dollarUnitPkgAddp()); - AstNode* const newp = new AstArraySel(nodep->fileline(), varrefp, dimp); + AstNode* const newp + = new AstArraySel{nodep->fileline(), newVarRefDollarUnit(varp), dimp}; nodep->replaceWith(newp); VL_DO_DANGLING(nodep->deleteTree(), nodep); } } break; } - case AstAttrType::TYPENAME: { + case VAttrType::TYPENAME: { UASSERT_OBJ(nodep->fromp(), nodep, "Unprovided expression"); const string result = nodep->fromp()->dtypep()->prettyDTypeName(); AstNode* const newp = new AstConst(nodep->fileline(), AstConst::String(), result); @@ -1474,7 +1482,7 @@ private: UASSERT_OBJ(basicp->width() <= 1, basicp, "must be 1 bit but actually " << basicp->width() << " bits"); AstBasicDType* const newp = new AstBasicDType( - basicp->fileline(), AstBasicDTypeKwd::LOGIC, basicp->numeric()); + basicp->fileline(), VBasicDTypeKwd::LOGIC, basicp->numeric()); newp->widthForce(1, 1); basicp->replaceWith(newp); VL_DO_DANGLING(pushDeletep(basicp), basicp); @@ -1665,7 +1673,7 @@ private: if (castable == DYNAMIC_CLASS) { // Keep in place, will compute at runtime return; - } else if (castable == DYNAMIC_ENUM) { + } else if (castable == ENUM_EXPLICIT || castable == ENUM_IMPLICIT) { // TODO is from is a constant we could simplify, though normal constant // elimination should do much the same // Form: "( ((v > size) ? false : enum_valid[v[N:0]]) @@ -1673,20 +1681,27 @@ private: auto* const enumDtp = VN_AS(toDtp, EnumDType); UASSERT_OBJ(enumDtp, nodep, "$cast determined as enum, but not enum type"); const uint64_t maxval = enumMaxValue(nodep, enumDtp); - const int selwidth = V3Number::log2b(maxval) + 1; // Width to address a bit - AstVar* const varp - = enumVarp(enumDtp, AstAttrType::ENUM_VALID, (1ULL << selwidth) - 1); - AstVarRef* const varrefp = new AstVarRef(fl, varp, VAccess::READ); - varrefp->classOrPackagep(v3Global.rootp()->dollarUnitPkgAddp()); - FileLine* const fl_nowarn = new FileLine(fl); - fl_nowarn->warnOff(V3ErrorCode::WIDTH, true); - auto* const testp = new AstCond{ - fl, - new AstGt{fl_nowarn, nodep->fromp()->cloneTree(false), - new AstConst{fl_nowarn, AstConst::Unsized64{}, maxval}}, - new AstConst{fl, AstConst::BitFalse{}}, - new AstArraySel{fl, varrefp, - new AstSel{fl, nodep->fromp()->cloneTree(false), 0, selwidth}}}; + const bool assoc = maxval > ENUM_LOOKUP_BITS; + AstNode* testp = nullptr; + if (assoc) { + AstVar* const varp = enumVarp(enumDtp, VAttrType::ENUM_VALID, true, 0); + testp = new AstAssocSel{fl, newVarRefDollarUnit(varp), + nodep->fromp()->cloneTree(false)}; + } else { + const int selwidth = V3Number::log2b(maxval) + 1; // Width to address a bit + AstVar* const varp + = enumVarp(enumDtp, VAttrType::ENUM_VALID, false, (1ULL << selwidth) - 1); + FileLine* const fl_nowarn = new FileLine(fl); + fl_nowarn->warnOff(V3ErrorCode::WIDTH, true); + testp = new AstCond{ + fl, + new AstGt{fl_nowarn, nodep->fromp()->cloneTree(false), + new AstConst{fl_nowarn, AstConst::Unsized64{}, maxval}}, + new AstConst{fl, AstConst::BitFalse{}}, + new AstArraySel{ + fl, newVarRefDollarUnit(varp), + new AstSel{fl, nodep->fromp()->cloneTree(false), 0, selwidth}}}; + } newp = new AstCond{fl, testp, new AstExprStmt{fl, new AstAssign{fl, nodep->top()->unlinkFrBack(), @@ -1753,7 +1768,8 @@ private: << toDtp->prettyDTypeNameQ() << " from " << fromDtp->prettyDTypeNameQ()); bad = true; - } else if (castable == COMPATIBLE || castable == DYNAMIC_ENUM) { + } else if (castable == COMPATIBLE || castable == ENUM_IMPLICIT + || castable == ENUM_EXPLICIT) { ; // Continue } else if (castable == DYNAMIC_CLASS) { nodep->v3error("Dynamic, not static cast, required to cast " @@ -2222,8 +2238,8 @@ private: AstNodeDType* const vdtypep = m_vup->dtypeNullp(); UASSERT_OBJ(vdtypep, nodep, "InitArray type not assigned by AstPattern/Var visitor"); nodep->dtypep(vdtypep); - if (const AstNodeArrayDType* const arrayp - = VN_CAST(vdtypep->skipRefp(), NodeArrayDType)) { + const AstNodeDType* const arrayp = vdtypep->skipRefp(); + if (VN_IS(arrayp, NodeArrayDType) || VN_IS(arrayp, AssocArrayDType)) { userIterateChildren(nodep, WidthVP(arrayp->subDTypep(), BOTH).p()); } else { UINFO(1, "dtype object " << vdtypep->skipRefp() << endl); @@ -2599,13 +2615,13 @@ private: nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } else if (nodep->name() == "name" || nodep->name() == "next" || nodep->name() == "prev") { - AstAttrType attrType; + VAttrType attrType; if (nodep->name() == "name") { - attrType = AstAttrType::ENUM_NAME; + attrType = VAttrType::ENUM_NAME; } else if (nodep->name() == "next") { - attrType = AstAttrType::ENUM_NEXT; + attrType = VAttrType::ENUM_NEXT; } else if (nodep->name() == "prev") { - attrType = AstAttrType::ENUM_PREV; + attrType = VAttrType::ENUM_PREV; } else { nodep->v3fatalSrc("Bad case"); } @@ -2633,17 +2649,23 @@ private: } // Need a runtime lookup table. Yuk. const uint64_t msbdim = enumMaxValue(nodep, adtypep); - const int selwidth = V3Number::log2b(msbdim) + 1; // Width to address a bit - AstVar* const varp = enumVarp(adtypep, attrType, (1ULL << selwidth) - 1); - AstVarRef* const varrefp = new AstVarRef(nodep->fileline(), varp, VAccess::READ); - varrefp->classOrPackagep(v3Global.rootp()->dollarUnitPkgAddp()); - AstNode* const newp = new AstArraySel( - nodep->fileline(), varrefp, - // Select in case widths are off due to msblen!=width - // We return "random" values if outside the range, which is fine - // as next/previous on illegal values just need something good out - new AstSel(nodep->fileline(), nodep->fromp()->unlinkFrBack(), 0, selwidth)); - nodep->replaceWith(newp); + const bool assoc = msbdim > ENUM_LOOKUP_BITS; + if (assoc) { + AstVar* const varp = enumVarp(adtypep, attrType, true, 0); + AstNode* const newp = new AstAssocSel{nodep->fileline(), newVarRefDollarUnit(varp), + nodep->fromp()->unlinkFrBack()}; + nodep->replaceWith(newp); + } else { + const int selwidth = V3Number::log2b(msbdim) + 1; // Width to address a bit + AstVar* const varp = enumVarp(adtypep, attrType, false, (1ULL << selwidth) - 1); + AstNode* const newp = new AstArraySel( + nodep->fileline(), newVarRefDollarUnit(varp), + // Select in case widths are off due to msblen!=width + // We return "random" values if outside the range, which is fine + // as next/previous on illegal values just need something good out + new AstSel(nodep->fileline(), nodep->fromp()->unlinkFrBack(), 0, selwidth)); + nodep->replaceWith(newp); + } VL_DO_DANGLING(nodep->deleteTree(), nodep); } else { nodep->v3error("Unknown built-in enum method " << nodep->prettyNameQ()); @@ -2667,6 +2689,7 @@ private: nodep->name(), // first/last/next/prev index_exprp->unlinkFrBack()); newp->dtypeSetSigned32(); + if (!nodep->firstAbovep()) newp->makeStatement(); } else if (nodep->name() == "exists") { // function int exists(input index) // IEEE really should have made this a "bit" return methodOkArguments(nodep, 1, 1); @@ -3328,7 +3351,7 @@ private: if (patp->lhssp()->nextp()) { // Can't just addNext, as would add to end of all members. // So detach, add next and reattach - AstNRelinker relinkHandle; + VNRelinker relinkHandle; patp->unlinkFrBack(&relinkHandle); while (AstNode* const movep = patp->lhssp()->nextp()) { movep->unlinkFrBack(); // Not unlinkFrBackWithNext, just one @@ -3771,6 +3794,167 @@ private: userIterateAndNext(nodep->resultp(), m_vup); nodep->dtypeFrom(nodep->resultp()); } + virtual void visit(AstForeach* nodep) override { + const AstSelLoopVars* const loopsp = VN_CAST(nodep->arrayp(), SelLoopVars); + UASSERT_OBJ(loopsp, nodep, "No loop variables under foreach"); + // if (debug()) nodep->dumpTree(cout, "-foreach-old: "); + AstNode* const fromp = loopsp->fromp(); + userIterateAndNext(fromp, WidthVP(SELF, BOTH).p()); + AstNodeDType* fromDtp = fromp->dtypep()->skipRefp(); + // Split into for loop + AstNode* bodyp = nodep->bodysp(); // Might be null + if (bodyp) bodyp->unlinkFrBackWithNext(); + // We record where the body needs to eventually go with bodyPointp + // (Can't use bodyp as might be null) + AstNode* lastBodyPointp = nullptr; + AstNode* newp = nullptr; + // Major dimension first + while (AstNode* argsp + = loopsp->elementsp()) { // Loop advances due to below varp->unlinkFrBack() + const bool empty = VN_IS(argsp, Empty); + AstVar* const varp = VN_CAST(argsp, Var); + UASSERT_OBJ(varp || empty, argsp, "Missing foreach loop variable"); + if (varp) varp->usedLoopIdx(true); + argsp->unlinkFrBack(); + if (!fromDtp) { + argsp->v3error("foreach loop variables exceed number of indices of array"); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + return; + } + fromDtp = fromDtp->skipRefp(); + UINFO(9, "- foreachArg " << argsp << endl); + UINFO(9, "- from on " << fromp << endl); + UINFO(9, "- from dtp " << fromDtp << endl); + + FileLine* const fl = argsp->fileline(); + AstNode* bodyPointp = new AstBegin{fl, "[EditWrapper]", nullptr}; + AstNode* loopp = nullptr; + if (const AstNodeArrayDType* const adtypep = VN_CAST(fromDtp, NodeArrayDType)) { + if (varp) { + loopp = createForeachLoopRanged(nodep, bodyPointp, varp, adtypep->declRange()); + } + // Prep for next + fromDtp = fromDtp->subDTypep(); + } else if (AstBasicDType* const adtypep = VN_CAST(fromDtp, BasicDType)) { + if (!adtypep->isRanged()) { + argsp->v3error("Illegal to foreach loop on basic '" + fromDtp->prettyTypeName() + + "'"); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + return; + } + if (varp) { + loopp = createForeachLoopRanged(nodep, bodyPointp, varp, adtypep->declRange()); + } + // Prep for next + fromDtp = nullptr; + } else if (VN_IS(fromDtp, DynArrayDType) || VN_IS(fromDtp, QueueDType)) { + if (varp) { + auto* const leftp = new AstConst{fl, AstConst::Signed32{}, 0}; + auto* const sizep + = new AstCMethodHard{fl, fromp->cloneTree(false), "size", nullptr}; + sizep->dtypeSetSigned32(); + sizep->didWidth(true); + sizep->protect(false); + AstNode* const condp + = new AstLt{fl, new AstVarRef{fl, varp, VAccess::READ}, sizep}; + AstNode* const incp = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1}, + new AstVarRef{fl, varp, VAccess::READ}}; + loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, condp, incp); + } + // Prep for next + fromDtp = fromDtp->subDTypep(); + } else if (const AstAssocArrayDType* const adtypep + = VN_CAST(fromDtp, AssocArrayDType)) { + // Make this: var KEY_TYPE index; + // bit index__Vfirst; + // index__Vfirst = 0; + // if (0 != array.first(index)) + // do body while (index__Vfirst || 0 != array.next(index)) + varp->dtypeFrom(adtypep->keyDTypep()); + AstVar* const first_varp = new AstVar{ + fl, VVarType::BLOCKTEMP, varp->name() + "__Vfirst", VFlagBitPacked{}, 1}; + first_varp->usedLoopIdx(true); + AstNode* const firstp = new AstMethodCall{ + fl, fromp->cloneTree(false), "first", + new AstArg{fl, "", new AstVarRef{fl, varp, VAccess::READWRITE}}}; + AstNode* const nextp = new AstMethodCall{ + fl, fromp->cloneTree(false), "next", + new AstArg{fl, "", new AstVarRef{fl, varp, VAccess::READWRITE}}}; + AstNode* const first_clearp + = new AstAssign{fl, new AstVarRef{fl, first_varp, VAccess::WRITE}, + new AstConst{fl, AstConst::BitFalse{}}}; + auto* const orp = new AstLogOr{fl, new AstVarRef{fl, first_varp, VAccess::READ}, + new AstNeq{fl, new AstConst{fl, 0}, nextp}}; + orp->sideEffect(true); + AstNode* const whilep = new AstWhile{fl, orp, first_clearp}; + first_clearp->addNext(bodyPointp); + AstNode* const ifbodyp + = new AstAssign{fl, new AstVarRef{fl, first_varp, VAccess::WRITE}, + new AstConst{fl, AstConst::BitTrue{}}}; + ifbodyp->addNext(whilep); + AstNode* const stmtsp = varp; // New statements for under new Begin + stmtsp->addNext(first_varp); + stmtsp->addNext( + new AstIf{fl, new AstNeq{fl, new AstConst{fl, 0}, firstp}, ifbodyp}); + loopp = new AstBegin{nodep->fileline(), "", stmtsp, false, true}; + // Prep for next + fromDtp = fromDtp->subDTypep(); + } else { + argsp->v3error("Illegal to foreach loop on '" + fromDtp->prettyTypeName() + "'"); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + return; + } + // New loop goes UNDER previous loop + if (varp) { + if (!newp) { + newp = loopp; + } else { + lastBodyPointp->replaceWith(loopp); + } + lastBodyPointp = bodyPointp; + } + } + // The parser validates we don't have "foreach (array[,,,])" + UASSERT_OBJ(newp, nodep, "foreach has no non-empty loop variable"); + if (bodyp) { + lastBodyPointp->replaceWith(bodyp); + } else { + lastBodyPointp->unlinkFrBack(); + } + // if (debug()) newp->dumpTreeAndNext(cout, "-foreach-new: "); + nodep->replaceWith(newp); + VL_DO_DANGLING(lastBodyPointp->deleteTree(), lastBodyPointp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + } + AstNode* createForeachLoopRanged(AstForeach* nodep, AstNode* bodysp, AstVar* varp, + const VNumRange& declRange) { + FileLine* const fl = varp->fileline(); + auto* const leftp = new AstConst{fl, AstConst::Signed32{}, declRange.left()}; + auto* const rightp = new AstConst{fl, AstConst::Signed32{}, declRange.right()}; + AstNode* condp; + AstNode* incp; + if (declRange.left() < declRange.right()) { + condp = new AstLte{fl, new AstVarRef{fl, varp, VAccess::READ}, rightp}; + incp = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1}, + new AstVarRef{fl, varp, VAccess::READ}}; + } else { + condp = new AstGte{fl, new AstVarRef{fl, varp, VAccess::READ}, rightp}; + incp = new AstSub{fl, new AstVarRef{fl, varp, VAccess::READ}, + new AstConst{fl, AstConst::Signed32{}, 1}}; + } + return createForeachLoop(nodep, bodysp, varp, leftp, condp, incp); + } + AstNode* createForeachLoop(AstForeach* nodep, AstNode* bodysp, AstVar* varp, AstNode* leftp, + AstNode* condp, AstNode* incp) { + FileLine* const fl = varp->fileline(); + auto* const whilep = new AstWhile{ + fl, condp, bodysp, new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, incp}}; + AstNode* const stmtsp = varp; // New statements for under new Begin + stmtsp->addNext(new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, leftp}); + stmtsp->addNext(whilep); + AstNode* const newp = new AstBegin{nodep->fileline(), "", stmtsp, false, true}; + return newp; + } virtual void visit(AstNodeAssign* nodep) override { // IEEE-2012 10.7, 11.8.2, 11.8.3, 11.5: (Careful of 11.8.1 which is @@ -3841,6 +4025,12 @@ private: } } + virtual void visit(AstRelease* nodep) override { + userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p()); + UASSERT_OBJ(nodep->lhsp()->dtypep(), nodep, "How can LValue be untyped?"); + UASSERT_OBJ(nodep->lhsp()->dtypep()->widthSized(), nodep, "How can LValue be unsized?"); + } + virtual void visit(AstSFormatF* nodep) override { // Excludes NodeDisplay, see below if (m_vup && !m_vup->prelim()) return; // Can be called as statement or function @@ -3894,7 +4084,7 @@ private: || VN_IS(dtypep, QueueDType)) { added = true; newFormat += "%@"; - AstNRelinker handle; + VNRelinker handle; argp->unlinkFrBack(&handle); AstCMath* const newp = new AstCMath(nodep->fileline(), "VL_TO_STRING(", 0, true); @@ -3988,10 +4178,10 @@ private: string text = nodep->fmtp()->text(); if (text.empty()) text = "Elaboration system task message (IEEE 1800-2017 20.11)"; switch (nodep->displayType()) { - case AstDisplayType::DT_INFO: nodep->v3warn(USERINFO, text); break; - case AstDisplayType::DT_ERROR: nodep->v3warn(USERERROR, text); break; - case AstDisplayType::DT_WARNING: nodep->v3warn(USERWARN, text); break; - case AstDisplayType::DT_FATAL: nodep->v3warn(USERFATAL, text); break; + case VDisplayType::DT_INFO: nodep->v3warn(USERINFO, text); break; + case VDisplayType::DT_ERROR: nodep->v3warn(USERERROR, text); break; + case VDisplayType::DT_WARNING: nodep->v3warn(USERWARN, text); break; + case VDisplayType::DT_FATAL: nodep->v3warn(USERFATAL, text); break; default: UASSERT_OBJ(false, nodep, "Unexpected elaboration display type"); } VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); @@ -4213,26 +4403,26 @@ private: modDTypep = modDTypep->skipRefp(); conDTypep = conDTypep->skipRefp(); AstNodeDType* subDTypep = modDTypep; - const int pinwidth = modDTypep->width(); + const int modwidth = modDTypep->width(); const int conwidth = conDTypep->width(); if (conDTypep == modDTypep // If match, we're golden || similarDTypeRecurse(conDTypep, modDTypep)) { userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p()); } else if (m_cellp->rangep()) { const int numInsts = m_cellp->rangep()->elementsConst(); - if (conwidth == pinwidth) { + if (conwidth == modwidth) { // Arrayed instants: widths match so connect to each instance subDTypep = conDTypep; // = same expr dtype - } else if (conwidth == numInsts * pinwidth) { + } else if (conwidth == numInsts * modwidth) { // Arrayed instants: one bit for each of the instants (each - // assign is 1 pinwidth wide) + // assign is 1 modwidth wide) subDTypep = conDTypep; // = same expr dtype (but numInst*pin_dtype) } else { // Must be a error according to spec // (Because we need to know if to connect to one or all instants) nodep->v3error(ucfirst(nodep->prettyOperatorName()) << " as part of a module instance array" - << " requires " << pinwidth << " or " << pinwidth * numInsts + << " requires " << modwidth << " or " << modwidth * numInsts << " bits, but connection's " << nodep->exprp()->prettyTypeName() << " generates " << conwidth << " bits. (IEEE 1800-2017 23.3.3)"); @@ -4248,12 +4438,12 @@ private: << " data type but connection is " << conDTypep->prettyDTypeNameQ() << " data type."); } else if (nodep->modVarp()->isTristate()) { - if (pinwidth != conwidth) { + if (modwidth != conwidth) { // Ideally should call pinReconnectSimple which would tolerate this // then have a conversion warning nodep->v3warn(E_UNSUPPORTED, "Unsupported: " << ucfirst(nodep->prettyOperatorName()) - << " to inout signal requires " << pinwidth + << " to inout signal requires " << modwidth << " bits, but connection's " << nodep->exprp()->prettyTypeName() << " generates " << conwidth << " bits."); @@ -4334,9 +4524,9 @@ private: // Very much like like an pin const AstNodeDType* const conDTypep = nodep->exprp()->dtypep(); const int numInsts = nodep->rangep()->elementsConst(); - const int pinwidth = numInsts; + const int modwidth = numInsts; const int conwidth = conDTypep->width(); - if (conwidth == 1 && pinwidth > 1) { // Multiple connections + if (conwidth == 1 && modwidth > 1) { // Multiple connections AstNodeDType* const subDTypep = nodep->findLogicDType(1, 1, conDTypep->numeric()); userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p()); AstNode* const newp = new AstReplicate(nodep->fileline(), @@ -4354,8 +4544,10 @@ private: // Grab width from the output variable (if it's a function) if (nodep->didWidth()) return; if (nodep->doingWidth()) { - nodep->v3warn(E_UNSUPPORTED, "Unsupported: Recursive function or task call"); - nodep->dtypeSetBit(); + UINFO(5, "Recursive function or task call: " << nodep); + nodep->v3warn(E_UNSUPPORTED, "Unsupported: Recursive function or task call: " + << nodep->prettyNameQ()); + nodep->recursive(true); nodep->didWidth(true); return; } @@ -4370,7 +4562,8 @@ private: // Would use user1 etc, but V3Width called from too many places to spend a user nodep->doingWidth(true); m_ftaskp = nodep; - userIterateChildren(nodep, nullptr); + // First width the function variable, as if is a recursive function we need data type + if (nodep->fvarp()) userIterate(nodep->fvarp(), nullptr); if (nodep->isConstructor()) { // Pretend it's void so less special casing needed when look at dtypes nodep->dtypeSetVoid(); @@ -4379,6 +4572,7 @@ private: UASSERT_OBJ(m_funcp, nodep, "FTask with function variable, but isn't a function"); nodep->dtypeFrom(nodep->fvarp()); // Which will get it from fvarp()->dtypep() } + userIterateChildren(nodep, nullptr); nodep->didWidth(true); nodep->doingWidth(false); m_funcp = nullptr; @@ -4435,11 +4629,11 @@ private: } if (portDtypep->basicp()->width() != pinDtypep->basicp()->width() || (portDtypep->basicp()->keyword() != pinDtypep->basicp()->keyword() - && !(portDtypep->basicp()->keyword() == AstBasicDTypeKwd::LOGIC_IMPLICIT - && pinDtypep->basicp()->keyword() == AstBasicDTypeKwd::LOGIC) - && !(portDtypep->basicp()->keyword() == AstBasicDTypeKwd::LOGIC + && !(portDtypep->basicp()->keyword() == VBasicDTypeKwd::LOGIC_IMPLICIT + && pinDtypep->basicp()->keyword() == VBasicDTypeKwd::LOGIC) + && !(portDtypep->basicp()->keyword() == VBasicDTypeKwd::LOGIC && pinDtypep->basicp()->keyword() - == AstBasicDTypeKwd::LOGIC_IMPLICIT))) { + == VBasicDTypeKwd::LOGIC_IMPLICIT))) { pinp->v3warn(E_UNSUPPORTED, "Shape of the argument does not match the shape of the parameter " << "(" << pinDtypep->basicp()->prettyDTypeNameQ() << " v.s. " @@ -4473,7 +4667,7 @@ private: if (portp->attrSFormat() && (!VN_IS(pinp, SFormatF) || pinp->nextp())) { // Not already done UINFO(4, " sformat via metacomment: " << nodep << endl); - AstNRelinker handle; + VNRelinker handle; argp->unlinkFrBackWithNext(&handle); // Format + additional args, if any AstNode* argsp = nullptr; while (AstArg* const nextargp = VN_AS(argp->nextp(), Arg)) { @@ -4499,15 +4693,15 @@ private: // Connection list is now incorrect (has extra args in it). goto reloop; // so exit early; next loop will correct it } // - else if (portp->basicp() && portp->basicp()->keyword() == AstBasicDTypeKwd::STRING + else if (portp->basicp() && portp->basicp()->keyword() == VBasicDTypeKwd::STRING && !VN_IS(pinp, CvtPackString) && !VN_IS(pinp, SFormatF) // Already generates a string && !VN_IS(portp->dtypep(), UnpackArrayDType) // Unpacked array must match && !(VN_IS(pinp, VarRef) && VN_AS(pinp, VarRef)->varp()->basicp()->keyword() - == AstBasicDTypeKwd::STRING)) { + == VBasicDTypeKwd::STRING)) { UINFO(4, " Add CvtPackString: " << pinp << endl); - AstNRelinker handle; + VNRelinker handle; pinp->unlinkFrBack(&handle); // No next, that's the next pin AstNode* const newp = new AstCvtPackString(pinp->fileline(), pinp); handle.relink(newp); @@ -4855,7 +5049,7 @@ private: void visit_negate_not(AstNodeUniop* nodep, bool real_ok) { // CALLER: (real_ok=false) Not - // CALLER: (real_ok=true) Negate + // CALLER: (real_ok=true) Negate - allow real numbers // Signed: From lhs // IEEE-2012 Table 11-21: // Widths: out width = lhs width @@ -4882,7 +5076,14 @@ private: AstNodeDType* const expDTypep = m_vup->dtypeOverridep(nodep->dtypep()); nodep->dtypep(expDTypep); // Propagate expression type to negation AstNodeDType* const subDTypep = expDTypep; - iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP); + // Some warning suppressions + bool lhsWarn = true; + if (VN_IS(nodep, Negate)) { + // Warn if user wants extra bit from carry + if (subDTypep->widthMin() == (nodep->lhsp()->widthMin() + 1)) lhsWarn = false; + } + iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP, + lhsWarn); } } @@ -5130,7 +5331,7 @@ private: nodep = newp; } else if (expWidth < nodep->width()) { // Trunc - Extract - AstNRelinker linker; + VNRelinker linker; nodep->unlinkFrBack(&linker); AstNode* const newp = new AstSel(nodep->fileline(), nodep, 0, expWidth); newp->didWidth(true); // Don't replace dtype with unsigned @@ -5138,7 +5339,7 @@ private: nodep = newp; } else { // Extend - AstNRelinker linker; + VNRelinker linker; nodep->unlinkFrBack(&linker); bool doSigned = false; switch (extendRule) { @@ -5183,7 +5384,7 @@ private: VL_DANGLING(nodep); nodep = newp; } else { - AstNRelinker linker; + VNRelinker linker; nodep->unlinkFrBack(&linker); AstNode* const newp = new AstRedOr(nodep->fileline(), nodep); linker.relink(newp); @@ -5337,7 +5538,7 @@ private: // For DOUBLE under a logical op, add implied test against zero, never a warning if (underp && underp->isDouble()) { UINFO(6, " spliceCvtCmpD0: " << underp << endl); - AstNRelinker linker; + VNRelinker linker; underp->unlinkFrBack(&linker); AstNode* const newp = new AstNeqD(nodep->fileline(), underp, @@ -5346,7 +5547,7 @@ private: } else if (VN_IS(underp->dtypep(), ClassRefDType) || (VN_IS(underp->dtypep(), BasicDType) && VN_AS(underp->dtypep(), BasicDType)->keyword() - == AstBasicDTypeKwd::CHANDLE)) { + == VBasicDTypeKwd::CHANDLE)) { // Allow warning-free "if (handle)" VL_DO_DANGLING(fixWidthReduce(underp), underp); // Changed } else if (!underp->dtypep()->basicp()) { @@ -5543,7 +5744,7 @@ private: // We don't warn here, "2.0 * 2" is common and reasonable if (nodep && !nodep->dtypep()->skipRefp()->isDouble()) { UINFO(6, " spliceCvtD: " << nodep << endl); - AstNRelinker linker; + VNRelinker linker; nodep->unlinkFrBack(&linker); AstNode* newp; if (nodep->dtypep()->skipRefp()->isSigned()) { @@ -5562,7 +5763,7 @@ private: // 11.8.2: Argument to convert is self-determined if (nodep && nodep->dtypep()->skipRefp()->isDouble()) { UINFO(6, " spliceCvtS: " << nodep << endl); - AstNRelinker linker; + VNRelinker linker; nodep->unlinkFrBack(&linker); if (const AstConst* const constp = VN_CAST(nodep, Const)) { // We convert to/from vlsint32 rather than use floor() as want to make sure is @@ -5588,7 +5789,7 @@ private: // 11.8.2: Argument to convert is self-determined if (nodep && !(nodep->dtypep()->basicp() && nodep->dtypep()->basicp()->isString())) { UINFO(6, " spliceCvtString: " << nodep << endl); - AstNRelinker linker; + VNRelinker linker; nodep->unlinkFrBack(&linker); AstNode* const newp = new AstCvtPackString(nodep->fileline(), nodep); linker.relink(newp); @@ -5604,15 +5805,15 @@ private: if (!nodep->dtypep()) nodep->dtypeFrom(nodep->lhsp()); // To simplify callers, some node types don't need to change switch (nodep->type()) { - case AstType::atEq: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; - case AstType::atNeq: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; - case AstType::atEqCase: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; - case AstType::atNeqCase: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; - case AstType::atEqWild: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; - case AstType::atNeqWild: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; - case AstType::atAdd: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; - case AstType::atSub: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; - case AstType::atShiftL: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atEq: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atNeq: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atEqCase: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atNeqCase: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atEqWild: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atNeqWild: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atAdd: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atSub: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; + case VNType::atShiftL: nodep->dtypeChgSigned(signedFlavorNeeded); return nullptr; default: break; } FileLine* const fl = nodep->fileline(); @@ -5620,22 +5821,22 @@ private: AstNode* const rhsp = nodep->rhsp()->unlinkFrBack(); AstNodeBiop* newp = nullptr; switch (nodep->type()) { - case AstType::atGt: newp = new AstGtS(fl, lhsp, rhsp); break; - case AstType::atGtS: newp = new AstGt(fl, lhsp, rhsp); break; - case AstType::atGte: newp = new AstGteS(fl, lhsp, rhsp); break; - case AstType::atGteS: newp = new AstGte(fl, lhsp, rhsp); break; - case AstType::atLt: newp = new AstLtS(fl, lhsp, rhsp); break; - case AstType::atLtS: newp = new AstLt(fl, lhsp, rhsp); break; - case AstType::atLte: newp = new AstLteS(fl, lhsp, rhsp); break; - case AstType::atLteS: newp = new AstLte(fl, lhsp, rhsp); break; - case AstType::atDiv: newp = new AstDivS(fl, lhsp, rhsp); break; - case AstType::atDivS: newp = new AstDiv(fl, lhsp, rhsp); break; - case AstType::atModDiv: newp = new AstModDivS(fl, lhsp, rhsp); break; - case AstType::atModDivS: newp = new AstModDiv(fl, lhsp, rhsp); break; - case AstType::atMul: newp = new AstMulS(fl, lhsp, rhsp); break; - case AstType::atMulS: newp = new AstMul(fl, lhsp, rhsp); break; - case AstType::atShiftR: newp = new AstShiftRS(fl, lhsp, rhsp); break; - case AstType::atShiftRS: newp = new AstShiftR(fl, lhsp, rhsp); break; + case VNType::atGt: newp = new AstGtS(fl, lhsp, rhsp); break; + case VNType::atGtS: newp = new AstGt(fl, lhsp, rhsp); break; + case VNType::atGte: newp = new AstGteS(fl, lhsp, rhsp); break; + case VNType::atGteS: newp = new AstGte(fl, lhsp, rhsp); break; + case VNType::atLt: newp = new AstLtS(fl, lhsp, rhsp); break; + case VNType::atLtS: newp = new AstLt(fl, lhsp, rhsp); break; + case VNType::atLte: newp = new AstLteS(fl, lhsp, rhsp); break; + case VNType::atLteS: newp = new AstLte(fl, lhsp, rhsp); break; + case VNType::atDiv: newp = new AstDivS(fl, lhsp, rhsp); break; + case VNType::atDivS: newp = new AstDiv(fl, lhsp, rhsp); break; + case VNType::atModDiv: newp = new AstModDivS(fl, lhsp, rhsp); break; + case VNType::atModDivS: newp = new AstModDiv(fl, lhsp, rhsp); break; + case VNType::atMul: newp = new AstMulS(fl, lhsp, rhsp); break; + case VNType::atMulS: newp = new AstMul(fl, lhsp, rhsp); break; + case VNType::atShiftR: newp = new AstShiftRS(fl, lhsp, rhsp); break; + case VNType::atShiftRS: newp = new AstShiftR(fl, lhsp, rhsp); break; default: // LCOV_EXCL_LINE nodep->v3fatalSrc("Node needs sign change, but bad case: " << nodep); break; @@ -5656,25 +5857,25 @@ private: AstNodeBiop* newp = nullptr; // No width change on output;... // All below have bool or double outputs switch (nodep->type()) { - case AstType::atAdd: newp = new AstAddD(fl, lhsp, rhsp); break; - case AstType::atSub: newp = new AstSubD(fl, lhsp, rhsp); break; - case AstType::atPow: newp = new AstPowD(fl, lhsp, rhsp); break; - case AstType::atEq: - case AstType::atEqCase: newp = new AstEqD(fl, lhsp, rhsp); break; - case AstType::atNeq: - case AstType::atNeqCase: newp = new AstNeqD(fl, lhsp, rhsp); break; - case AstType::atGt: - case AstType::atGtS: newp = new AstGtD(fl, lhsp, rhsp); break; - case AstType::atGte: - case AstType::atGteS: newp = new AstGteD(fl, lhsp, rhsp); break; - case AstType::atLt: - case AstType::atLtS: newp = new AstLtD(fl, lhsp, rhsp); break; - case AstType::atLte: - case AstType::atLteS: newp = new AstLteD(fl, lhsp, rhsp); break; - case AstType::atDiv: - case AstType::atDivS: newp = new AstDivD(fl, lhsp, rhsp); break; - case AstType::atMul: - case AstType::atMulS: newp = new AstMulD(fl, lhsp, rhsp); break; + case VNType::atAdd: newp = new AstAddD(fl, lhsp, rhsp); break; + case VNType::atSub: newp = new AstSubD(fl, lhsp, rhsp); break; + case VNType::atPow: newp = new AstPowD(fl, lhsp, rhsp); break; + case VNType::atEq: + case VNType::atEqCase: newp = new AstEqD(fl, lhsp, rhsp); break; + case VNType::atNeq: + case VNType::atNeqCase: newp = new AstNeqD(fl, lhsp, rhsp); break; + case VNType::atGt: + case VNType::atGtS: newp = new AstGtD(fl, lhsp, rhsp); break; + case VNType::atGte: + case VNType::atGteS: newp = new AstGteD(fl, lhsp, rhsp); break; + case VNType::atLt: + case VNType::atLtS: newp = new AstLtD(fl, lhsp, rhsp); break; + case VNType::atLte: + case VNType::atLteS: newp = new AstLteD(fl, lhsp, rhsp); break; + case VNType::atDiv: + case VNType::atDivS: newp = new AstDivD(fl, lhsp, rhsp); break; + case VNType::atMul: + case VNType::atMulS: newp = new AstMulD(fl, lhsp, rhsp); break; default: // LCOV_EXCL_LINE nodep->v3fatalSrc("Node needs conversion to double, but bad case: " << nodep); break; @@ -5695,18 +5896,18 @@ private: AstNodeBiop* newp = nullptr; // No width change on output;... // All below have bool or double outputs switch (nodep->type()) { - case AstType::atEq: - case AstType::atEqCase: newp = new AstEqN(fl, lhsp, rhsp); break; - case AstType::atNeq: - case AstType::atNeqCase: newp = new AstNeqN(fl, lhsp, rhsp); break; - case AstType::atGt: - case AstType::atGtS: newp = new AstGtN(fl, lhsp, rhsp); break; - case AstType::atGte: - case AstType::atGteS: newp = new AstGteN(fl, lhsp, rhsp); break; - case AstType::atLt: - case AstType::atLtS: newp = new AstLtN(fl, lhsp, rhsp); break; - case AstType::atLte: - case AstType::atLteS: newp = new AstLteN(fl, lhsp, rhsp); break; + case VNType::atEq: + case VNType::atEqCase: newp = new AstEqN(fl, lhsp, rhsp); break; + case VNType::atNeq: + case VNType::atNeqCase: newp = new AstNeqN(fl, lhsp, rhsp); break; + case VNType::atGt: + case VNType::atGtS: newp = new AstGtN(fl, lhsp, rhsp); break; + case VNType::atGte: + case VNType::atGteS: newp = new AstGteN(fl, lhsp, rhsp); break; + case VNType::atLt: + case VNType::atLtS: newp = new AstLtN(fl, lhsp, rhsp); break; + case VNType::atLte: + case VNType::atLteS: newp = new AstLteN(fl, lhsp, rhsp); break; default: // LCOV_EXCL_LINE nodep->v3fatalSrc("Node needs conversion to string, but bad case: " << nodep); break; @@ -5725,7 +5926,7 @@ private: AstNode* const lhsp = nodep->lhsp()->unlinkFrBack(); AstNodeUniop* newp = nullptr; switch (nodep->type()) { - case AstType::atNegate: newp = new AstNegateD(fl, lhsp); break; + case VNType::atNegate: newp = new AstNegateD(fl, lhsp); break; default: // LCOV_EXCL_LINE nodep->v3fatalSrc("Node needs conversion to double, but bad case: " << nodep); break; @@ -5802,7 +6003,7 @@ private: return dtnodep; } - AstConst* dimensionValue(FileLine* fileline, AstNodeDType* nodep, AstAttrType attrType, + AstConst* dimensionValue(FileLine* fileline, AstNodeDType* nodep, VAttrType attrType, int dim) { // Return the dimension value for the specified attribute and constant dimension AstNodeDType* dtypep = nodep->skipRefp(); @@ -5827,7 +6028,7 @@ private: AstConst* valp = nullptr; // If nullptr, construct from val int val = 0; switch (attrType) { - case AstAttrType::DIM_BITS: { + case VAttrType::DIM_BITS: { int bits = 1; while (dtypep) { // UINFO(9, " bits at "<v3fatalSrc("Missing DIM ATTR type case"); break; } if (!valp) valp = new AstConst(fileline, AstConst::Signed32(), val); @@ -5870,7 +6071,7 @@ private: << ")=" << valp << endl); return valp; } - AstVar* dimensionVarp(AstNodeDType* nodep, AstAttrType attrType, uint32_t msbdim) { + AstVar* dimensionVarp(AstNodeDType* nodep, VAttrType attrType, uint32_t msbdim) { // Return a variable table which has specified dimension properties for this variable const auto pos = m_tableMap.find(std::make_pair(nodep, attrType)); if (pos != m_tableMap.end()) return pos->second; @@ -5879,7 +6080,7 @@ private: new AstRange(nodep->fileline(), msbdim, 0)); AstInitArray* const initp = new AstInitArray(nodep->fileline(), vardtypep, nullptr); v3Global.rootp()->typeTablep()->addTypesp(vardtypep); - AstVar* const varp = new AstVar(nodep->fileline(), AstVarType::MODULETEMP, + AstVar* const varp = new AstVar(nodep->fileline(), VVarType::MODULETEMP, "__Vdimtab_" + VString::downcase(attrType.ascii()) + cvtToStr(m_dtTables++), vardtypep); @@ -5910,23 +6111,23 @@ private: UASSERT_OBJ(vconstp, errNodep, "Enum item without constified value"); if (vconstp->toUQuad() >= maxval) maxval = vconstp->toUQuad(); } - if (adtypep->itemsp()->width() > 64 || maxval >= (1 << 16)) { + if (adtypep->itemsp()->width() > 64) { errNodep->v3warn(E_UNSUPPORTED, - "Unsupported: enum next/prev method on enum with > 10 bits"); - return 0; + "Unsupported: enum next/prev/name method on enum with > 64 bits"); + return 64; } return maxval; } - AstVar* enumVarp(AstEnumDType* nodep, AstAttrType attrType, uint32_t msbdim) { + AstVar* enumVarp(AstEnumDType* nodep, VAttrType attrType, bool assoc, uint32_t msbdim) { // Return a variable table which has specified dimension properties for this variable const auto pos = m_tableMap.find(std::make_pair(nodep, attrType)); if (pos != m_tableMap.end()) return pos->second; - UINFO(9, "Construct Venumtab attr=" << attrType.ascii() << " max=" << msbdim << " for " - << nodep << endl); + UINFO(9, "Construct Venumtab attr=" << attrType.ascii() << " assoc=" << assoc + << " max=" << msbdim << " for " << nodep << endl); AstNodeDType* basep; - if (attrType == AstAttrType::ENUM_NAME) { + if (attrType == VAttrType::ENUM_NAME) { basep = nodep->findStringDType(); - } else if (attrType == AstAttrType::ENUM_VALID) { + } else if (attrType == VAttrType::ENUM_VALID) { // TODO in theory we could bit-pack the bits in the table, but // would require additional operations to extract, so only // would be worth it for larger tables which perhaps could be @@ -5935,11 +6136,16 @@ private: } else { basep = nodep->dtypep(); } - AstNodeArrayDType* const vardtypep = new AstUnpackArrayDType( - nodep->fileline(), basep, new AstRange(nodep->fileline(), msbdim, 0)); + AstNodeDType* vardtypep; + if (assoc) { + vardtypep = new AstAssocArrayDType{nodep->fileline(), basep, nodep}; + } else { + vardtypep = new AstUnpackArrayDType{nodep->fileline(), basep, + new AstRange(nodep->fileline(), msbdim, 0)}; + } AstInitArray* const initp = new AstInitArray(nodep->fileline(), vardtypep, nullptr); v3Global.rootp()->typeTablep()->addTypesp(vardtypep); - AstVar* const varp = new AstVar(nodep->fileline(), AstVarType::MODULETEMP, + AstVar* const varp = new AstVar(nodep->fileline(), VVarType::MODULETEMP, "__Venumtab_" + VString::downcase(attrType.ascii()) + cvtToStr(m_dtTables++), vardtypep); @@ -5950,11 +6156,11 @@ private: v3Global.rootp()->dollarUnitPkgAddp()->addStmtp(varp); // Default for all unspecified values - if (attrType == AstAttrType::ENUM_NAME) { + if (attrType == VAttrType::ENUM_NAME) { initp->defaultp(new AstConst(nodep->fileline(), AstConst::String(), "")); - } else if (attrType == AstAttrType::ENUM_NEXT || attrType == AstAttrType::ENUM_PREV) { + } else if (attrType == VAttrType::ENUM_NEXT || attrType == VAttrType::ENUM_PREV) { initp->defaultp(new AstConst(nodep->fileline(), V3Number(nodep, nodep->width(), 0))); - } else if (attrType == AstAttrType::ENUM_VALID) { + } else if (attrType == VAttrType::ENUM_VALID) { initp->defaultp(new AstConst{nodep->fileline(), AstConst::BitFalse{}}); } else { nodep->v3fatalSrc("Bad case"); @@ -5962,9 +6168,7 @@ private: // Find valid values and populate UASSERT_OBJ(nodep->itemsp(), nodep, "enum without items"); - std::vector values; - values.resize(msbdim + 1); - for (unsigned i = 0; i < (msbdim + 1); ++i) values[i] = nullptr; + std::map values; { AstEnumItem* const firstp = nodep->itemsp(); const AstEnumItem* prevp = firstp; // Prev must start with last item @@ -5973,14 +6177,14 @@ private: AstEnumItem* const nextp = VN_AS(itemp->nextp(), EnumItem); const AstConst* const vconstp = VN_AS(itemp->valuep(), Const); UASSERT_OBJ(vconstp, nodep, "Enum item without constified value"); - const uint32_t i = vconstp->toUInt(); - if (attrType == AstAttrType::ENUM_NAME) { + const vluint64_t i = vconstp->toUQuad(); + if (attrType == VAttrType::ENUM_NAME) { values[i] = new AstConst(nodep->fileline(), AstConst::String(), itemp->name()); - } else if (attrType == AstAttrType::ENUM_NEXT) { + } else if (attrType == VAttrType::ENUM_NEXT) { values[i] = (nextp ? nextp : firstp)->valuep()->cloneTree(false); // A const - } else if (attrType == AstAttrType::ENUM_PREV) { + } else if (attrType == VAttrType::ENUM_PREV) { values[i] = prevp->valuep()->cloneTree(false); // A const - } else if (attrType == AstAttrType::ENUM_VALID) { + } else if (attrType == VAttrType::ENUM_VALID) { values[i] = new AstConst(nodep->fileline(), AstConst::BitTrue{}); } else { nodep->v3fatalSrc("Bad case"); @@ -5990,8 +6194,12 @@ private: } } // Add all specified values to table - for (unsigned i = 0; i < (msbdim + 1); ++i) { - if (values[i]) initp->addIndexValuep(i, values[i]); + if (assoc) { + for (const auto& itr : values) initp->addIndexValuep(itr.first, itr.second); + } else { + for (vluint64_t i = 0; i < (msbdim + 1); ++i) { + if (values[i]) initp->addIndexValuep(i, values[i]); + } } userIterate(varp, nullptr); // May have already done $unit so must do this var m_tableMap.emplace(std::make_pair(nodep, attrType), varp); @@ -6091,11 +6299,22 @@ private: const bool fromNumericable = VN_IS(fromBaseDtp, BasicDType) || VN_IS(fromBaseDtp, EnumDType) || VN_IS(fromBaseDtp, NodeUOrStructDType); + + const AstNodeDType* toBaseDtp = toDtp; + while (const AstPackArrayDType* const packp = VN_CAST(toBaseDtp, PackArrayDType)) { + toBaseDtp = packp->subDTypep(); + while (const AstRefDType* const refp = VN_CAST(toBaseDtp, RefDType)) { + toBaseDtp = refp->refDTypep(); + } + } + const bool toNumericable + = VN_IS(toBaseDtp, BasicDType) || VN_IS(toBaseDtp, NodeUOrStructDType); // UNSUP unpacked struct/unions (treated like BasicDType) - if (VN_IS(toDtp, BasicDType) || VN_IS(toDtp, NodeUOrStructDType)) { + if (toNumericable) { if (fromNumericable) return COMPATIBLE; } else if (VN_IS(toDtp, EnumDType)) { - if (fromNumericable) return DYNAMIC_ENUM; + if (VN_IS(fromBaseDtp, EnumDType) && toDtp->sameTree(fromDtp)) return ENUM_IMPLICIT; + if (fromNumericable) return ENUM_EXPLICIT; } else if (VN_IS(toDtp, ClassRefDType) && VN_IS(fromConstp, Const)) { if (VN_IS(fromConstp, Const) && VN_AS(fromConstp, Const)->num().isNull()) return COMPATIBLE; @@ -6132,6 +6351,11 @@ private: VL_DO_DANGLING(pushDeletep(nodep), nodep); } } + AstNode* newVarRefDollarUnit(AstVar* nodep) { + AstVarRef* const varrefp = new AstVarRef{nodep->fileline(), nodep, VAccess::READ}; + varrefp->classOrPackagep(v3Global.rootp()->dollarUnitPkgAddp()); + return varrefp; + } AstNode* nodeForUnsizedWarning(AstNode* nodep) { // Return a nodep to use for unsized warnings, reporting on child if can if (nodep->op1p() && nodep->op1p()->dtypep() && !nodep->op1p()->dtypep()->widthSized()) { diff --git a/src/V3Width.h b/src/V3Width.h index 6b7f1d5ca..2d6cfb9d7 100644 --- a/src/V3Width.h +++ b/src/V3Width.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,8 +20,8 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3Error.h" -#include "V3Ast.h" +class AstNetlist; +class AstNode; //============================================================================ diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h index eb7ba7409..606c1cf41 100644 --- a/src/V3WidthCommit.h +++ b/src/V3WidthCommit.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,7 +34,7 @@ /// Remove all $signed, $unsigned, we're done with them. /// This step is only called on real V3Width, not intermediate e.g. widthParams -class WidthRemoveVisitor final : public AstNVisitor { +class WidthRemoveVisitor final : public VNVisitor { private: // METHODS void replaceWithSignedVersion(AstNode* nodep, AstNode* newp) { @@ -64,10 +64,10 @@ public: // Now that all widthing is complete, // Copy all width() to widthMin(). V3Const expects this -class WidthCommitVisitor final : public AstNVisitor { +class WidthCommitVisitor final : public VNVisitor { // NODE STATE // AstVar::user1p -> bool, processed - const AstUser1InUse m_inuser1; + const VNUser1InUse m_inuser1; // STATE AstNodeModule* m_modp = nullptr; diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index e1f1c9427..a437c472d 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,12 +31,13 @@ #include "V3Global.h" #include "V3Width.h" +#include "V3Ast.h" #include "V3Const.h" //###################################################################### // Width state, as a visitor of each AstNode -class WidthSelVisitor final : public AstNVisitor { +class WidthSelVisitor final : public VNVisitor { private: // IMPORTANT //**** This is not a normal visitor, in that all iteration is instead diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 2d20c24c5..7ba0c113a 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -51,6 +51,7 @@ #include "V3EmitXml.h" #include "V3Expand.h" #include "V3File.h" +#include "V3Force.h" #include "V3Gate.h" #include "V3GenClk.h" #include "V3Graph.h" @@ -110,7 +111,6 @@ static void reportStatsIfEnabled() { V3Stats::statsFinalAll(v3Global.rootp()); V3Stats::statsReport(); } - if (v3Global.opt.debugEmitV()) V3EmitV::debugEmitV("final"); } static void process() { @@ -245,7 +245,7 @@ static void process() { } } - //--PRE-FLAT OPTIMIZATIONS------------------ + // --PRE-FLAT OPTIMIZATIONS------------------ // Initial const/dead to reduce work for ordering code V3Const::constifyAll(v3Global.rootp()); @@ -256,7 +256,7 @@ static void process() { V3Error::abortIfErrors(); - //--FLATTENING--------------- + // --FLATTENING--------------- if (!(v3Global.opt.xmlOnly() && !v3Global.opt.flatten())) { // We're going to flatten the hierarchy, so as many optimizations that @@ -276,7 +276,7 @@ static void process() { V3Class::classAll(v3Global.rootp()); } - //--SCOPE BASED OPTIMIZATIONS-------------- + // --SCOPE BASED OPTIMIZATIONS-------------- if (!(v3Global.opt.xmlOnly() && !v3Global.opt.flatten())) { // Cleanup @@ -334,6 +334,10 @@ static void process() { // Create tracing sample points, before we start eliminating signals if (v3Global.opt.trace()) V3TraceDecl::traceDeclAll(v3Global.rootp()); + // Convert forceable signals, process force/release statements. + // After V3TraceDecl so we don't trace additional signals inserted to implement forcing. + V3Force::forceAll(v3Global.rootp()); + // Gate-based logic elimination; eliminate signals and push constant across cell boundaries // Instant propagation makes lots-o-constant reduction possibilities. if (v3Global.opt.oGate()) { @@ -371,7 +375,6 @@ static void process() { V3ActiveTop::activeTopAll(v3Global.rootp()); if (v3Global.opt.stats()) V3Stats::statsStageAll(v3Global.rootp(), "PreOrder"); - if (v3Global.opt.debugEmitV()) V3EmitV::debugEmitV("preorder"); // Order the code; form SBLOCKs and BLOCKCALLs V3Order::orderAll(v3Global.rootp()); @@ -407,7 +410,7 @@ static void process() { if (v3Global.opt.stats()) V3Stats::statsStageAll(v3Global.rootp(), "Scoped"); } - //--MODULE OPTIMIZATIONS-------------- + // --MODULE OPTIMIZATIONS-------------- if (!v3Global.opt.xmlOnly()) { // Split deep blocks to appease MSVC++. Must be before Localize. @@ -430,7 +433,7 @@ static void process() { V3Error::abortIfErrors(); - //--GENERATION------------------ + // --GENERATION------------------ if (!v3Global.opt.xmlOnly()) { // Remove unused vars @@ -542,6 +545,8 @@ static void process() { V3EmitC::emitcFiles(); } + if (v3Global.opt.stats()) V3Stats::statsStage("emit"); + // Statistics reportStatsIfEnabled(); @@ -573,7 +578,7 @@ static void verilate(const string& argString) { v3fatalSrc("VERILATOR_DEBUG_SKIP_IDENTICAL w/ --skip-identical: Changes found\n"); } // LCOV_EXCL_STOP - //--FRONTEND------------------ + // --FRONTEND------------------ // Cleanup V3Os::unlinkRegexp(v3Global.opt.hierTopDataDir(), v3Global.opt.prefix() + "_*.tree"); @@ -582,7 +587,7 @@ static void verilate(const string& argString) { // Internal tests (after option parsing as need debug() setting, // and after removing files as may make debug output) - AstBasicDTypeKwd::selfTest(); + VBasicDTypeKwd::selfTest(); if (v3Global.opt.debugSelfTest()) { VHashSha256::selfTest(); VSpellCheck::selfTest(); diff --git a/src/VlcBucket.h b/src/VlcBucket.h index efaf1413a..5bc39d946 100644 --- a/src/VlcBucket.h +++ b/src/VlcBucket.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,6 +20,9 @@ #include "config_build.h" #include "verilatedos.h" +#define V3ERROR_NO_GLOBAL_ +#include "V3Error.h" + //******************************************************************** // VlcBuckets - Container of all coverage point hits for a given test // This is a bitmap array - we store a single bit to indicate a test diff --git a/src/VlcMain.cpp b/src/VlcMain.cpp index f8c57d7c8..f4f6717ca 100644 --- a/src/VlcMain.cpp +++ b/src/VlcMain.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -98,7 +98,7 @@ void VlcOptions::showVersion(bool verbose) { if (!verbose) return; cout << endl; - cout << "Copyright 2003-2021 by Wilson Snyder. Verilator is free software; you can\n"; + cout << "Copyright 2003-2022 by Wilson Snyder. Verilator is free software; you can\n"; cout << "redistribute it and/or modify the Verilator internals under the terms of\n"; cout << "either the GNU Lesser General Public License Version 3 or the Perl Artistic\n"; cout << "License Version 2.0.\n"; diff --git a/src/VlcOptions.h b/src/VlcOptions.h index 6bebf0902..6f4bd3a0f 100644 --- a/src/VlcOptions.h +++ b/src/VlcOptions.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/VlcPoint.h b/src/VlcPoint.h index c9ea193bb..4b8e761ea 100644 --- a/src/VlcPoint.h +++ b/src/VlcPoint.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -20,12 +20,15 @@ #include "config_build.h" #include "verilatedos.h" -#include "verilated_cov_key.h" - #include #include +#include #include +#define V3ERROR_NO_GLOBAL_ +#include "V3Error.h" +#include "verilated_cov_key.h" + //******************************************************************** // VlcPoint - A coverage point (across all tests) diff --git a/src/VlcSource.h b/src/VlcSource.h index c8de073a1..f8dece1a8 100644 --- a/src/VlcSource.h +++ b/src/VlcSource.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -21,6 +21,7 @@ #include "verilatedos.h" #include +#include #include //******************************************************************** diff --git a/src/VlcTest.h b/src/VlcTest.h index cf354d6aa..1596bcb66 100644 --- a/src/VlcTest.h +++ b/src/VlcTest.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp index a36b50d7a..1d57c23ce 100644 --- a/src/VlcTop.cpp +++ b/src/VlcTop.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -21,6 +21,8 @@ #include #include +#include +#include //###################################################################### diff --git a/src/VlcTop.h b/src/VlcTop.h index 106191b1a..2d9ccc39c 100644 --- a/src/VlcTop.h +++ b/src/VlcTop.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/astgen b/src/astgen index 7fe3d9fdd..f27c3b7d2 100755 --- a/src/astgen +++ b/src/astgen @@ -366,8 +366,6 @@ def read_types(filename): supern = match.group(1) if match else "" assert classn != "AstNode" or supern == "", "AstNode can't have a superclass" if re.search(r'Ast', supern) or classn == "AstNode": - if supern == "AstNDeleter": - continue classn = re.sub(r'^Ast', '', classn) supern = re.sub(r'^Ast', '', supern) Classes[classn] = supern @@ -384,7 +382,7 @@ def read_stages(filename): line = re.sub(r'//.*$', '', line) if re.match(r'^\s*$', line): continue - match = re.match(r'^\s*([A-Za-z0-9]+)::', line) + match = re.search(r'\s([A-Za-z0-9]+)::', line) if match: stage = match.group(1) + ".cpp" if stage not in Stages: @@ -407,6 +405,12 @@ def read_refs(filename): if ref not in ClassRefs: ClassRefs[ref] = {'newed': {}, 'used': {}} ClassRefs[ref]['used'][basename] = 1 + for match in re.finditer( + r'(VN_IS|VN_AS|VN_CAST)\([^.]+, ([A-Za-z0-9_]+)', line): + ref = "Ast" + match.group(2) + if ref not in ClassRefs: + ClassRefs[ref] = {'newed': {}, 'used': {}} + ClassRefs[ref]['used'][basename] = 1 def open_file(filename): @@ -527,13 +531,13 @@ def write_impl(filename): fh.write("return ") if re.search(r'^Node', typen): fh.write( - "static_cast(nodep->type()) >= static_cast(AstType::first" + "static_cast(nodep->type()) >= static_cast(VNType::first" + typen + ") && ") fh.write( - "static_cast(nodep->type()) <= static_cast(AstType::last" + "static_cast(nodep->type()) <= static_cast(VNType::last" + typen + "); ") else: - fh.write("nodep->type() == AstType::at" + typen + "; ") + fh.write("nodep->type() == VNType::at" + typen + "; ") fh.write("}\n") @@ -621,7 +625,7 @@ def write_macros(filename): typen = match.group(1) base = match.group(4) if not typen.startswith("Node"): - macro = "#define ASTGEN_SUPER_{t}(...) {b}(AstType::at{t}, __VA_ARGS__)\n" \ + macro = "#define ASTGEN_SUPER_{t}(...) {b}(VNType::at{t}, __VA_ARGS__)\n" \ .format(b=base, t=typen) fh.write(macro) @@ -644,7 +648,7 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""Generate V3Ast headers to reduce C++ code duplication.""", epilog= - """Copyright 2002-2021 by Wilson Snyder. This program is free software; you + """Copyright 2002-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/bisonpre b/src/bisonpre index 3038f2a06..efebd9744 100755 --- a/src/bisonpre +++ b/src/bisonpre @@ -501,7 +501,7 @@ BISON GRAMMAR EXTENSIONS If the bison version is >= the specified version, include the given command. -Copyright 2002-2021 by Wilson Snyder. This program is free software; you +Copyright 2002-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/config_build.h.in b/src/config_build.h.in index a6808d09b..d044c1411 100644 --- a/src/config_build.h.in +++ b/src/config_build.h.in @@ -8,7 +8,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/config_rev b/src/config_rev index 50c477e55..754ab29d2 100755 --- a/src/config_rev +++ b/src/config_rev @@ -2,7 +2,7 @@ # pylint: disable=C0103,C0114 ###################################################################### # -# Copyright 2005-2021 by Wilson Snyder. This program is free software; you +# Copyright 2005-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/src/cppcheck_filtered b/src/cppcheck_filtered index c1011c00b..7e803b306 100755 --- a/src/cppcheck_filtered +++ b/src/cppcheck_filtered @@ -165,7 +165,7 @@ filters out unnecessary warnings related to Verilator. Run as: cd $VERILATOR_ROOT make -k cppcheck""", epilog= - """Copyright 2014-2021 by Wilson Snyder. This program is free software; you + """Copyright 2014-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/flexfix b/src/flexfix index 476907fb1..9ade34b8f 100755 --- a/src/flexfix +++ b/src/flexfix @@ -2,7 +2,7 @@ # pylint: disable=C0114,C0301 ###################################################################### # -# Copyright 2002-2021 by Wilson Snyder. This program is free software; you +# Copyright 2002-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/src/verilog.l b/src/verilog.l index 31cf6481f..588da6073 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -6,7 +6,7 @@ * ************************************************************************** * - * Copyright 2003-2021 by Wilson Snyder. Verilator is free software; you + * Copyright 2003-2022 by Wilson Snyder. Verilator is free software; you * can redistribute it and/or modify it under the terms of either the * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. @@ -112,6 +112,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "coverage_block_off" { FL; return yVLT_COVERAGE_BLOCK_OFF; } "coverage_off" { FL; return yVLT_COVERAGE_OFF; } "coverage_on" { FL; return yVLT_COVERAGE_ON; } + "forceable" { FL; return yVLT_FORCEABLE; } "full_case" { FL; return yVLT_FULL_CASE; } "hier_block" { FL; return yVLT_HIER_BLOCK; } "inline" { FL; return yVLT_INLINE; } @@ -141,7 +142,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} -?"-match" { FL; return yVLT_D_MATCH; } -?"-model" { FL; return yVLT_D_MODEL; } -?"-module" { FL; return yVLT_D_MODULE; } - -?"-msg" { FL; return yVLT_D_MSG; } -?"-mtask" { FL; return yVLT_D_MTASK; } -?"-rule" { FL; return yVLT_D_RULE; } -?"-task" { FL; return yVLT_D_TASK; } @@ -722,6 +722,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; } "/*verilator coverage_off*/" { FL_FWD; PARSEP->lexFileline()->coverageOn(false); FL_BRK; } "/*verilator coverage_on*/" { FL_FWD; PARSEP->lexFileline()->coverageOn(true); FL_BRK; } + "/*verilator forceable*/" { FL; return yVL_FORCEABLE; } "/*verilator full_case*/" { FL; return yVL_FULL_CASE; } "/*verilator hier_block*/" { FL; return yVL_HIER_BLOCK; } "/*verilator inline_module*/" { FL; return yVL_INLINE_MODULE; } diff --git a/src/verilog.y b/src/verilog.y index 2238e184a..c5bac151a 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2021 by Wilson Snyder. This program is free software; you +// Copyright 2003-2022 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -51,7 +51,7 @@ class V3ParseGrammar { public: bool m_impliedDecl = false; // Allow implied wire declarations - AstVarType m_varDecl; // Type for next signal declaration (reg/wire/etc) + VVarType m_varDecl; // Type for next signal declaration (reg/wire/etc) bool m_varDeclTyped = false; // Var got reg/wire for dedup check VDirection m_varIO; // Direction for next signal declaration (reg/wire/etc) VLifetime m_varLifetime; // Static/Automatic for next signal @@ -74,7 +74,7 @@ public: // CONSTRUCTORS V3ParseGrammar() { - m_varDecl = AstVarType::UNKNOWN; + m_varDecl = VVarType::UNKNOWN; m_varIO = VDirection::NONE; } static V3ParseGrammar* singletonp() { @@ -97,8 +97,7 @@ public: return new AstText(fileline, newtext); } AstDisplay* createDisplayError(FileLine* fileline) { - AstDisplay* nodep - = new AstDisplay(fileline, AstDisplayType::DT_ERROR, "", nullptr, nullptr); + AstDisplay* nodep = new AstDisplay(fileline, VDisplayType::DT_ERROR, "", nullptr, nullptr); nodep->addNext(new AstStop(fileline, true)); return nodep; } @@ -134,7 +133,7 @@ public: << name << "'"); } } - void setVarDecl(AstVarType type) { m_varDecl = type; } + void setVarDecl(VVarType type) { m_varDecl = type; } void setDType(AstNodeDType* dtypep) { if (m_varDTypep) VL_DO_CLEAR(m_varDTypep->deleteTree(), m_varDTypep = nullptr); m_varDTypep = dtypep; @@ -170,7 +169,7 @@ public: if (dtypep->implicit()) { // It's no longer implicit but a wire logic type AstBasicDType* const newp = new AstBasicDType{ - dtypep->fileline(), AstBasicDTypeKwd::LOGIC, dtypep->numeric(), + dtypep->fileline(), VBasicDTypeKwd::LOGIC, dtypep->numeric(), dtypep->width(), dtypep->widthMin()}; VL_DO_DANGLING(dtypep->deleteTree(), dtypep); dtypep = newp; @@ -189,8 +188,8 @@ public: } }; -const AstBasicDTypeKwd LOGIC = AstBasicDTypeKwd::LOGIC; // Shorthand "LOGIC" -const AstBasicDTypeKwd LOGIC_IMPLICIT = AstBasicDTypeKwd::LOGIC_IMPLICIT; +const VBasicDTypeKwd LOGIC = VBasicDTypeKwd::LOGIC; // Shorthand "LOGIC" +const VBasicDTypeKwd LOGIC_IMPLICIT = VBasicDTypeKwd::LOGIC_IMPLICIT; int V3ParseGrammar::s_modTypeImpNum = 0; @@ -224,7 +223,7 @@ int V3ParseGrammar::s_modTypeImpNum = 0; GRAMMARP->m_varDeclTyped = false; \ } #define VARDECL(type) \ - { GRAMMARP->setVarDecl(AstVarType::type); } + { GRAMMARP->setVarDecl(VVarType::type); } #define VARIO(type) \ { GRAMMARP->m_varIO = VDirection::type; } #define VARLIFE(flag) \ @@ -341,6 +340,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yVLT_COVERAGE_BLOCK_OFF "coverage_block_off" %token yVLT_COVERAGE_OFF "coverage_off" %token yVLT_COVERAGE_ON "coverage_on" +%token yVLT_FORCEABLE "forceable" %token yVLT_FULL_CASE "full_case" %token yVLT_HIER_BLOCK "hier_block" %token yVLT_INLINE "inline" @@ -370,7 +370,6 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yVLT_D_MATCH "--match" %token yVLT_D_MODEL "--model" %token yVLT_D_MODULE "--module" -%token yVLT_D_MSG "--msg" %token yVLT_D_MTASK "--mtask" %token yVLT_D_RULE "--rule" %token yVLT_D_TASK "--task" @@ -812,6 +811,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yVL_CLOCKER "/*verilator clocker*/" %token yVL_CLOCK_ENABLE "/*verilator clock_enable*/" %token yVL_COVERAGE_BLOCK_OFF "/*verilator coverage_block_off*/" +%token yVL_FORCEABLE "/*verilator forceable*/" %token yVL_FULL_CASE "/*verilator full_case*/" %token yVL_HIER_BLOCK "/*verilator hier_block*/" %token yVL_INLINE_MODULE "/*verilator inline_module*/" @@ -1205,7 +1205,7 @@ udpFront: { $$ = new AstPrimitive($3, *$3); $$->inLibrary(true); $$->lifetime($2); $$->modTrace(false); - $$->addStmtp(new AstPragma($3, AstPragmaType::INLINE_MODULE)); + $$->addStmtp(new AstPragma($3, VPragmaType::INLINE_MODULE)); GRAMMARP->m_tracingParse = false; PARSEP->rootp()->addModulep($$); SYMP->pushNew($$); } @@ -1281,7 +1281,7 @@ portAndTagE: { int p = PINNUMINC(); const string name = "__pinNumber" + cvtToStr(p); $$ = new AstPort{CRELINE(), p, name}; - AstVar* varp = new AstVar{CRELINE(), AstVarType::PORT, name, VFlagChildDType{}, + AstVar* varp = new AstVar{CRELINE(), VVarType::PORT, name, VFlagChildDType{}, new AstBasicDType{CRELINE(), LOGIC_IMPLICIT}}; varp->declDirection(VDirection::INPUT); varp->direction(VDirection::INPUT); @@ -1624,7 +1624,7 @@ list_of_genvar_identifiers: // IEEE: list_of_genvar_identifiers (for decl genvar_identifierDecl: // IEEE: genvar_identifier (for declaration) id/*new-genvar_identifier*/ sigAttrListE { VARRESET_NONLIST(GENVAR); - VARDTYPE(new AstBasicDType($1, AstBasicDTypeKwd::INTEGER)); + VARDTYPE(new AstBasicDType($1, VBasicDTypeKwd::INTEGER)); $$ = VARDONEA($1, *$1, nullptr, $2); } ; @@ -1779,24 +1779,24 @@ tf_port_declaration: // ==IEEE: tf_port_declaration ; integer_atom_type: // ==IEEE: integer_atom_type - yBYTE { $$ = new AstBasicDType($1,AstBasicDTypeKwd::BYTE); } - | ySHORTINT { $$ = new AstBasicDType($1,AstBasicDTypeKwd::SHORTINT); } - | yINT { $$ = new AstBasicDType($1,AstBasicDTypeKwd::INT); } - | yLONGINT { $$ = new AstBasicDType($1,AstBasicDTypeKwd::LONGINT); } - | yINTEGER { $$ = new AstBasicDType($1,AstBasicDTypeKwd::INTEGER); } - | yTIME { $$ = new AstBasicDType($1,AstBasicDTypeKwd::TIME); } + yBYTE { $$ = new AstBasicDType($1,VBasicDTypeKwd::BYTE); } + | ySHORTINT { $$ = new AstBasicDType($1,VBasicDTypeKwd::SHORTINT); } + | yINT { $$ = new AstBasicDType($1,VBasicDTypeKwd::INT); } + | yLONGINT { $$ = new AstBasicDType($1,VBasicDTypeKwd::LONGINT); } + | yINTEGER { $$ = new AstBasicDType($1,VBasicDTypeKwd::INTEGER); } + | yTIME { $$ = new AstBasicDType($1,VBasicDTypeKwd::TIME); } ; integer_vector_type: // ==IEEE: integer_atom_type - yBIT { $$ = new AstBasicDType($1,AstBasicDTypeKwd::BIT); } - | yLOGIC { $$ = new AstBasicDType($1,AstBasicDTypeKwd::LOGIC); } - | yREG { $$ = new AstBasicDType($1,AstBasicDTypeKwd::LOGIC); } // logic==reg + yBIT { $$ = new AstBasicDType($1,VBasicDTypeKwd::BIT); } + | yLOGIC { $$ = new AstBasicDType($1,VBasicDTypeKwd::LOGIC); } + | yREG { $$ = new AstBasicDType($1,VBasicDTypeKwd::LOGIC); } // logic==reg ; non_integer_type: // ==IEEE: non_integer_type - yREAL { $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); } - | yREALTIME { $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); } - | ySHORTREAL { $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); UNSUPREAL($1); } + yREAL { $$ = new AstBasicDType($1,VBasicDTypeKwd::DOUBLE); } + | yREALTIME { $$ = new AstBasicDType($1,VBasicDTypeKwd::DOUBLE); } + | ySHORTREAL { $$ = new AstBasicDType($1,VBasicDTypeKwd::DOUBLE); UNSUPREAL($1); } ; signingE: // IEEE: signing - plus empty @@ -1859,19 +1859,19 @@ data_typeNoRef: // ==IEEE: data_type, excluding class_type etc refe SYMP,VFlagChildDType(),$1),$2,true); } | enumDecl { $$ = new AstDefImplicitDType($1->fileline(),"__typeimpenum"+cvtToStr(GRAMMARP->s_modTypeImpNum++), SYMP,VFlagChildDType(),$1); } - | ySTRING { $$ = new AstBasicDType($1,AstBasicDTypeKwd::STRING); } - | yCHANDLE { $$ = new AstBasicDType($1,AstBasicDTypeKwd::CHANDLE); } - | yEVENT { $$ = new AstBasicDType($1,AstBasicDTypeKwd::EVENTVALUE); } + | ySTRING { $$ = new AstBasicDType($1,VBasicDTypeKwd::STRING); } + | yCHANDLE { $$ = new AstBasicDType($1,VBasicDTypeKwd::CHANDLE); } + | yEVENT { $$ = new AstBasicDType($1,VBasicDTypeKwd::EVENTVALUE); } // // Rules overlap virtual_interface_declaration // // Parameters here are SV2009 // // IEEE has ['.' modport] but that will conflict with port // // declarations which decode '.' modport themselves, so // // instead see data_typeVar | yVIRTUAL__INTERFACE yINTERFACE id/*interface*/ - { $$ = new AstBasicDType{$1, AstBasicDTypeKwd::CHANDLE}; + { $$ = new AstBasicDType{$1, VBasicDTypeKwd::CHANDLE}; BBUNSUP($1, "Unsupported: virtual interface"); } | yVIRTUAL__anyID id/*interface*/ - { $$ = new AstBasicDType{$1, AstBasicDTypeKwd::CHANDLE}; + { $$ = new AstBasicDType{$1, VBasicDTypeKwd::CHANDLE}; BBUNSUP($1, "Unsupported: virtual data type"); } | type_reference { $$ = $1; } // // IEEE: class_scope: see data_type above @@ -2050,7 +2050,7 @@ enumDecl: ; enum_base_typeE: // IEEE: enum_base_type - /* empty */ { $$ = new AstBasicDType(CRELINE(), AstBasicDTypeKwd::INT); } + /* empty */ { $$ = new AstBasicDType(CRELINE(), VBasicDTypeKwd::INT); } // // Not in spec, but obviously "enum [1:0]" should work // // implicit_type expanded, without empty // // Note enum base types are always packed data types @@ -2256,7 +2256,7 @@ dtypeAttrList: ; dtypeAttr: - yVL_PUBLIC { $$ = new AstAttrOf($1,AstAttrType::DT_PUBLIC); } + yVL_PUBLIC { $$ = new AstAttrOf($1,VAttrType::DT_PUBLIC); } ; vlTag: // verilator tag handling @@ -2294,16 +2294,16 @@ non_port_module_item: // ==IEEE: non_port_module_item { $$ = nullptr; BBUNSUP(CRELINE(), "Unsupported: interface decls within module decls"); } | timeunits_declaration { $$ = $1; } // // Verilator specific - | yaSCHDR { $$ = new AstScHdr($1,*$1); } - | yaSCINT { $$ = new AstScInt($1,*$1); } - | yaSCIMP { $$ = new AstScImp($1,*$1); } - | yaSCIMPH { $$ = new AstScImpHdr($1,*$1); } - | yaSCCTOR { $$ = new AstScCtor($1,*$1); } - | yaSCDTOR { $$ = new AstScDtor($1,*$1); } - | yVL_HIER_BLOCK { $$ = new AstPragma($1,AstPragmaType::HIER_BLOCK); } - | yVL_INLINE_MODULE { $$ = new AstPragma($1,AstPragmaType::INLINE_MODULE); } - | yVL_NO_INLINE_MODULE { $$ = new AstPragma($1,AstPragmaType::NO_INLINE_MODULE); } - | yVL_PUBLIC_MODULE { $$ = new AstPragma($1,AstPragmaType::PUBLIC_MODULE); v3Global.dpi(true); } + | yaSCHDR { $$ = new AstScHdr($1,*$1); v3Global.setHasSCTextSections(); } + | yaSCINT { $$ = new AstScInt($1,*$1); v3Global.setHasSCTextSections(); } + | yaSCIMP { $$ = new AstScImp($1,*$1); v3Global.setHasSCTextSections(); } + | yaSCIMPH { $$ = new AstScImpHdr($1,*$1); v3Global.setHasSCTextSections(); } + | yaSCCTOR { $$ = new AstScCtor($1,*$1); v3Global.setHasSCTextSections(); } + | yaSCDTOR { $$ = new AstScDtor($1,*$1); v3Global.setHasSCTextSections(); } + | yVL_HIER_BLOCK { $$ = new AstPragma($1,VPragmaType::HIER_BLOCK); } + | yVL_INLINE_MODULE { $$ = new AstPragma($1,VPragmaType::INLINE_MODULE); } + | yVL_NO_INLINE_MODULE { $$ = new AstPragma($1,VPragmaType::NO_INLINE_MODULE); } + | yVL_PUBLIC_MODULE { $$ = new AstPragma($1,VPragmaType::PUBLIC_MODULE); v3Global.dpi(true); } ; module_or_generate_item: // ==IEEE: module_or_generate_item @@ -2647,19 +2647,20 @@ sigAttrList: ; sigAttr: - yVL_CLOCKER { $$ = new AstAttrOf($1,AstAttrType::VAR_CLOCKER); } - | yVL_NO_CLOCKER { $$ = new AstAttrOf($1,AstAttrType::VAR_NO_CLOCKER); } - | yVL_CLOCK_ENABLE { $$ = new AstAttrOf($1,AstAttrType::VAR_CLOCK_ENABLE); } - | yVL_PUBLIC { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC); v3Global.dpi(true); } - | yVL_PUBLIC_FLAT { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT); v3Global.dpi(true); } - | yVL_PUBLIC_FLAT_RD { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RD); v3Global.dpi(true); } - | yVL_PUBLIC_FLAT_RW { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RW); v3Global.dpi(true); } - | yVL_PUBLIC_FLAT_RW attr_event_control { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RW); v3Global.dpi(true); + yVL_CLOCKER { $$ = new AstAttrOf($1,VAttrType::VAR_CLOCKER); } + | yVL_NO_CLOCKER { $$ = new AstAttrOf($1,VAttrType::VAR_NO_CLOCKER); } + | yVL_CLOCK_ENABLE { $$ = new AstAttrOf($1,VAttrType::VAR_CLOCK_ENABLE); } + | yVL_FORCEABLE { $$ = new AstAttrOf($1,VAttrType::VAR_FORCEABLE); } + | yVL_PUBLIC { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC); v3Global.dpi(true); } + | yVL_PUBLIC_FLAT { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT); v3Global.dpi(true); } + | yVL_PUBLIC_FLAT_RD { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT_RD); v3Global.dpi(true); } + | yVL_PUBLIC_FLAT_RW { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT_RW); v3Global.dpi(true); } + | yVL_PUBLIC_FLAT_RW attr_event_control { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT_RW); v3Global.dpi(true); $$ = $$->addNext(new AstAlwaysPublic($1,$2,nullptr)); } - | yVL_ISOLATE_ASSIGNMENTS { $$ = new AstAttrOf($1,AstAttrType::VAR_ISOLATE_ASSIGNMENTS); } - | yVL_SC_BV { $$ = new AstAttrOf($1,AstAttrType::VAR_SC_BV); } - | yVL_SFORMAT { $$ = new AstAttrOf($1,AstAttrType::VAR_SFORMAT); } - | yVL_SPLIT_VAR { $$ = new AstAttrOf($1,AstAttrType::VAR_SPLIT_VAR); } + | yVL_ISOLATE_ASSIGNMENTS { $$ = new AstAttrOf($1,VAttrType::VAR_ISOLATE_ASSIGNMENTS); } + | yVL_SC_BV { $$ = new AstAttrOf($1,VAttrType::VAR_SC_BV); } + | yVL_SFORMAT { $$ = new AstAttrOf($1,VAttrType::VAR_SFORMAT); } + | yVL_SPLIT_VAR { $$ = new AstAttrOf($1,VAttrType::VAR_SPLIT_VAR); } ; rangeListE: // IEEE: [{packed_dimension}] @@ -2772,7 +2773,7 @@ instDecl: } } // // IEEE: interface_identifier' .' modport_identifier list_of_interface_identifiers | id/*interface*/ '.' id/*modport*/ - /*mid*/ { VARRESET_NONLIST(AstVarType::IFACEREF); + /*mid*/ { VARRESET_NONLIST(VVarType::IFACEREF); VARDTYPE(new AstIfaceRefDType($1, $3, "", *$1, *$3)); } /*cont*/ mpInstnameList ';' { $$ = VARDONEP($5,nullptr,nullptr); } @@ -3089,10 +3090,10 @@ statement_item: // IEEE: statement_item //UNSUP: delay_or_event_controlE above | yDEASSIGN variable_lvalue ';' { $$ = nullptr; BBUNSUP($1, "Unsupported: Verilog 1995 deassign"); } - | yFORCE expr '=' expr ';' - { $$ = nullptr; BBUNSUP($1, "Unsupported: Verilog 1995 force"); } + | yFORCE variable_lvalue '=' expr ';' + { $$ = new AstAssignForce{$1, $2, $4}; v3Global.setHasForceableSignals(); } | yRELEASE variable_lvalue ';' - { $$ = nullptr; BBUNSUP($1, "Unsupported: Verilog 1995 release"); } + { $$ = new AstRelease{$1, $2}; v3Global.setHasForceableSignals(); } // // // IEEE: case_statement | unique_priorityE caseStart caseAttrE case_itemListE yENDCASE { $$ = $2; if ($4) $2->addItemsp($4); @@ -3233,7 +3234,7 @@ statementFor: // IEEE: part of statement ; statementVerilatorPragmas: - yVL_COVERAGE_BLOCK_OFF { $$ = new AstPragma($1,AstPragmaType::COVERAGE_BLOCK_OFF); } + yVL_COVERAGE_BLOCK_OFF { $$ = new AstPragma($1,VPragmaType::COVERAGE_BLOCK_OFF); } ; //UNSUPoperator_assignment: // IEEE: operator_assignment @@ -3522,8 +3523,9 @@ for_step_assignment: // ==IEEE: for_step_assignment ; loop_variables: // IEEE: loop_variables - varRefBase { $$ = $1; } - | loop_variables ',' varRefBase { $$ = $1; $1->addNext($3); } + parseRefBase { $$ = $1; } + | loop_variables ',' parseRefBase { $$ = $1; $$->addNext($3); } + | ',' parseRefBase { $$ = new AstEmpty{$1}; $$->addNext($2); } ; //************************************************ @@ -3618,7 +3620,7 @@ system_t_call: // IEEE: system_tf_call (as task) // | yD_EXIT parenE { $$ = new AstFinish($1); } // - | yD_FCLOSE '(' idClassSel ')' { $$ = new AstFClose($1, $3); } + | yD_FCLOSE '(' expr ')' { $$ = new AstFClose{$1, $3}; } | yD_FFLUSH parenE { $$ = new AstFFlush($1, nullptr); } | yD_FFLUSH '(' expr ')' { $$ = new AstFFlush($1, $3); } | yD_FINISH parenE { $$ = new AstFinish($1); } @@ -3632,59 +3634,59 @@ system_t_call: // IEEE: system_tf_call (as task) | yD_SWRITEH '(' expr ',' exprDispList ')' { $$ = new AstSFormat($1, $3, $5, 'h'); } | yD_SWRITEO '(' expr ',' exprDispList ')' { $$ = new AstSFormat($1, $3, $5, 'o'); } // - | yD_DISPLAY parenE { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, nullptr, nullptr); } - | yD_DISPLAY '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, nullptr, $3); } - | yD_DISPLAYB parenE { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, nullptr, nullptr, 'b'); } - | yD_DISPLAYB '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, nullptr, $3, 'b'); } - | yD_DISPLAYH parenE { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, nullptr, nullptr, 'h'); } - | yD_DISPLAYH '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, nullptr, $3, 'h'); } - | yD_DISPLAYO parenE { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, nullptr, nullptr, 'o'); } - | yD_DISPLAYO '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, nullptr, $3, 'o'); } - | yD_MONITOR '(' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_MONITOR, nullptr, $3); } - | yD_MONITORB '(' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_MONITOR, nullptr, $3, 'b'); } - | yD_MONITORH '(' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_MONITOR, nullptr, $3, 'h'); } - | yD_MONITORO '(' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_MONITOR, nullptr, $3, 'o'); } - | yD_STROBE '(' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_STROBE, nullptr, $3); } - | yD_STROBEB '(' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_STROBE, nullptr, $3, 'b'); } - | yD_STROBEH '(' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_STROBE, nullptr, $3, 'h'); } - | yD_STROBEO '(' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_STROBE, nullptr, $3, 'o'); } + | yD_DISPLAY parenE { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr); } + | yD_DISPLAY '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3); } + | yD_DISPLAYB parenE { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr, 'b'); } + | yD_DISPLAYB '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3, 'b'); } + | yD_DISPLAYH parenE { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr, 'h'); } + | yD_DISPLAYH '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3, 'h'); } + | yD_DISPLAYO parenE { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr, 'o'); } + | yD_DISPLAYO '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3, 'o'); } + | yD_MONITOR '(' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, nullptr, $3); } + | yD_MONITORB '(' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, nullptr, $3, 'b'); } + | yD_MONITORH '(' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, nullptr, $3, 'h'); } + | yD_MONITORO '(' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, nullptr, $3, 'o'); } + | yD_STROBE '(' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, nullptr, $3); } + | yD_STROBEB '(' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, nullptr, $3, 'b'); } + | yD_STROBEH '(' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, nullptr, $3, 'h'); } + | yD_STROBEO '(' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, nullptr, $3, 'o'); } | yD_WRITE parenE { $$ = nullptr; } // NOP - | yD_WRITE '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_WRITE, nullptr, $3); } + | yD_WRITE '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_WRITE, nullptr, $3); } | yD_WRITEB parenE { $$ = nullptr; } // NOP - | yD_WRITEB '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_WRITE, nullptr, $3, 'b'); } + | yD_WRITEB '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_WRITE, nullptr, $3, 'b'); } | yD_WRITEH parenE { $$ = nullptr; } // NOP - | yD_WRITEH '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_WRITE, nullptr, $3, 'h'); } + | yD_WRITEH '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_WRITE, nullptr, $3, 'h'); } | yD_WRITEO parenE { $$ = nullptr; } // NOP - | yD_WRITEO '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_WRITE, nullptr, $3, 'o'); } - | yD_FDISPLAY '(' expr ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, $3, nullptr); } - | yD_FDISPLAY '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, $3, $5); } - | yD_FDISPLAYB '(' expr ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, $3, nullptr, 'b'); } - | yD_FDISPLAYB '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, $3, $5, 'b'); } - | yD_FDISPLAYH '(' expr ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, $3, nullptr, 'h'); } - | yD_FDISPLAYH '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, $3, $5, 'h'); } - | yD_FDISPLAYO '(' expr ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, $3, nullptr, 'o'); } - | yD_FDISPLAYO '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_DISPLAY, $3, $5, 'o'); } - | yD_FMONITOR '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_MONITOR, $3, $5); } - | yD_FMONITORB '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_MONITOR, $3, $5, 'b'); } - | yD_FMONITORH '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_MONITOR, $3, $5, 'h'); } - | yD_FMONITORO '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_MONITOR, $3, $5, 'o'); } - | yD_FSTROBE '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_STROBE, $3, $5); } - | yD_FSTROBEB '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_STROBE, $3, $5, 'b'); } - | yD_FSTROBEH '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_STROBE, $3, $5, 'h'); } - | yD_FSTROBEO '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_STROBE, $3, $5, 'o'); } - | yD_FWRITE '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_WRITE, $3, $5); } - | yD_FWRITEB '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_WRITE, $3, $5, 'b'); } - | yD_FWRITEH '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_WRITE, $3, $5, 'h'); } - | yD_FWRITEO '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, AstDisplayType::DT_WRITE, $3, $5, 'o'); } - | yD_INFO parenE { $$ = new AstDisplay($1,AstDisplayType::DT_INFO, nullptr, nullptr); } - | yD_INFO '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_INFO, nullptr, $3); } - | yD_WARNING parenE { $$ = new AstDisplay($1,AstDisplayType::DT_WARNING, nullptr, nullptr); } - | yD_WARNING '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_WARNING, nullptr, $3); } + | yD_WRITEO '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_WRITE, nullptr, $3, 'o'); } + | yD_FDISPLAY '(' expr ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, nullptr); } + | yD_FDISPLAY '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, $5); } + | yD_FDISPLAYB '(' expr ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, nullptr, 'b'); } + | yD_FDISPLAYB '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, $5, 'b'); } + | yD_FDISPLAYH '(' expr ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, nullptr, 'h'); } + | yD_FDISPLAYH '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, $5, 'h'); } + | yD_FDISPLAYO '(' expr ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, nullptr, 'o'); } + | yD_FDISPLAYO '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, $5, 'o'); } + | yD_FMONITOR '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, $3, $5); } + | yD_FMONITORB '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, $3, $5, 'b'); } + | yD_FMONITORH '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, $3, $5, 'h'); } + | yD_FMONITORO '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, $3, $5, 'o'); } + | yD_FSTROBE '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, $3, $5); } + | yD_FSTROBEB '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, $3, $5, 'b'); } + | yD_FSTROBEH '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, $3, $5, 'h'); } + | yD_FSTROBEO '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, $3, $5, 'o'); } + | yD_FWRITE '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_WRITE, $3, $5); } + | yD_FWRITEB '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_WRITE, $3, $5, 'b'); } + | yD_FWRITEH '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_WRITE, $3, $5, 'h'); } + | yD_FWRITEO '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1, VDisplayType::DT_WRITE, $3, $5, 'o'); } + | yD_INFO parenE { $$ = new AstDisplay($1,VDisplayType::DT_INFO, nullptr, nullptr); } + | yD_INFO '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_INFO, nullptr, $3); } + | yD_WARNING parenE { $$ = new AstDisplay($1,VDisplayType::DT_WARNING, nullptr, nullptr); } + | yD_WARNING '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_WARNING, nullptr, $3); } | yD_ERROR parenE { $$ = GRAMMARP->createDisplayError($1); } - | yD_ERROR '(' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_ERROR, nullptr, $3); $$->addNext(new AstStop($1, true)); } - | yD_FATAL parenE { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, nullptr, nullptr); $$->addNext(new AstStop($1, false)); } - | yD_FATAL '(' expr ')' { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, nullptr, nullptr); $$->addNext(new AstStop($1, false)); DEL($3); } - | yD_FATAL '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, nullptr, $5); $$->addNext(new AstStop($1, false)); DEL($3); } + | yD_ERROR '(' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_ERROR, nullptr, $3); $$->addNext(new AstStop($1, true)); } + | yD_FATAL parenE { $$ = new AstDisplay($1,VDisplayType::DT_FATAL, nullptr, nullptr); $$->addNext(new AstStop($1, false)); } + | yD_FATAL '(' expr ')' { $$ = new AstDisplay($1,VDisplayType::DT_FATAL, nullptr, nullptr); $$->addNext(new AstStop($1, false)); DEL($3); } + | yD_FATAL '(' expr ',' exprDispList ')' { $$ = new AstDisplay($1,VDisplayType::DT_FATAL, nullptr, $5); $$->addNext(new AstStop($1, false)); DEL($3); } // | yD_MONITOROFF parenE { $$ = new AstMonitorOff($1, true); } | yD_MONITORON parenE { $$ = new AstMonitorOff($1, false); } @@ -3740,8 +3742,8 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task or func) | yD_ATAN '(' expr ')' { $$ = new AstAtanD($1,$3); } | yD_ATAN2 '(' expr ',' expr ')' { $$ = new AstAtan2D($1,$3,$5); } | yD_ATANH '(' expr ')' { $$ = new AstAtanhD($1,$3); } - | yD_BITS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_BITS,$3); } - | yD_BITS '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_BITS,$3,$5); } + | yD_BITS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_BITS,$3); } + | yD_BITS '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_BITS,$3,$5); } | yD_BITSTOREAL '(' expr ')' { $$ = new AstBitsToRealD($1,$3); } | yD_BITSTOSHORTREAL '(' expr ')' { $$ = new AstBitsToRealD($1,$3); UNSUPREAL($1); } | yD_CEIL '(' expr ')' { $$ = new AstCeilD($1,$3); } @@ -3757,7 +3759,7 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task or func) { $$ = new AstCountBits($1, $3, $5, $7, $9); BBUNSUP($11, "Unsupported: $countbits with more than 3 control fields"); } | yD_COUNTONES '(' expr ')' { $$ = new AstCountOnes($1,$3); } - | yD_DIMENSIONS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_DIMENSIONS,$3); } + | yD_DIMENSIONS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_DIMENSIONS,$3); } | yD_EXP '(' expr ')' { $$ = new AstExpD($1,$3); } | yD_FELL '(' expr ')' { $$ = new AstFell($1,$3); } | yD_FELL '(' expr ',' expr ')' { $$ = $3; BBUNSUP($1, "Unsupported: $fell and clock arguments"); } @@ -3773,20 +3775,20 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task or func) | yD_FSCANF '(' expr ',' str commaVRDListE ')' { $$ = new AstFScanF($1,*$5,$3,$6); } | yD_FSEEK '(' idClassSel ',' expr ',' expr ')' { $$ = new AstFSeek($1,$3,$5,$7); } | yD_FTELL '(' idClassSel ')' { $$ = new AstFTell($1, $3); } - | yD_HIGH '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_HIGH,$3,nullptr); } - | yD_HIGH '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_HIGH,$3,$5); } + | yD_HIGH '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_HIGH,$3,nullptr); } + | yD_HIGH '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_HIGH,$3,$5); } | yD_HYPOT '(' expr ',' expr ')' { $$ = new AstHypotD($1,$3,$5); } - | yD_INCREMENT '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_INCREMENT,$3,nullptr); } - | yD_INCREMENT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_INCREMENT,$3,$5); } + | yD_INCREMENT '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_INCREMENT,$3,nullptr); } + | yD_INCREMENT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_INCREMENT,$3,$5); } | yD_ISUNBOUNDED '(' expr ')' { $$ = new AstIsUnbounded($1, $3); } | yD_ISUNKNOWN '(' expr ')' { $$ = new AstIsUnknown($1, $3); } | yD_ITOR '(' expr ')' { $$ = new AstIToRD($1,$3); } - | yD_LEFT '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_LEFT,$3,nullptr); } - | yD_LEFT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_LEFT,$3,$5); } + | yD_LEFT '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_LEFT,$3,nullptr); } + | yD_LEFT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_LEFT,$3,$5); } | yD_LN '(' expr ')' { $$ = new AstLogD($1,$3); } | yD_LOG10 '(' expr ')' { $$ = new AstLog10D($1,$3); } - | yD_LOW '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_LOW,$3,nullptr); } - | yD_LOW '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_LOW,$3,$5); } + | yD_LOW '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_LOW,$3,nullptr); } + | yD_LOW '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_LOW,$3,$5); } | yD_ONEHOT '(' expr ')' { $$ = new AstOneHot($1,$3); } | yD_ONEHOT0 '(' expr ')' { $$ = new AstOneHot0($1,$3); } | yD_PAST '(' expr ')' { $$ = new AstPast($1,$3, nullptr); } @@ -3799,8 +3801,8 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task or func) | yD_REALTIME parenE { $$ = new AstTimeD($1, VTimescale(VTimescale::NONE)); } | yD_REALTOBITS '(' expr ')' { $$ = new AstRealToBits($1,$3); } | yD_REWIND '(' idClassSel ')' { $$ = new AstFSeek($1, $3, new AstConst($1, 0), new AstConst($1, 0)); } - | yD_RIGHT '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_RIGHT,$3,nullptr); } - | yD_RIGHT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_RIGHT,$3,$5); } + | yD_RIGHT '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_RIGHT,$3,nullptr); } + | yD_RIGHT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_RIGHT,$3,$5); } | yD_ROSE '(' expr ')' { $$ = new AstRose($1,$3); } | yD_ROSE '(' expr ',' expr ')' { $$ = $3; BBUNSUP($1, "Unsupported: $rose and clock arguments"); } | yD_RTOI '(' expr ')' { $$ = new AstRToIS($1,$3); } @@ -3810,8 +3812,8 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task or func) | yD_SIGNED '(' expr ')' { $$ = new AstSigned($1,$3); } | yD_SIN '(' expr ')' { $$ = new AstSinD($1,$3); } | yD_SINH '(' expr ')' { $$ = new AstSinhD($1,$3); } - | yD_SIZE '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_SIZE,$3,nullptr); } - | yD_SIZE '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_SIZE,$3,$5); } + | yD_SIZE '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_SIZE,$3,nullptr); } + | yD_SIZE '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_SIZE,$3,$5); } | yD_SQRT '(' expr ')' { $$ = new AstSqrtD($1,$3); } | yD_SSCANF '(' expr ',' str commaVRDListE ')' { $$ = new AstSScanF($1,*$5,$3,$6); } | yD_STIME parenE { $$ = new AstSel($1, new AstTime($1, VTimescale(VTimescale::NONE)), 0, 32); } @@ -3821,9 +3823,9 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task or func) | yD_TANH '(' expr ')' { $$ = new AstTanhD($1,$3); } | yD_TESTPLUSARGS '(' str ')' { $$ = new AstTestPlusArgs($1,*$3); } | yD_TIME parenE { $$ = new AstTime($1, VTimescale(VTimescale::NONE)); } - | yD_TYPENAME '(' exprOrDataType ')' { $$ = new AstAttrOf($1, AstAttrType::TYPENAME, $3); } + | yD_TYPENAME '(' exprOrDataType ')' { $$ = new AstAttrOf($1, VAttrType::TYPENAME, $3); } | yD_UNGETC '(' expr ',' expr ')' { $$ = new AstFUngetC($1, $5, $3); } // Arg swap to file first - | yD_UNPACKED_DIMENSIONS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_UNPK_DIMENSIONS,$3); } + | yD_UNPACKED_DIMENSIONS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,VAttrType::DIM_UNPK_DIMENSIONS,$3); } | yD_UNSIGNED '(' expr ')' { $$ = new AstUnsigned($1, $3); } | yD_URANDOM '(' expr ')' { $$ = new AstRand($1, $3, true); } | yD_URANDOM parenE { $$ = new AstRand($1, nullptr, true); } @@ -3839,15 +3841,15 @@ elaboration_system_task: // IEEE: elaboration_system_task (1800-2009) elaboration_system_task_guts: // IEEE: part of elaboration_system_task (1800-2009) // // $fatal first argument is exit number, must be constant - yD_INFO parenE { $$ = new AstElabDisplay($1, AstDisplayType::DT_INFO, nullptr); } - | yD_INFO '(' exprList ')' { $$ = new AstElabDisplay($1, AstDisplayType::DT_INFO, $3); } - | yD_WARNING parenE { $$ = new AstElabDisplay($1, AstDisplayType::DT_WARNING, nullptr); } - | yD_WARNING '(' exprList ')' { $$ = new AstElabDisplay($1, AstDisplayType::DT_WARNING, $3); } - | yD_ERROR parenE { $$ = new AstElabDisplay($1, AstDisplayType::DT_ERROR, nullptr); } - | yD_ERROR '(' exprList ')' { $$ = new AstElabDisplay($1, AstDisplayType::DT_ERROR, $3); } - | yD_FATAL parenE { $$ = new AstElabDisplay($1, AstDisplayType::DT_FATAL, nullptr); } - | yD_FATAL '(' expr ')' { $$ = new AstElabDisplay($1, AstDisplayType::DT_FATAL, nullptr); DEL($3); } - | yD_FATAL '(' expr ',' exprListE ')' { $$ = new AstElabDisplay($1, AstDisplayType::DT_FATAL, $5); DEL($3); } + yD_INFO parenE { $$ = new AstElabDisplay($1, VDisplayType::DT_INFO, nullptr); } + | yD_INFO '(' exprList ')' { $$ = new AstElabDisplay($1, VDisplayType::DT_INFO, $3); } + | yD_WARNING parenE { $$ = new AstElabDisplay($1, VDisplayType::DT_WARNING, nullptr); } + | yD_WARNING '(' exprList ')' { $$ = new AstElabDisplay($1, VDisplayType::DT_WARNING, $3); } + | yD_ERROR parenE { $$ = new AstElabDisplay($1, VDisplayType::DT_ERROR, nullptr); } + | yD_ERROR '(' exprList ')' { $$ = new AstElabDisplay($1, VDisplayType::DT_ERROR, $3); } + | yD_FATAL parenE { $$ = new AstElabDisplay($1, VDisplayType::DT_FATAL, nullptr); } + | yD_FATAL '(' expr ')' { $$ = new AstElabDisplay($1, VDisplayType::DT_FATAL, nullptr); DEL($3); } + | yD_FATAL '(' expr ',' exprListE ')' { $$ = new AstElabDisplay($1, VDisplayType::DT_FATAL, $5); DEL($3); } ; //UNSUPproperty_actual_arg: // ==IEEE: property_actual_arg @@ -4051,8 +4053,8 @@ tf_item_declaration: // ==IEEE: tf_item_declaration ; tf_item_declarationVerilator: // Verilator extensions - yVL_PUBLIC { $$ = new AstPragma($1,AstPragmaType::PUBLIC_TASK); v3Global.dpi(true); } - | yVL_NO_INLINE_TASK { $$ = new AstPragma($1,AstPragmaType::NO_INLINE_TASK); } + yVL_PUBLIC { $$ = new AstPragma($1,VPragmaType::PUBLIC_TASK); v3Global.dpi(true); } + | yVL_NO_INLINE_TASK { $$ = new AstPragma($1,VPragmaType::NO_INLINE_TASK); } ; tf_port_listE: // IEEE: tf_port_list + empty @@ -5007,6 +5009,8 @@ idArrayedForeach: // IEEE: id + select (under foreach expression) // // To avoid conflicts we allow expr as first element, must post-check | idArrayed '[' expr ',' loop_variables ']' { $3 = AstNode::addNextNull($3, $5); $$ = new AstSelLoopVars($2, $1, $3); } + | idArrayed '[' ',' loop_variables ']' + { $4 = AstNode::addNextNull(new AstEmpty{$3}, $4); $$ = new AstSelLoopVars($2, $1, $4); } ; // VarRef without any dots or vectorizaion @@ -5014,6 +5018,12 @@ varRefBase: id { $$ = new AstVarRef($1, *$1, VAccess::READ); } ; +// ParseRef +parseRefBase: + id + { $$ = new AstParseRef{$1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr}; } + ; + // yaSTRING shouldn't be used directly, instead via an abstraction below str: // yaSTRING but with \{escapes} need decoded yaSTRING { $$ = PARSEP->newString(GRAMMARP->deQuote($1,*$1)); } @@ -6216,8 +6226,7 @@ class_item: // ==IEEE: class_item | timeunits_declaration { $$ = $1; } //UNSUP covergroup_declaration { $$ = $1; } // // local_parameter_declaration under parameter_declaration - | parameter_declaration ';' - { $$ = $1; BBUNSUP($2, "Unsupported: class parameters"); } // 1800-2009 + | parameter_declaration ';' { $$ = $1; } | ';' { $$ = nullptr; } // | error ';' { $$ = nullptr; } @@ -6413,7 +6422,7 @@ vltItem: | yVLT_FULL_CASE yVLT_D_FILE yaSTRING yVLT_D_LINES yaINTNUM { V3Config::addCaseFull(*$3, $5->toUInt()); } | yVLT_HIER_BLOCK vltDModuleE - { V3Config::addModulePragma(*$2, AstPragmaType::HIER_BLOCK); } + { V3Config::addModulePragma(*$2, VPragmaType::HIER_BLOCK); } | yVLT_PARALLEL_CASE yVLT_D_FILE yaSTRING { V3Config::addCaseParallel(*$3, 0); } | yVLT_PARALLEL_CASE yVLT_D_FILE yaSTRING yVLT_D_LINES yaINTNUM @@ -6426,10 +6435,6 @@ vltOffFront: yVLT_COVERAGE_OFF { $$ = V3ErrorCode::I_COVERAGE; } | yVLT_TRACING_OFF { $$ = V3ErrorCode::I_TRACING; } | yVLT_LINT_OFF { $$ = V3ErrorCode::I_LINT; } - | yVLT_LINT_OFF yVLT_D_MSG idAny - { $$ = V3ErrorCode((*$3).c_str()); - if ($$ == V3ErrorCode::EC_ERROR) { $1->v3error("Unknown Error Code: " << *$3); } - $2->v3warn(DEPRECATED, "Deprecated -msg in configuration files, use -rule instead."); } | yVLT_LINT_OFF yVLT_D_RULE idAny { $$ = V3ErrorCode((*$3).c_str()); if ($$ == V3ErrorCode::EC_ERROR) { $1->v3error("Unknown Error Code: " << *$3); } } @@ -6439,10 +6444,6 @@ vltOnFront: yVLT_COVERAGE_ON { $$ = V3ErrorCode::I_COVERAGE; } | yVLT_TRACING_ON { $$ = V3ErrorCode::I_TRACING; } | yVLT_LINT_ON { $$ = V3ErrorCode::I_LINT; } - | yVLT_LINT_ON yVLT_D_MSG idAny - { $$ = V3ErrorCode((*$3).c_str()); - if ($$ == V3ErrorCode::EC_ERROR) { $1->v3error("Unknown Error Code: " << *$3); } - $2->v3warn(DEPRECATED, "Deprecated -msg in configuration files, use -rule instead."); } | yVLT_LINT_ON yVLT_D_RULE idAny { $$ = V3ErrorCode((*$3).c_str()); if ($$ == V3ErrorCode::EC_ERROR) { $1->v3error("Unknown Error Code: " << *$3); } } @@ -6470,17 +6471,18 @@ vltVarAttrVarE: ; vltVarAttrFront: - yVLT_CLOCK_ENABLE { $$ = AstAttrType::VAR_CLOCK_ENABLE; } - | yVLT_CLOCKER { $$ = AstAttrType::VAR_CLOCKER; } - | yVLT_ISOLATE_ASSIGNMENTS { $$ = AstAttrType::VAR_ISOLATE_ASSIGNMENTS; } - | yVLT_NO_CLOCKER { $$ = AstAttrType::VAR_NO_CLOCKER; } - | yVLT_PUBLIC { $$ = AstAttrType::VAR_PUBLIC; v3Global.dpi(true); } - | yVLT_PUBLIC_FLAT { $$ = AstAttrType::VAR_PUBLIC_FLAT; v3Global.dpi(true); } - | yVLT_PUBLIC_FLAT_RD { $$ = AstAttrType::VAR_PUBLIC_FLAT_RD; v3Global.dpi(true); } - | yVLT_PUBLIC_FLAT_RW { $$ = AstAttrType::VAR_PUBLIC_FLAT_RW; v3Global.dpi(true); } - | yVLT_SC_BV { $$ = AstAttrType::VAR_SC_BV; } - | yVLT_SFORMAT { $$ = AstAttrType::VAR_SFORMAT; } - | yVLT_SPLIT_VAR { $$ = AstAttrType::VAR_SPLIT_VAR; } + yVLT_CLOCK_ENABLE { $$ = VAttrType::VAR_CLOCK_ENABLE; } + | yVLT_CLOCKER { $$ = VAttrType::VAR_CLOCKER; } + | yVLT_ISOLATE_ASSIGNMENTS { $$ = VAttrType::VAR_ISOLATE_ASSIGNMENTS; } + | yVLT_NO_CLOCKER { $$ = VAttrType::VAR_NO_CLOCKER; } + | yVLT_FORCEABLE { $$ = VAttrType::VAR_FORCEABLE; } + | yVLT_PUBLIC { $$ = VAttrType::VAR_PUBLIC; v3Global.dpi(true); } + | yVLT_PUBLIC_FLAT { $$ = VAttrType::VAR_PUBLIC_FLAT; v3Global.dpi(true); } + | yVLT_PUBLIC_FLAT_RD { $$ = VAttrType::VAR_PUBLIC_FLAT_RD; v3Global.dpi(true); } + | yVLT_PUBLIC_FLAT_RW { $$ = VAttrType::VAR_PUBLIC_FLAT_RW; v3Global.dpi(true); } + | yVLT_SC_BV { $$ = VAttrType::VAR_SC_BV; } + | yVLT_SFORMAT { $$ = VAttrType::VAR_SFORMAT; } + | yVLT_SPLIT_VAR { $$ = VAttrType::VAR_SPLIT_VAR; } ; //********************************************************************** diff --git a/src/vlcovgen b/src/vlcovgen index a62b8253f..1c749e98c 100755 --- a/src/vlcovgen +++ b/src/vlcovgen @@ -83,7 +83,7 @@ parser = argparse.ArgumentParser( description= """Generate verilated_cov headers to reduce C++ code duplication.""", epilog= - """Copyright 2002-2021 by Wilson Snyder. This program is free software; you + """Copyright 2002-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/test_regress/CMakeLists.txt b/test_regress/CMakeLists.txt index 413578a64..8a7119cf0 100644 --- a/test_regress/CMakeLists.txt +++ b/test_regress/CMakeLists.txt @@ -4,7 +4,7 @@ # # This CMake file is meant to be consumed by regression tests. # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/Makefile b/test_regress/Makefile index 747e756e0..fcc0a934a 100644 --- a/test_regress/Makefile +++ b/test_regress/Makefile @@ -5,7 +5,7 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/Makefile_obj b/test_regress/Makefile_obj index 945d0cdcd..b600939fa 100644 --- a/test_regress/Makefile_obj +++ b/test_regress/Makefile_obj @@ -5,7 +5,7 @@ # # This is executed in the object directory, and called by ../Makefile # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -34,6 +34,7 @@ CPPFLAGS += -DVL_DEBUG=1 CPPFLAGS += -DTEST_OBJ_DIR=$(TEST_OBJ_DIR) CPPFLAGS += -DVM_PREFIX=$(VM_PREFIX) CPPFLAGS += -DVM_PREFIX_INCLUDE="<$(VM_PREFIX).h>" +CPPFLAGS += -DVM_PREFIX_ROOT_INCLUDE="<$(VM_PREFIX)___024root.h>" CPPFLAGS += $(CPPFLAGS_DRIVER) CPPFLAGS += $(CPPFLAGS_DRIVER2) CPPFLAGS += $(CPPFLAGS_ADD) diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 0200feddf..48b6d9539 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -1844,6 +1844,7 @@ sub _make_main { $fh->print(" std::unique_ptr tfp{new VerilatedFstSc};\n") if $self->{trace_format} eq 'fst-sc'; $fh->print(" std::unique_ptr tfp{new VerilatedVcdC};\n") if $self->{trace_format} eq 'vcd-c'; $fh->print(" std::unique_ptr tfp{new VerilatedVcdSc};\n") if $self->{trace_format} eq 'vcd-sc'; + $fh->print(" sc_core::sc_start(sc_core::SC_ZERO_TIME); // Finish elaboration before trace and open\n") if $self->sc; $fh->print(" topp->trace(tfp.get(), 99);\n"); $fh->print(" tfp->open(\"" . $self->trace_filename . "\");\n"); @@ -2433,7 +2434,7 @@ sub file_grep { return if ($contents eq "_Already_Errored_"); if ($contents !~ /$regexp/) { $self->error("File_grep: $filename: Regexp not found: $regexp\n"); - } elsif ($expvalue && $expvalue ne $1) { + } elsif (defined($expvalue) && $expvalue ne $1) { $self->error("File_grep: $filename: Got='$1' Expected='$expvalue' in regexp: $regexp\n"); } } @@ -3062,7 +3063,7 @@ Command to use to invoke XSim xvlog The latest version is available from L. -Copyright 2003-2021 by Wilson Snyder. This program is free software; you +Copyright 2003-2022 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/test_regress/t/TestCheck.h b/test_regress/t/TestCheck.h index 17236efbf..ac42dde3b 100644 --- a/test_regress/t/TestCheck.h +++ b/test_regress/t/TestCheck.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2017 by Wilson Snyder. This program is free software; you can +// Copyright 2013-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/TestSimulator.h b/test_regress/t/TestSimulator.h index 7c378e664..ba4735542 100644 --- a/test_regress/t/TestSimulator.h +++ b/test_regress/t/TestSimulator.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2017 by Wilson Snyder. This program is free software; you can +// Copyright 2013-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/TestVpi.h b/test_regress/t/TestVpi.h index bf9d1460f..389707823 100644 --- a/test_regress/t/TestVpi.h +++ b/test_regress/t/TestVpi.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2017 by Wilson Snyder. This program is free software; you can +// Copyright 2013-2022 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/t_EXAMPLE.pl b/test_regress/t/t_EXAMPLE.pl index 2cb5eeaff..1aa73f80a 100755 --- a/test_regress/t/t_EXAMPLE.pl +++ b/test_regress/t/t_EXAMPLE.pl @@ -2,7 +2,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2021 by Wilson Snyder. This program is free software; you +# Copyright 2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index 3cc26f133..0e3a9b428 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -13,7 +13,7 @@ // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by ____YOUR_NAME_HERE____. +// any use, without warranty, 2022 by ____YOUR_NAME_HERE____. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_alw_nosplit.v b/test_regress/t/t_alw_nosplit.v index 53a29461e..2bfb37b6e 100644 --- a/test_regress/t/t_alw_nosplit.v +++ b/test_regress/t/t_alw_nosplit.v @@ -47,11 +47,21 @@ module t (/*AUTOARG*/ f_split_1 = m_din; end - reg [15:0] l_split_1, l_split_2; - always @ (posedge clk) begin - l_split_2 <= l_split_1; - l_split_1 <= l_split_2 | m_din; - end + function logic[15:0] sideeffect_func(logic [15:0] v); + /*verilator no_inline_task */ + $display(" sideeffect_func() is called %t", $time); + return ~v; + endfunction + reg [15:0] m_split_1 = 0; + reg [15:0] m_split_2 = 0; + always @(posedge clk) begin + if (sideeffect_func(m_split_1) != 16'b0) begin + m_split_1 <= m_din; + end else begin + m_split_2 <= m_din; + end + end + reg [15:0] z_split_1, z_split_2; always @ (posedge clk) begin @@ -104,6 +114,7 @@ module t (/*AUTOARG*/ if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop; if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; + if (!(m_split_1==16'hfeed && m_split_2==16'h0000)) $stop; if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; end if (cyc==5) begin @@ -113,6 +124,7 @@ module t (/*AUTOARG*/ // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; + if (!(m_split_1==16'hfeed && m_split_2==16'h0000)) $stop; if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; end if (cyc==6) begin @@ -122,6 +134,7 @@ module t (/*AUTOARG*/ // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; + if (!(m_split_1==16'he11e && m_split_2==16'h0000)) $stop; if (!(z_split_1==16'h1ee1 && z_split_2==16'h0112)) $stop; end if (cyc==7) begin diff --git a/test_regress/t/t_alw_split.pl b/test_regress/t/t_alw_split.pl index ba9c8f933..7b60fb6fc 100755 --- a/test_regress/t/t_alw_split.pl +++ b/test_regress/t/t_alw_split.pl @@ -15,7 +15,7 @@ compile( ); if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 3); + file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 4); } execute( diff --git a/test_regress/t/t_alw_split.v b/test_regress/t/t_alw_split.v index 8d5419ac1..b6b1e7efa 100644 --- a/test_regress/t/t_alw_split.v +++ b/test_regress/t/t_alw_split.v @@ -50,6 +50,12 @@ module t (/*AUTOARG*/ end end + reg [15:0] l_split_1, l_split_2; + always @ (posedge clk) begin + l_split_2 <= l_split_1; + l_split_1 <= l_split_2 | m_din; + end + // (The checker block is an exception, it won't split.) always @ (posedge clk) begin if (cyc!=0) begin diff --git a/test_regress/t/t_alw_split_rst.pl b/test_regress/t/t_alw_split_rst.pl index 87d186513..fe393b88e 100755 --- a/test_regress/t/t_alw_split_rst.pl +++ b/test_regress/t/t_alw_split_rst.pl @@ -16,7 +16,7 @@ compile( ); if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); + file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 12); } execute( diff --git a/test_regress/t/t_alw_splitord.pl b/test_regress/t/t_alw_splitord.pl index a1d66aaad..972bb3672 100755 --- a/test_regress/t/t_alw_splitord.pl +++ b/test_regress/t/t_alw_splitord.pl @@ -15,7 +15,7 @@ compile( ); if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); + file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 5); } execute( diff --git a/test_regress/t/t_assoc.v b/test_regress/t/t_assoc.v index 278003ca4..9e20a7626 100644 --- a/test_regress/t/t_assoc.v +++ b/test_regress/t/t_assoc.v @@ -44,6 +44,12 @@ module t (/*AUTOARG*/ i = a.prev(k); `checkh(i, 0); v = $sformatf("%p", a); `checks(v, "'{'h2:\"bared\", 'h3:\"fooed\"} "); + a.first(k); `checks(k, 4'd2); + a.next(k); `checks(k, 4'd3); + a.next(k); + a.last(k); `checks(k, 4'd3); + a.prev(k); `checks(k, 4'd2); + a.delete(4'd2); i = a.size(); `checkh(i, 1); @@ -99,6 +105,16 @@ module t (/*AUTOARG*/ `checkh(a[~65'hfe], ~ 90'hfee); end + begin + int a [string]; + int sum; + sum = 0; + a["one"] = 1; + a["two"] = 2; + foreach (a[i]) sum += a[i]; + `checkh(sum, 1 + 2); + end + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_case_huge.pl b/test_regress/t/t_case_huge.pl index b8b37ebdc..73bc861e6 100755 --- a/test_regress/t/t_case_huge.pl +++ b/test_regress/t/t_case_huge.pl @@ -16,8 +16,7 @@ compile( if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10); - file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, - ($Self->{vltmt} ? 0 : 8)); + file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 8); } execute( diff --git a/test_regress/t/t_case_incrdecr.pl b/test_regress/t/t_case_incrdecr.pl new file mode 100755 index 000000000..abbcf936a --- /dev/null +++ b/test_regress/t/t_case_incrdecr.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--trace --Os -x-assign 0"], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_case_incrdecr.v b/test_regress/t/t_case_incrdecr.v new file mode 100644 index 000000000..4b3e6e2fc --- /dev/null +++ b/test_regress/t/t_case_incrdecr.v @@ -0,0 +1,156 @@ +module t + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + int cyc = 0; + + logic [1:0] case_sel; + + always @ (posedge clk) begin : main + cyc <= cyc + 1; + + case_sel <= 2'($urandom); + + if (cyc > 100) begin + $write("*-* All Finished *-*\n"); + $finish(); + end + end + + + // ------------------------- + // Simple case-stmt with ++/-- + + logic [3:0] count_d; + logic [3:0] count_q = '0; + + logic [3:0] want_count_d; + logic [3:0] want_count_q = '0; + + always_ff @(posedge clk) begin : flops + count_q <= count_d; + want_count_q <= want_count_d; + end + + always @(posedge clk) begin : simple_check + if (cyc > 0) begin + if (count_q !== want_count_q) begin + $error("%m: Checks cyc=%0d, count_q (%0d) !== want_count_q (%0d)", + cyc, count_q, want_count_q); + $stop; // don't finish to fail the test. + end + end + end + + always_comb begin : update_golden_counts + want_count_d = want_count_q; + if (case_sel == 2'b10) + want_count_d++; + else if (case_sel == 2'b01) + want_count_d--; + end + + // Make sure the ++ and -- operators are handled correctly in case stmts. + // Test for https://github.com/verilator/verilator/issues/3346 + always_comb begin : update_counts + count_d = count_q; + case (case_sel) + 2'b10: count_d++; + 2'b01: count_d--; + default : ; + endcase // case (case_sel) + end + + // ------------------------- + // FSM with ++/-- + // A more elaborate case statement, with if-else, for loops, etc + // to confirm that ++/-- is handled by V3LinkInc.cpp + logic [3:0] state_d, state_q; + initial state_q = '0; + logic [3:0] state_counter_d, state_counter_q; + always_ff @(posedge clk) begin + state_q <= state_d; + state_counter_q <= state_counter_d; + end + + + always_comb begin : update_state + state_d = state_q; + state_counter_d = state_counter_q; + case (state_q) + + // state 0, no begin/end, goes to state 1 + 4'd0: state_d = 4'd1; + + // state 1, clears state_counter_d, goes to state 2 + 4'd1: begin + state_d = 4'd2; + state_counter_d = '0; + end + + // state 2, wait until state_counter_d increments to 4. + 4'd2: begin + state_counter_d++; + if (state_counter_q == 4) begin + state_d = 4'd3; + end + end + // state 3, decrements state_counter_d from 5 to 0. + 4'd3: begin + state_counter_d--; + if (state_counter_q == 1) begin + state_d = 4'd4; + end + end + + 4'd4: begin + // add 4 with for-loop and ++. + for (int unsigned i = 0; i < 4; i++) begin + state_counter_d++; + end + + if (state_counter_q == 12) begin + state_counter_d = '0; + state_d = 4'd5; + end + end + + 4'd5: begin + // add 8 with a while loop and go to state 6. + while (state_counter_d <= 7) begin + state_counter_d++; + end + + if (state_counter_d == 8) begin + state_d = 4'd15; + end + end + 4'd15 : begin + // success, stay here. + state_counter_d = 4'd7; // pick and hold some success number. + end + default: ; + endcase // case (state_q) + + end // block: state + + always @(posedge clk) begin : simple_state_check + //$display("%m: debug, cyc=%0d, state_q=%0d, state_counter_q=%0d", + // cyc, state_q, state_counter_q); + if (cyc >= 90) begin + // the above FSM should finish before 90 cycles. + // Make sure we made it to state 4'd15. + if (state_q !== 4'd15 || + state_counter_q !== 4'd7) begin + $error("%m: EOT checks, cyc=%0d, state_q=%0d (want 15), state_counter_q=%0d (want 7)", + cyc, state_q, state_counter_q); + $stop; // don't finish to fail the test. + end + end + end + +endmodule : t diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v index bf7ca06c5..6a3990561 100644 --- a/test_regress/t/t_cast.v +++ b/test_regress/t/t_cast.v @@ -15,6 +15,7 @@ module t; typedef logic [3:0] mc_t; typedef mc_t tocast_t; + typedef logic [2:0] [7:0] two_dee_t; typedef struct packed { logic [15:0] data; @@ -42,6 +43,8 @@ module t; logic [15:0] allones = 16'hffff; parameter FOUR = 4; + localparam two_dee_t two_dee = two_dee_t'(32'habcdef); + // bug925 localparam [6:0] RESULT = 7'((6*9+92)%96); @@ -63,6 +66,9 @@ module t; logic [32:0] b33 = {32'(0), one}; logic [31:0] b32 = {31'(0), one}; + logic [31:0] thirty_two_bits; + two_dee_t two_dee_sig; + initial begin if (logic8bit != 8'h12) $stop; if (4'shf > 4'sh0) $stop; @@ -107,6 +113,17 @@ module t; if (b33 != 33'b1) $stop; if (b32 != 32'b1) $stop; + if (two_dee[0] != 8'hef) $stop; + if (two_dee[1] != 8'hcd) $stop; + if (two_dee[2] != 8'hab) $stop; + + thirty_two_bits = 32'h123456; + two_dee_sig = two_dee_t'(thirty_two_bits); + + if (two_dee_sig[0] != 8'h56) $stop; + if (two_dee_sig[1] != 8'h34) $stop; + if (two_dee_sig[2] != 8'h12) $stop; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_cdc_async_bad.out b/test_regress/t/t_cdc_async_bad.out index 64dd3783f..697a80fe0 100644 --- a/test_regress/t/t_cdc_async_bad.out +++ b/test_regress/t/t_cdc_async_bad.out @@ -1,8 +1,9 @@ +%Warning-DEPRECATED: Option --cdc is deprecated and is planned for removal + ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest + ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:28:21: Logic in path that feeds async reset, via signal: 't.rst2_bad_n' 28 | wire rst2_bad_n = rst0_n | rst1_n; | ^ - ... For warning description see https://verilator.org/warn/CDCRSTLOGIC?v=latest - ... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53:21: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n' 53 | wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); diff --git a/test_regress/t/t_class_format.out b/test_regress/t/t_class_format.out index e4886448b..dd9e17d2a 100644 --- a/test_regress/t/t_class_format.out +++ b/test_regress/t/t_class_format.out @@ -1,4 +1,4 @@ -''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44} , name:"object_name"}' -''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944} , name:"object_name"}' +''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44} , cwide:'{'h0, 'h0} , name:"object_name"}' +''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944} , cwide:'{'h0, 'h0} , name:"object_name"}' DEBUG: object_name (@0) message *-* All Finished *-* diff --git a/test_regress/t/t_class_format.v b/test_regress/t/t_class_format.v index 15a67bca9..ac11b68c0 100644 --- a/test_regress/t/t_class_format.v +++ b/test_regress/t/t_class_format.v @@ -15,6 +15,7 @@ class Cls; bit b; int i; bit [15:0] carray4 [4]; + bit [64:0] cwide[2]; string name; task debug(); $display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message"); diff --git a/test_regress/t/t_class_param.out b/test_regress/t/t_class_param.out index 6e28c9b3d..442cfc01e 100644 --- a/test_regress/t/t_class_param.out +++ b/test_regress/t/t_class_param.out @@ -1,10 +1,30 @@ -%Error-UNSUPPORTED: t/t_class_param.v:9:23: Unsupported: class parameters - : ... In instance t - 9 | class Cls #(parameter P = 12); - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_class_param.v:20:11: Unsupported: parameterized classes +%Error-UNSUPPORTED: t/t_class_param.v:40:11: Unsupported: parameterized classes : ... In instance t - 20 | Cls #(.P(4)) c4; - | ^ + 40 | Cls #(.PBASE(4)) c4; + | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_class_param.v:42:12: Unsupported: parameterized classes + : ... In instance t + 42 | Wrap #(.P(16)) w16; + | ^ +%Error-UNSUPPORTED: t/t_class_param.v:13:24: Unsupported: class parameters + : ... In instance t + 13 | class Wrap #(parameter P = 13); + | ^ +%Error-UNSUPPORTED: t/t_class_param.v:21:15: Unsupported: class parameters + : ... In instance t + 21 | localparam PMINUS1 = P - 1; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_class_param.v:20:17: Unsupported: parameterized classes + : ... In instance t + 20 | Cls#(PMINUS1 + 1) c1; + | ^ +%Error-UNSUPPORTED: t/t_class_param.v:24:23: Unsupported: class parameters + : ... In instance t + 24 | class Cls #(parameter PBASE = 12); + | ^~~~~ +%Error-UNSUPPORTED: t/t_class_param.v:35:14: Unsupported: parameterized classes + : ... In instance t + 35 | typedef Cls#(8) Cls8_t; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_param.v b/test_regress/t/t_class_param.v index 6313faf57..0fc61cb76 100644 --- a/test_regress/t/t_class_param.v +++ b/test_regress/t/t_class_param.v @@ -4,36 +4,80 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); -class Cls #(parameter P = 12); - bit [P-1:0] member; - function bit [P-1:0] get_member; - return member; - endfunction +// See also t_class_param_mod.v + +typedef class Cls; + +class Wrap #(parameter P = 13); function int get_p; - return P; + return c1.get_p(); endfunction + function new; + c1 = new; + endfunction + Cls#(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last endclass - Cls c12; - Cls #(.P(4)) c4; +class Cls #(parameter PBASE = 12); + bit [PBASE-1:0] member; + function bit [PBASE-1:0] get_member; + return member; + endfunction + static function int get_p; + return PBASE; + endfunction + typedef enum { E_PBASE = PBASE } enum_t; +endclass +typedef Cls#(8) Cls8_t; + +module t (/*AUTOARG*/); + + Cls c12; + Cls #(.PBASE(4)) c4; + Cls8_t c8; + Wrap #(.P(16)) w16; initial begin c12 = new; c4 = new; - if (c12.P != 12) $stop; - if (c4.P != 4) $stop; + c8 = new; + w16 = new; + if (Cls#()::PBASE != 12) $stop; + if (Cls#(4)::PBASE != 4) $stop; + if (Cls8_t::PBASE != 8) $stop; + + if (Cls#()::E_PBASE != 12) $stop; + if (Cls#(4)::E_PBASE != 4) $stop; + if (Cls8_t::E_PBASE != 8) $stop; + + if (c12.PBASE != 12) $stop; + if (c4.PBASE != 4) $stop; + if (c8.PBASE != 8) $stop; + + if (Cls#()::get_p() != 12) $stop; + if (Cls#(4)::get_p() != 4) $stop; + if (Cls8_t::get_p() != 8) $stop; + if (c12.get_p() != 12) $stop; if (c4.get_p() != 4) $stop; + if (c8.get_p() != 8) $stop; + if (w16.get_p() != 16) $stop; + // verilator lint_off WIDTH c12.member = 32'haaaaaaaa; c4.member = 32'haaaaaaaa; + c8.member = 32'haaaaaaaa; // verilator lint_on WIDTH if (c12.member != 12'haaa) $stop; if (c4.member != 4'ha) $stop; if (c12.get_member() != 12'haaa) $stop; if (c4.get_member() != 4'ha) $stop; + `checks($sformatf("%p", c12), "'{member:'haaa}"); + `checks($sformatf("%p", c4), "'{member:'ha}"); + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_class_param_mod.pl b/test_regress/t/t_class_param_mod.pl new file mode 100755 index 000000000..a2ed99042 --- /dev/null +++ b/test_regress/t/t_class_param_mod.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_class_param_mod.v b/test_regress/t/t_class_param_mod.v new file mode 100644 index 000000000..67065e2d7 --- /dev/null +++ b/test_regress/t/t_class_param_mod.v @@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +// See also t_class_param.v + +module t (/*AUTOARG*/); + +class Cls #(parameter PBASE = 12); + bit [PBASE-1:0] member; + function bit [PBASE-1:0] get_member; + return member; + endfunction + static function int get_p; + return PBASE; + endfunction + typedef enum { E_PBASE = PBASE } enum_t; +endclass + +class Wrap #(parameter P = 13); + function int get_p; + return c1.get_p(); + endfunction + function new; + c1 = new; + endfunction + Cls#(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last +endclass + + typedef Cls#(8) Cls8_t; + + Cls c12; + Cls #(.PBASE(4)) c4; + Cls8_t c8; + Wrap #(.P(16)) w16; + initial begin + c12 = new; + c4 = new; + c8 = new; + w16 = new; + if (Cls#()::PBASE != 12) $stop; + if (Cls#(4)::PBASE != 4) $stop; + if (Cls8_t::PBASE != 8) $stop; + + if (Cls#()::E_PBASE != 12) $stop; + if (Cls#(4)::E_PBASE != 4) $stop; + if (Cls8_t::E_PBASE != 8) $stop; + + if (c12.PBASE != 12) $stop; + if (c4.PBASE != 4) $stop; + if (c8.PBASE != 8) $stop; + + if (Cls#()::get_p() != 12) $stop; + if (Cls#(4)::get_p() != 4) $stop; + if (Cls8_t::get_p() != 8) $stop; + + if (c12.get_p() != 12) $stop; + if (c4.get_p() != 4) $stop; + if (c8.get_p() != 8) $stop; + if (w16.get_p() != 16) $stop; + + // verilator lint_off WIDTH + c12.member = 32'haaaaaaaa; + c4.member = 32'haaaaaaaa; + c8.member = 32'haaaaaaaa; + // verilator lint_on WIDTH + if (c12.member != 12'haaa) $stop; + if (c4.member != 4'ha) $stop; + if (c12.get_member() != 12'haaa) $stop; + if (c4.get_member() != 4'ha) $stop; + `checks($sformatf("%p", c12), "'{member:'haaa}"); + `checks($sformatf("%p", c4), "'{member:'ha}"); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_param_nconst_bad.out b/test_regress/t/t_class_param_nconst_bad.out new file mode 100644 index 000000000..100f930d8 --- /dev/null +++ b/test_regress/t/t_class_param_nconst_bad.out @@ -0,0 +1,10 @@ +%Error-UNSUPPORTED: t/t_class_param_nconst_bad.v:12:11: Unsupported: parameterized classes + : ... In instance t + 12 | Cls #(.PARAM($random)) c; + | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_class_param_nconst_bad.v:7:23: Unsupported: class parameters + : ... In instance t + 7 | class Cls #(parameter PARAM = 12); + | ^~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_class_param_nconst_bad.pl b/test_regress/t/t_class_param_nconst_bad.pl new file mode 100755 index 000000000..7be596e0f --- /dev/null +++ b/test_regress/t/t_class_param_nconst_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_param_nconst_bad.v b/test_regress/t/t_class_param_nconst_bad.v new file mode 100644 index 000000000..c7c37437d --- /dev/null +++ b/test_regress/t/t_class_param_nconst_bad.v @@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Cls #(parameter PARAM = 12); +endclass + +module t (/*AUTOARG*/); + + Cls #(.PARAM($random)) c; // Bad param name + +endmodule diff --git a/test_regress/t/t_class_param_pkg.out b/test_regress/t/t_class_param_pkg.out new file mode 100644 index 000000000..a01b5aed6 --- /dev/null +++ b/test_regress/t/t_class_param_pkg.out @@ -0,0 +1,30 @@ +%Error-UNSUPPORTED: t/t_class_param_pkg.v:43:16: Unsupported: parameterized classes + : ... In instance t + 43 | Pkg::Cls #(.PBASE(4)) c4; + | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_class_param_pkg.v:45:17: Unsupported: parameterized classes + : ... In instance t + 45 | Pkg::Wrap #(.P(16)) w16; + | ^ +%Error-UNSUPPORTED: t/t_class_param_pkg.v:14:27: Unsupported: class parameters + : ... In instance t + 14 | class Wrap #(parameter P = 13); + | ^ +%Error-UNSUPPORTED: t/t_class_param_pkg.v:22:18: Unsupported: class parameters + : ... In instance t + 22 | localparam PMINUS1 = P - 1; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_class_param_pkg.v:21:20: Unsupported: parameterized classes + : ... In instance t + 21 | Cls#(PMINUS1 + 1) c1; + | ^ +%Error-UNSUPPORTED: t/t_class_param_pkg.v:25:26: Unsupported: class parameters + : ... In instance t + 25 | class Cls #(parameter PBASE = 12); + | ^~~~~ +%Error-UNSUPPORTED: t/t_class_param_pkg.v:36:22: Unsupported: parameterized classes + : ... In instance t + 36 | typedef Pkg::Cls#(8) Cls8_t; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_class_param_pkg.pl b/test_regress/t/t_class_param_pkg.pl new file mode 100755 index 000000000..2ad4a887d --- /dev/null +++ b/test_regress/t/t_class_param_pkg.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_class_param_pkg.v b/test_regress/t/t_class_param_pkg.v new file mode 100644 index 000000000..4c53244f8 --- /dev/null +++ b/test_regress/t/t_class_param_pkg.v @@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +// See also t_class_param_mod.v + +package Pkg; + typedef class Cls; + + class Wrap #(parameter P = 13); + function int get_p; + return c1.get_p(); + endfunction + function new; + c1 = new; + endfunction + Cls#(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last + endclass + + class Cls #(parameter PBASE = 12); + bit [PBASE-1:0] member; + function bit [PBASE-1:0] get_member; + return member; + endfunction + static function int get_p; + return PBASE; + endfunction + typedef enum { E_PBASE = PBASE } enum_t; + endclass + + typedef Pkg::Cls#(8) Cls8_t; + +endpackage + +module t (/*AUTOARG*/); + + Pkg::Cls c12; + Pkg::Cls #(.PBASE(4)) c4; + Pkg::Cls8_t c8; + Pkg::Wrap #(.P(16)) w16; + initial begin + c12 = new; + c4 = new; + c8 = new; + w16 = new; + if (Pkg::Cls#()::PBASE != 12) $stop; + if (Pkg::Cls#(4)::PBASE != 4) $stop; + if (Pkg::Cls8_t::PBASE != 8) $stop; + + if (Pkg::Cls#()::E_PBASE != 12) $stop; + if (Pkg::Cls#(4)::E_PBASE != 4) $stop; + if (Pkg::Cls8_t::E_PBASE != 8) $stop; + + if (c12.PBASE != 12) $stop; + if (c4.PBASE != 4) $stop; + if (c8.PBASE != 8) $stop; + + if (Pkg::Cls#()::get_p() != 12) $stop; + if (Pkg::Cls#(4)::get_p() != 4) $stop; + if (Pkg::Cls8_t::get_p() != 8) $stop; + + if (c12.get_p() != 12) $stop; + if (c4.get_p() != 4) $stop; + if (c8.get_p() != 8) $stop; + if (w16.get_p() != 16) $stop; + + // verilator lint_off WIDTH + c12.member = 32'haaaaaaaa; + c4.member = 32'haaaaaaaa; + c8.member = 32'haaaaaaaa; + // verilator lint_on WIDTH + if (c12.member != 12'haaa) $stop; + if (c4.member != 4'ha) $stop; + if (c12.get_member() != 12'haaa) $stop; + if (c4.get_member() != 4'ha) $stop; + `checks($sformatf("%p", c12), "'{member:'haaa}"); + `checks($sformatf("%p", c4), "'{member:'ha}"); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_static.out b/test_regress/t/t_class_static.out index 922e3f434..927221b52 100644 --- a/test_regress/t/t_class_static.out +++ b/test_regress/t/t_class_static.out @@ -1,10 +1,6 @@ -%Error-UNSUPPORTED: t/t_class_static.v:12:15: Unsupported: 'static' class members - : ... In instance t - 12 | static int c_st = 2; - | ^~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_class_static.v:25:18: Unsupported: 'static' function/task variables : ... In instance t 25 | static int st = 2; st++; return st; | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_class_static_member.pl b/test_regress/t/t_class_static_member.pl new file mode 100755 index 000000000..b46d46042 --- /dev/null +++ b/test_regress/t/t_class_static_member.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_static_member.v b/test_regress/t/t_class_static_member.v new file mode 100644 index 000000000..bc772f2e6 --- /dev/null +++ b/test_regress/t/t_class_static_member.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +class Cls; + int c_no = 2; + //automatic int c_au = 2; // automatic not a legal keyword here + static int c_st = 22; + + function int f_c_no (); + ++c_no; return c_no; + endfunction + function int f_c_st (); + ++c_st; return c_st; + endfunction + + static function int f_cs_st (); + ++c_st; return c_st; + endfunction + +endclass + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + Cls a = new; + Cls b = new; + + int v; + + initial begin + v = a.f_c_no(); `checkh(v, 3); + v = a.f_c_no(); `checkh(v, 4); + v = b.f_c_no(); `checkh(v, 3); + v = b.f_c_no(); `checkh(v, 4); + v = a.f_c_st(); `checkh(v, 23); + v = a.f_c_st(); `checkh(v, 24); + v = b.f_c_st(); `checkh(v, 25); + v = b.f_c_st(); `checkh(v, 26); + // + v = Cls::f_cs_st(); `checkh(v, 27); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_class_static_member_pkg.pl b/test_regress/t/t_class_static_member_pkg.pl new file mode 100755 index 000000000..b46d46042 --- /dev/null +++ b/test_regress/t/t_class_static_member_pkg.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_static_member_pkg.v b/test_regress/t/t_class_static_member_pkg.v new file mode 100644 index 000000000..ac36ab758 --- /dev/null +++ b/test_regress/t/t_class_static_member_pkg.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +package Pkg; +class Cls; + int c_no = 2; + //automatic int c_au = 2; // automatic not a legal keyword here + static int c_st = 22; + + function int f_c_no (); + ++c_no; return c_no; + endfunction + function int f_c_st (); + ++c_st; return c_st; + endfunction + + static function int f_cs_st (); + ++c_st; return c_st; + endfunction + +endclass +endpackage + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + Pkg::Cls a = new; + Pkg::Cls b = new; + + int v; + + initial begin + v = a.f_c_no(); `checkh(v, 3); + v = a.f_c_no(); `checkh(v, 4); + v = b.f_c_no(); `checkh(v, 3); + v = b.f_c_no(); `checkh(v, 4); + v = a.f_c_st(); `checkh(v, 23); + v = a.f_c_st(); `checkh(v, 24); + v = b.f_c_st(); `checkh(v, 25); + v = b.f_c_st(); `checkh(v, 26); + // + v = Pkg::Cls::f_cs_st(); `checkh(v, 27); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_class_static_order.out b/test_regress/t/t_class_static_order.out deleted file mode 100644 index 211d7e595..000000000 --- a/test_regress/t/t_class_static_order.out +++ /dev/null @@ -1,14 +0,0 @@ -%Error-UNSUPPORTED: t/t_class_static_order.v:23:16: Unsupported: 'static' class members - : ... In instance t - 23 | static ClsZ z = new; - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_class_static_order.v:34:16: Unsupported: 'static' class members - : ... In instance t - 34 | static ClsA a = new; - | ^ -%Error-UNSUPPORTED: t/t_class_static_order.v:35:16: Unsupported: 'static' class members - : ... In instance t - 35 | static ClsB b = new; - | ^ -%Error: Exiting due to diff --git a/test_regress/t/t_class_static_order.pl b/test_regress/t/t_class_static_order.pl index 2ad4a887d..aabcde63e 100755 --- a/test_regress/t/t_class_static_order.pl +++ b/test_regress/t/t_class_static_order.pl @@ -11,13 +11,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, ); execute( check_finished => 1, - ) if !$Self->{vlt_all}; + ); ok(1); 1; diff --git a/test_regress/t/t_class_unsup_bad.out b/test_regress/t/t_class_unsup_bad.out index 9b2c8fa30..eba10d537 100644 --- a/test_regress/t/t_class_unsup_bad.out +++ b/test_regress/t/t_class_unsup_bad.out @@ -5,9 +5,6 @@ %Error-UNSUPPORTED: t/t_class_unsup_bad.v:8:1: Unsupported: virtual data type 8 | virtual vi_t vi2; | ^~~~~~~ -%Error-UNSUPPORTED: t/t_class_unsup_bad.v:14:26: Unsupported: class parameters - 14 | localparam LOCPAR = 10; - | ^ %Error: t/t_class_unsup_bad.v:29:24: Syntax error: 'const'/'rand'/'randc' not allowed before function/task declaration 29 | const function void func_const; endfunction | ^~~~~~~~~~ diff --git a/test_regress/t/t_clk_concat.pl b/test_regress/t/t_clk_concat.pl index cebae1cb9..6506f7873 100755 --- a/test_regress/t/t_clk_concat.pl +++ b/test_regress/t/t_clk_concat.pl @@ -17,9 +17,9 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_clk_concat_vlt.pl b/test_regress/t/t_clk_concat_vlt.pl index 9808ed638..aada588d7 100755 --- a/test_regress/t/t_clk_concat_vlt.pl +++ b/test_regress/t/t_clk_concat_vlt.pl @@ -18,10 +18,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_cover_line_trace.out b/test_regress/t/t_cover_line_trace.out index 56c0bd1d1..9c6365e91 100644 --- a/test_regress/t/t_cover_line_trace.out +++ b/test_regress/t/t_cover_line_trace.out @@ -1,7 +1,6 @@ $version Generated by VerilatedVcd $end -$date Sun May 31 15:48:42 2020 - $end -$timescale 1ps $end +$date Sat Dec 18 13:32:31 2021 $end +$timescale 1ps $end $scope module top $end $var wire 1 W clk $end @@ -11,31 +10,31 @@ $timescale 1ps $end $var wire 8 ' cyc_copy [7:0] $end $var wire 1 % toggle $end $var wire 32 ; vlCoverageLineTrace_t_cover_line__102_elsif [31:0] $end - $var wire 32 : vlCoverageLineTrace_t_cover_line__105_elsif [31:0] $end - $var wire 32 9 vlCoverageLineTrace_t_cover_line__112_else [31:0] $end - $var wire 32 8 vlCoverageLineTrace_t_cover_line__112_if [31:0] $end + $var wire 32 < vlCoverageLineTrace_t_cover_line__105_elsif [31:0] $end + $var wire 32 = vlCoverageLineTrace_t_cover_line__112_else [31:0] $end + $var wire 32 > vlCoverageLineTrace_t_cover_line__112_if [31:0] $end $var wire 32 X vlCoverageLineTrace_t_cover_line__119_block [31:0] $end $var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end $var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end - $var wire 32 > vlCoverageLineTrace_t_cover_line__47_block [31:0] $end - $var wire 32 = vlCoverageLineTrace_t_cover_line__48_else [31:0] $end - $var wire 32 < vlCoverageLineTrace_t_cover_line__48_if [31:0] $end - $var wire 32 ) vlCoverageLineTrace_t_cover_line__52_else [31:0] $end - $var wire 32 ( vlCoverageLineTrace_t_cover_line__52_if [31:0] $end - $var wire 32 + vlCoverageLineTrace_t_cover_line__53_else [31:0] $end - $var wire 32 * vlCoverageLineTrace_t_cover_line__53_if [31:0] $end - $var wire 32 - vlCoverageLineTrace_t_cover_line__58_else [31:0] $end - $var wire 32 , vlCoverageLineTrace_t_cover_line__58_if [31:0] $end - $var wire 32 / vlCoverageLineTrace_t_cover_line__59_else [31:0] $end - $var wire 32 . vlCoverageLineTrace_t_cover_line__59_if [31:0] $end - $var wire 32 1 vlCoverageLineTrace_t_cover_line__65_else [31:0] $end - $var wire 32 0 vlCoverageLineTrace_t_cover_line__65_if [31:0] $end - $var wire 32 3 vlCoverageLineTrace_t_cover_line__66_else [31:0] $end - $var wire 32 2 vlCoverageLineTrace_t_cover_line__66_if [31:0] $end + $var wire 32 ( vlCoverageLineTrace_t_cover_line__47_block [31:0] $end + $var wire 32 ) vlCoverageLineTrace_t_cover_line__48_else [31:0] $end + $var wire 32 * vlCoverageLineTrace_t_cover_line__48_if [31:0] $end + $var wire 32 + vlCoverageLineTrace_t_cover_line__52_else [31:0] $end + $var wire 32 , vlCoverageLineTrace_t_cover_line__52_if [31:0] $end + $var wire 32 - vlCoverageLineTrace_t_cover_line__53_else [31:0] $end + $var wire 32 . vlCoverageLineTrace_t_cover_line__53_if [31:0] $end + $var wire 32 / vlCoverageLineTrace_t_cover_line__58_else [31:0] $end + $var wire 32 0 vlCoverageLineTrace_t_cover_line__58_if [31:0] $end + $var wire 32 1 vlCoverageLineTrace_t_cover_line__59_else [31:0] $end + $var wire 32 2 vlCoverageLineTrace_t_cover_line__59_if [31:0] $end + $var wire 32 3 vlCoverageLineTrace_t_cover_line__65_else [31:0] $end + $var wire 32 4 vlCoverageLineTrace_t_cover_line__65_if [31:0] $end + $var wire 32 5 vlCoverageLineTrace_t_cover_line__66_else [31:0] $end + $var wire 32 6 vlCoverageLineTrace_t_cover_line__66_if [31:0] $end $var wire 32 7 vlCoverageLineTrace_t_cover_line__75_elsif [31:0] $end - $var wire 32 6 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end - $var wire 32 5 vlCoverageLineTrace_t_cover_line__83_else [31:0] $end - $var wire 32 4 vlCoverageLineTrace_t_cover_line__83_if [31:0] $end + $var wire 32 8 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end + $var wire 32 9 vlCoverageLineTrace_t_cover_line__83_else [31:0] $end + $var wire 32 : vlCoverageLineTrace_t_cover_line__83_if [31:0] $end $var wire 32 ] vlCoverageLineTrace_t_cover_line__92_block [31:0] $end $var wire 32 ^ vlCoverageLineTrace_t_cover_line__93_block [31:0] $end $var wire 32 _ vlCoverageLineTrace_t_cover_line__96_block [31:0] $end @@ -43,57 +42,57 @@ $timescale 1ps $end $scope module a1 $end $var wire 1 W clk $end $var wire 1 % toggle $end - $var wire 32 B vlCoverageLineTrace_t_cover_line__132_block [31:0] $end + $var wire 32 ? vlCoverageLineTrace_t_cover_line__132_block [31:0] $end $var wire 32 @ vlCoverageLineTrace_t_cover_line__133_else [31:0] $end - $var wire 32 ? vlCoverageLineTrace_t_cover_line__133_if [31:0] $end - $var wire 32 A vlCoverageLineTrace_t_cover_line__137_else [31:0] $end + $var wire 32 A vlCoverageLineTrace_t_cover_line__133_if [31:0] $end + $var wire 32 B vlCoverageLineTrace_t_cover_line__137_else [31:0] $end $upscope $end $scope module a2 $end $var wire 1 W clk $end $var wire 1 % toggle $end - $var wire 32 F vlCoverageLineTrace_t_cover_line__132_block [31:0] $end + $var wire 32 C vlCoverageLineTrace_t_cover_line__132_block [31:0] $end $var wire 32 D vlCoverageLineTrace_t_cover_line__133_else [31:0] $end - $var wire 32 C vlCoverageLineTrace_t_cover_line__133_if [31:0] $end - $var wire 32 E vlCoverageLineTrace_t_cover_line__137_else [31:0] $end + $var wire 32 E vlCoverageLineTrace_t_cover_line__133_if [31:0] $end + $var wire 32 F vlCoverageLineTrace_t_cover_line__137_else [31:0] $end $upscope $end $scope module b1 $end $var wire 1 W clk $end $var wire 1 % toggle $end - $var wire 32 O vlCoverageLineTrace_t_cover_line__156_block [31:0] $end - $var wire 32 K vlCoverageLineTrace_t_cover_line__158_else [31:0] $end + $var wire 32 K vlCoverageLineTrace_t_cover_line__156_block [31:0] $end + $var wire 32 L vlCoverageLineTrace_t_cover_line__158_else [31:0] $end $var wire 32 b vlCoverageLineTrace_t_cover_line__158_if [31:0] $end $var wire 32 M vlCoverageLineTrace_t_cover_line__162_else [31:0] $end - $var wire 32 L vlCoverageLineTrace_t_cover_line__162_if [31:0] $end - $var wire 32 N vlCoverageLineTrace_t_cover_line__166_else [31:0] $end + $var wire 32 N vlCoverageLineTrace_t_cover_line__162_if [31:0] $end + $var wire 32 O vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $upscope $end $scope module b2 $end $var wire 1 W clk $end $var wire 1 % toggle $end - $var wire 32 T vlCoverageLineTrace_t_cover_line__156_block [31:0] $end - $var wire 32 P vlCoverageLineTrace_t_cover_line__158_else [31:0] $end + $var wire 32 P vlCoverageLineTrace_t_cover_line__156_block [31:0] $end + $var wire 32 Q vlCoverageLineTrace_t_cover_line__158_else [31:0] $end $var wire 32 c vlCoverageLineTrace_t_cover_line__158_if [31:0] $end $var wire 32 R vlCoverageLineTrace_t_cover_line__162_else [31:0] $end - $var wire 32 Q vlCoverageLineTrace_t_cover_line__162_if [31:0] $end - $var wire 32 S vlCoverageLineTrace_t_cover_line__166_else [31:0] $end + $var wire 32 S vlCoverageLineTrace_t_cover_line__162_if [31:0] $end + $var wire 32 T vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $upscope $end $scope module o1 $end $var wire 1 W clk $end $var wire 1 % toggle $end - $var wire 32 J vlCoverageLineTrace_t_cover_line__220_block [31:0] $end - $var wire 32 I vlCoverageLineTrace_t_cover_line__221_else [31:0] $end - $var wire 32 H vlCoverageLineTrace_t_cover_line__221_if [31:0] $end - $var wire 32 G vlCoverageLineTrace_t_cover_line__224_else [31:0] $end + $var wire 32 G vlCoverageLineTrace_t_cover_line__220_block [31:0] $end + $var wire 32 H vlCoverageLineTrace_t_cover_line__221_else [31:0] $end + $var wire 32 I vlCoverageLineTrace_t_cover_line__221_if [31:0] $end + $var wire 32 J vlCoverageLineTrace_t_cover_line__224_else [31:0] $end $var wire 32 a vlCoverageLineTrace_t_cover_line__224_if [31:0] $end $upscope $end $scope module t1 $end $var wire 1 W clk $end $var wire 1 % toggle $end $var wire 32 U vlCoverageLineTrace_t_cover_line__187_block [31:0] $end - $var wire 32 \ vlCoverageLineTrace_t_cover_line__191_block [31:0] $end + $var wire 32 Y vlCoverageLineTrace_t_cover_line__191_block [31:0] $end $var wire 32 Z vlCoverageLineTrace_t_cover_line__194_else [31:0] $end - $var wire 32 Y vlCoverageLineTrace_t_cover_line__194_if [31:0] $end + $var wire 32 [ vlCoverageLineTrace_t_cover_line__194_if [31:0] $end $var wire 32 V vlCoverageLineTrace_t_cover_line__197_else [31:0] $end - $var wire 32 [ vlCoverageLineTrace_t_cover_line__197_if [31:0] $end + $var wire 32 \ vlCoverageLineTrace_t_cover_line__197_if [31:0] $end $upscope $end $upscope $end $upscope $end @@ -169,7 +168,8 @@ b00000000000000000000000000000000 c #10 b00000000000000000000000000000010 & b00000010 ' -b00000000000000000000000000000001 ) +b00000000000000000000000000000001 ( +b00000000000000000000000000000001 * b00000000000000000000000000000001 + b00000000000000000000000000000001 - b00000000000000000000000000000001 / @@ -177,35 +177,35 @@ b00000000000000000000000000000001 1 b00000000000000000000000000000001 3 b00000000000000000000000000000001 5 b00000000000000000000000000000001 9 -b00000000000000000000000000000001 < -b00000000000000000000000000000001 > +b00000000000000000000000000000001 = +b00000000000000000000000000000001 ? b00000000000000000000000000000001 @ -b00000000000000000000000000000001 A b00000000000000000000000000000001 B +b00000000000000000000000000000001 C b00000000000000000000000000000001 D -b00000000000000000000000000000001 E b00000000000000000000000000000001 F -b00000000000000000000000000000001 I -b00000000000000000000000000000001 J +b00000000000000000000000000000001 G +b00000000000000000000000000000001 H b00000000000000000000000000000001 K +b00000000000000000000000000000001 L b00000000000000000000000000000001 M -b00000000000000000000000000000001 N b00000000000000000000000000000001 O b00000000000000000000000000000001 P +b00000000000000000000000000000001 Q b00000000000000000000000000000001 R -b00000000000000000000000000000001 S b00000000000000000000000000000001 T b00000000000000000000000000000001 U b00000000000000000000000000000001 V 1W +b00000000000000000000000000000001 Y b00000000000000000000000000000001 Z -b00000000000000000000000000000001 \ #15 0W #20 b00000000000000000000000000000011 & b00000011 ' -b00000000000000000000000000000010 ) +b00000000000000000000000000000010 ( +b00000000000000000000000000000010 * b00000000000000000000000000000010 + b00000000000000000000000000000010 - b00000000000000000000000000000010 / @@ -213,315 +213,314 @@ b00000000000000000000000000000010 1 b00000000000000000000000000000010 3 b00000000000000000000000000000010 5 b00000000000000000000000000000010 9 -b00000000000000000000000000000010 < -b00000000000000000000000000000010 > +b00000000000000000000000000000010 = +b00000000000000000000000000000010 ? b00000000000000000000000000000010 @ -b00000000000000000000000000000010 A b00000000000000000000000000000010 B +b00000000000000000000000000000010 C b00000000000000000000000000000010 D -b00000000000000000000000000000010 E b00000000000000000000000000000010 F -b00000000000000000000000000000010 I -b00000000000000000000000000000010 J +b00000000000000000000000000000010 G +b00000000000000000000000000000010 H b00000000000000000000000000000010 K +b00000000000000000000000000000010 L b00000000000000000000000000000010 M -b00000000000000000000000000000010 N b00000000000000000000000000000010 O b00000000000000000000000000000010 P +b00000000000000000000000000000010 Q b00000000000000000000000000000010 R -b00000000000000000000000000000010 S b00000000000000000000000000000010 T b00000000000000000000000000000010 U b00000000000000000000000000000010 V 1W +b00000000000000000000000000000010 Y b00000000000000000000000000000010 Z -b00000000000000000000000000000010 \ #25 0W #30 1% b00000000000000000000000000000100 & b00000100 ' -b00000000000000000000000000000001 ( -b00000000000000000000000000000001 * +b00000000000000000000000000000011 ( +b00000000000000000000000000000011 * b00000000000000000000000000000001 , b00000000000000000000000000000001 . b00000000000000000000000000000001 0 b00000000000000000000000000000001 2 +b00000000000000000000000000000001 4 +b00000000000000000000000000000001 6 b00000000000000000000000000000001 7 b00000000000000000000000000000001 ; -b00000000000000000000000000000011 < -b00000000000000000000000000000011 > +b00000000000000000000000000000011 ? b00000000000000000000000000000011 @ -b00000000000000000000000000000011 A b00000000000000000000000000000011 B +b00000000000000000000000000000011 C b00000000000000000000000000000011 D -b00000000000000000000000000000011 E b00000000000000000000000000000011 F -b00000000000000000000000000000011 I -b00000000000000000000000000000011 J +b00000000000000000000000000000011 G +b00000000000000000000000000000011 H b00000000000000000000000000000011 K +b00000000000000000000000000000011 L b00000000000000000000000000000011 M -b00000000000000000000000000000011 N b00000000000000000000000000000011 O b00000000000000000000000000000011 P +b00000000000000000000000000000011 Q b00000000000000000000000000000011 R -b00000000000000000000000000000011 S b00000000000000000000000000000011 T b00000000000000000000000000000011 U b00000000000000000000000000000011 V 1W +b00000000000000000000000000000011 Y b00000000000000000000000000000011 Z -b00000000000000000000000000000011 \ #35 0W #40 0% b00000000000000000000000000000101 & b00000101 ' -b00000000000000000000000000000011 ) +b00000000000000000000000000000100 ( +b00000000000000000000000000000100 * b00000000000000000000000000000011 + b00000000000000000000000000000011 - b00000000000000000000000000000011 / b00000000000000000000000000000011 1 b00000000000000000000000000000011 3 -b00000000000000000000000000000001 6 -b00000000000000000000000000000011 9 -b00000000000000000000000000000100 < -b00000000000000000000000000000100 > -b00000000000000000000000000000001 ? -b00000000000000000000000000000100 B -b00000000000000000000000000000001 C -b00000000000000000000000000000100 F -b00000000000000000000000000000001 G -b00000000000000000000000000000001 H -b00000000000000000000000000000100 J +b00000000000000000000000000000011 5 +b00000000000000000000000000000001 8 +b00000000000000000000000000000011 = +b00000000000000000000000000000100 ? +b00000000000000000000000000000001 A +b00000000000000000000000000000100 C +b00000000000000000000000000000001 E +b00000000000000000000000000000100 G +b00000000000000000000000000000001 I +b00000000000000000000000000000001 J b00000000000000000000000000000100 K -b00000000000000000000000000000001 L -b00000000000000000000000000000100 O +b00000000000000000000000000000100 L +b00000000000000000000000000000001 N b00000000000000000000000000000100 P -b00000000000000000000000000000001 Q -b00000000000000000000000000000100 T +b00000000000000000000000000000100 Q +b00000000000000000000000000000001 S b00000000000000000000000000000100 U b00000000000000000000000000000100 V 1W -b00000000000000000000000000000001 Y -b00000000000000000000000000000100 \ +b00000000000000000000000000000100 Y +b00000000000000000000000000000001 [ #45 0W #50 b00000000000000000000000000000110 & b00000110 ' -b00000000000000000000000000000100 ) +b00000000000000000000000000000101 ( +b00000000000000000000000000000101 * b00000000000000000000000000000100 + b00000000000000000000000000000100 - b00000000000000000000000000000100 / b00000000000000000000000000000100 1 b00000000000000000000000000000100 3 -b00000000000000000000000000000001 4 +b00000000000000000000000000000100 5 b00000000000000000000000000000001 : -b00000000000000000000000000000101 < -b00000000000000000000000000000101 > +b00000000000000000000000000000001 < +b00000000000000000000000000000101 ? b00000000000000000000000000000100 @ -b00000000000000000000000000000100 A -b00000000000000000000000000000101 B +b00000000000000000000000000000100 B +b00000000000000000000000000000101 C b00000000000000000000000000000100 D -b00000000000000000000000000000100 E -b00000000000000000000000000000101 F -b00000000000000000000000000000100 I -b00000000000000000000000000000101 J +b00000000000000000000000000000100 F +b00000000000000000000000000000101 G +b00000000000000000000000000000100 H b00000000000000000000000000000101 K +b00000000000000000000000000000101 L b00000000000000000000000000000100 M -b00000000000000000000000000000100 N -b00000000000000000000000000000101 O +b00000000000000000000000000000100 O b00000000000000000000000000000101 P +b00000000000000000000000000000101 Q b00000000000000000000000000000100 R -b00000000000000000000000000000100 S -b00000000000000000000000000000101 T +b00000000000000000000000000000100 T b00000000000000000000000000000101 U b00000000000000000000000000000101 V 1W b00000000000000000000000000000001 X +b00000000000000000000000000000110 Y b00000000000000000000000000000101 Z -b00000000000000000000000000000001 [ -b00000000000000000000000000000110 \ +b00000000000000000000000000000001 \ #55 0W #60 b00000000000000000000000000000111 & b00000111 ' -b00000000000000000000000000000101 ) +b00000000000000000000000000000110 ( +b00000000000000000000000000000110 * b00000000000000000000000000000101 + b00000000000000000000000000000101 - b00000000000000000000000000000101 / b00000000000000000000000000000101 1 b00000000000000000000000000000101 3 -b00000000000000000000000000000011 5 -b00000000000000000000000000000100 9 -b00000000000000000000000000000110 < -b00000000000000000000000000000110 > +b00000000000000000000000000000101 5 +b00000000000000000000000000000011 9 +b00000000000000000000000000000100 = +b00000000000000000000000000000110 ? b00000000000000000000000000000101 @ -b00000000000000000000000000000101 A -b00000000000000000000000000000110 B +b00000000000000000000000000000101 B +b00000000000000000000000000000110 C b00000000000000000000000000000101 D -b00000000000000000000000000000101 E -b00000000000000000000000000000110 F -b00000000000000000000000000000101 I -b00000000000000000000000000000110 J +b00000000000000000000000000000101 F +b00000000000000000000000000000110 G +b00000000000000000000000000000101 H b00000000000000000000000000000110 K +b00000000000000000000000000000110 L b00000000000000000000000000000101 M -b00000000000000000000000000000101 N -b00000000000000000000000000000110 O +b00000000000000000000000000000101 O b00000000000000000000000000000110 P +b00000000000000000000000000000110 Q b00000000000000000000000000000101 R -b00000000000000000000000000000101 S -b00000000000000000000000000000110 T +b00000000000000000000000000000101 T b00000000000000000000000000000110 U b00000000000000000000000000000110 V 1W +b00000000000000000000000000000111 Y b00000000000000000000000000000110 Z -b00000000000000000000000000000111 \ #65 0W #70 b00000000000000000000000000001000 & b00001000 ' -b00000000000000000000000000000110 ) +b00000000000000000000000000000111 ( +b00000000000000000000000000000111 * b00000000000000000000000000000110 + b00000000000000000000000000000110 - b00000000000000000000000000000110 / b00000000000000000000000000000110 1 b00000000000000000000000000000110 3 -b00000000000000000000000000000100 5 -b00000000000000000000000000000101 9 -b00000000000000000000000000000111 < -b00000000000000000000000000000111 > +b00000000000000000000000000000110 5 +b00000000000000000000000000000100 9 +b00000000000000000000000000000101 = +b00000000000000000000000000000111 ? b00000000000000000000000000000110 @ -b00000000000000000000000000000110 A -b00000000000000000000000000000111 B +b00000000000000000000000000000110 B +b00000000000000000000000000000111 C b00000000000000000000000000000110 D -b00000000000000000000000000000110 E -b00000000000000000000000000000111 F -b00000000000000000000000000000110 I -b00000000000000000000000000000111 J +b00000000000000000000000000000110 F +b00000000000000000000000000000111 G +b00000000000000000000000000000110 H b00000000000000000000000000000111 K +b00000000000000000000000000000111 L b00000000000000000000000000000110 M -b00000000000000000000000000000110 N -b00000000000000000000000000000111 O +b00000000000000000000000000000110 O b00000000000000000000000000000111 P +b00000000000000000000000000000111 Q b00000000000000000000000000000110 R -b00000000000000000000000000000110 S -b00000000000000000000000000000111 T +b00000000000000000000000000000110 T b00000000000000000000000000000111 U b00000000000000000000000000000111 V 1W +b00000000000000000000000000001000 Y b00000000000000000000000000000111 Z -b00000000000000000000000000001000 \ #75 0W #80 b00000000000000000000000000001001 & b00001001 ' -b00000000000000000000000000000111 ) +b00000000000000000000000000001000 ( +b00000000000000000000000000001000 * b00000000000000000000000000000111 + b00000000000000000000000000000111 - b00000000000000000000000000000111 / b00000000000000000000000000000111 1 b00000000000000000000000000000111 3 -b00000000000000000000000000000101 5 -b00000000000000000000000000000110 9 -b00000000000000000000000000001000 < -b00000000000000000000000000001000 > +b00000000000000000000000000000111 5 +b00000000000000000000000000000101 9 +b00000000000000000000000000000110 = +b00000000000000000000000000001000 ? b00000000000000000000000000000111 @ -b00000000000000000000000000000111 A -b00000000000000000000000000001000 B +b00000000000000000000000000000111 B +b00000000000000000000000000001000 C b00000000000000000000000000000111 D -b00000000000000000000000000000111 E -b00000000000000000000000000001000 F -b00000000000000000000000000000111 I -b00000000000000000000000000001000 J +b00000000000000000000000000000111 F +b00000000000000000000000000001000 G +b00000000000000000000000000000111 H b00000000000000000000000000001000 K +b00000000000000000000000000001000 L b00000000000000000000000000000111 M -b00000000000000000000000000000111 N -b00000000000000000000000000001000 O +b00000000000000000000000000000111 O b00000000000000000000000000001000 P +b00000000000000000000000000001000 Q b00000000000000000000000000000111 R -b00000000000000000000000000000111 S -b00000000000000000000000000001000 T +b00000000000000000000000000000111 T b00000000000000000000000000001000 U b00000000000000000000000000001000 V 1W +b00000000000000000000000000001001 Y b00000000000000000000000000001000 Z -b00000000000000000000000000001001 \ #85 0W #90 b00000000000000000000000000001010 & b00001010 ' -b00000000000000000000000000001000 ) +b00000000000000000000000000001001 ( +b00000000000000000000000000001001 * b00000000000000000000000000001000 + b00000000000000000000000000001000 - b00000000000000000000000000001000 / b00000000000000000000000000001000 1 b00000000000000000000000000001000 3 -b00000000000000000000000000000110 5 -b00000000000000000000000000000111 9 -b00000000000000000000000000001001 < -b00000000000000000000000000001001 > +b00000000000000000000000000001000 5 +b00000000000000000000000000000110 9 +b00000000000000000000000000000111 = +b00000000000000000000000000001001 ? b00000000000000000000000000001000 @ -b00000000000000000000000000001000 A -b00000000000000000000000000001001 B +b00000000000000000000000000001000 B +b00000000000000000000000000001001 C b00000000000000000000000000001000 D -b00000000000000000000000000001000 E -b00000000000000000000000000001001 F -b00000000000000000000000000001000 I -b00000000000000000000000000001001 J +b00000000000000000000000000001000 F +b00000000000000000000000000001001 G +b00000000000000000000000000001000 H b00000000000000000000000000001001 K +b00000000000000000000000000001001 L b00000000000000000000000000001000 M -b00000000000000000000000000001000 N -b00000000000000000000000000001001 O +b00000000000000000000000000001000 O b00000000000000000000000000001001 P +b00000000000000000000000000001001 Q b00000000000000000000000000001000 R -b00000000000000000000000000001000 S -b00000000000000000000000000001001 T +b00000000000000000000000000001000 T b00000000000000000000000000001001 U b00000000000000000000000000001001 V 1W +b00000000000000000000000000001010 Y b00000000000000000000000000001001 Z -b00000000000000000000000000001010 \ #95 0W #100 b00000000000000000000000000001011 & b00001011 ' -b00000000000000000000000000001001 ) +b00000000000000000000000000001010 ( +b00000000000000000000000000001010 * b00000000000000000000000000001001 + b00000000000000000000000000001001 - b00000000000000000000000000001001 / b00000000000000000000000000001001 1 b00000000000000000000000000001001 3 -b00000000000000000000000000000111 5 -b00000000000000000000000000000001 8 -b00000000000000000000000000001010 < -b00000000000000000000000000001010 > +b00000000000000000000000000001001 5 +b00000000000000000000000000000111 9 +b00000000000000000000000000000001 > +b00000000000000000000000000001010 ? b00000000000000000000000000001001 @ -b00000000000000000000000000001001 A -b00000000000000000000000000001010 B +b00000000000000000000000000001001 B +b00000000000000000000000000001010 C b00000000000000000000000000001001 D -b00000000000000000000000000001001 E -b00000000000000000000000000001010 F -b00000000000000000000000000001001 I -b00000000000000000000000000001010 J +b00000000000000000000000000001001 F +b00000000000000000000000000001010 G +b00000000000000000000000000001001 H b00000000000000000000000000001010 K +b00000000000000000000000000001010 L b00000000000000000000000000001001 M -b00000000000000000000000000001001 N -b00000000000000000000000000001010 O +b00000000000000000000000000001001 O b00000000000000000000000000001010 P +b00000000000000000000000000001010 Q b00000000000000000000000000001001 R -b00000000000000000000000000001001 S -b00000000000000000000000000001010 T +b00000000000000000000000000001001 T b00000000000000000000000000001010 U b00000000000000000000000000001010 V 1W +b00000000000000000000000000001011 Y b00000000000000000000000000001010 Z -b00000000000000000000000000001011 \ diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out index c7b2e8201..75c4736a9 100644 --- a/test_regress/t/t_debug_emitv.out +++ b/test_regress/t/t_debug_emitv.out @@ -1,246 +1,378 @@ -module Vt_debug_emitv___024root; +module Vt_debug_emitv_t; input logic clk; input logic in; - signed int [31:0] t.array[0:2]; - logic [15:0] t.pubflat; - logic [15:0] t.pubflat_r; - signed int [31:0] t.fd; - signed int [31:0] t.i; - signed int [31:0] t.cyc; - signed int [31:0] t.fo; - signed int [31:0] t.sum; - signed real t.r; - string t.str; - signed int [31:0] t._Vpast_0_0; - signed int [31:0] t._Vpast_1_0; - signed int [31:0] t.unnamedblk3.i; - @(*)@([settle])@([initial])@(posedge clk)@(negedge - clk)always @( - *)@( - [settle])@( - [initial])@( - posedge - clk)@( - negedge - clk) begin - $display("stmt"); - end - always @([settle])@([initial])@(posedge clk)@(negedge - clk) begin - $display("stmt"); - end - initial begin - // Function: f - $write("stmt\nstmt 0 99\n"); - // Function: t - $display("stmt"); - // Function: f - $write("stmt\nstmt 1 -1\n"); - // Function: t - $display("stmt"); - // Function: f - $display("stmt"); - $display("stmt 2 -2"); - // Function: t - $display("stmt"); - $display("stmt"); - end + typedef + ???? // ENUMDTYPE 't.e_t' - ???? // CFUNC '_final_TOP' - $display("stmt"); - always @(posedge clk)@(negedge clk) begin - $display("posedge clk"); + ???? // ENUMITEM 'ZERO' + 32'h0 + ???? // ENUMITEM 'ONE' + 'sh1 + ???? // REFDTYPE 'e_t' + struct packed + { + ???? // REFDTYPE 'e_t' + a}signed logic [2:0] struct + {signed logic [2:0] a}logicunion + {logic a} + ???? // REFDTYPE 'ps_t' + bit [31:0] const + ???? // REFDTYPE 'ps_t' + const + ???? // REFDTYPE 'ps_t' + [0:2] + ???? // REFDTYPE 'us_t' + + ???? // REFDTYPE 'union_t' + signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0] + ???? // QUEUEDTYPE + signed int [31:0] string + ???? // ASSOCARRAYDTYPE + signed int [31:0] + ???? // UNSIZEDARRAYDTYPE + + ???? // DYNARRAYDTYPE + signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] e_t; + typedef struct packed + { + ???? // REFDTYPE 'e_t' + a}signed logic [2:0] struct + {signed logic [2:0] a}logicunion + {logic a} + ???? // REFDTYPE 'ps_t' + bit [31:0] const + ???? // REFDTYPE 'ps_t' + const + ???? // REFDTYPE 'ps_t' + [0:2] + ???? // REFDTYPE 'us_t' + + ???? // REFDTYPE 'union_t' + signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0] + ???? // QUEUEDTYPE + signed int [31:0] string + ???? // ASSOCARRAYDTYPE + signed int [31:0] + ???? // UNSIZEDARRAYDTYPE + + ???? // DYNARRAYDTYPE + signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] ps_t; + typedef struct + {signed logic [2:0] a}logicunion + {logic a} + ???? // REFDTYPE 'ps_t' + bit [31:0] const + ???? // REFDTYPE 'ps_t' + const + ???? // REFDTYPE 'ps_t' + [0:2] + ???? // REFDTYPE 'us_t' + + ???? // REFDTYPE 'union_t' + signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0] + ???? // QUEUEDTYPE + signed int [31:0] string + ???? // ASSOCARRAYDTYPE + signed int [31:0] + ???? // UNSIZEDARRAYDTYPE + + ???? // DYNARRAYDTYPE + signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] us_t; + typedef union + {logic a} + ???? // REFDTYPE 'ps_t' + bit [31:0] const + ???? // REFDTYPE 'ps_t' + const + ???? // REFDTYPE 'ps_t' + [0:2] + ???? // REFDTYPE 'us_t' + + ???? // REFDTYPE 'union_t' + signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0] + ???? // QUEUEDTYPE + signed int [31:0] string + ???? // ASSOCARRAYDTYPE + signed int [31:0] + ???? // UNSIZEDARRAYDTYPE + + ???? // DYNARRAYDTYPE + signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] union_t; + struct packed + { + ???? // REFDTYPE 'e_t' + a} ps[0:2]; + struct + {signed logic [2:0] a} us; + union + {logic a} unu; + signed int [31:0] array[0:2]; + initial begin + array = '{0:32'sh1, 1:32'sh2, 2:32'sh3}; end - always @(posedge clk)@(negedge clk) begin - __Vdly__t.pubflat_r <= t.pubflat; + logic [15:0] pubflat; + logic [15:0] pubflat_r; + logic [15:0] pubflat_w; + assign pubflat_w = pubflat; + signed int [31:0] fd; + signed int [31:0] i; + + ???? // QUEUEDTYPE + q; + + ???? // ASSOCARRAYDTYPE + assoc; + + ???? // DYNARRAYDTYPE + dyn; + task t; + $display("stmt"); + endtask + function f; + input signed int [31:0] v; + begin : label0 + $display("stmt"); + f = ((v == 'sh0) ? 'sh63 : ((~ v) + 'sh1)); + disable label0; + end + endfunction + initial begin + begin : unnamedblk1 + signed int [31:0] other; + begin + begin : unnamedblk2 + signed int [31:0] i; + i = 'sh0; + while ((i < 'sh3)) begin + begin + other = f(i); + $display("stmt %~ %~", + iother, other); + t()end + i = (i + 'h1); + end + end + end + begin : named + $display("stmt"); + end + end end - always @(posedge clk)@(negedge clk) begin - __Vdly__t.cyc <= (32'sh1 + t.cyc); - __Vdly__t.r <= (0.01 + t.r); - t.fo = t.cyc; - // Function: inc - __Vtask_t.sub.inc__2__i = t.fo; - __Vtask_t.sub.inc__2__o = (32'h1 + __Vtask_t.sub.inc__2__i[31:1]); - t.sum = __Vtask_t.sub.inc__2__o; - // Function: f - __Vfunc_t.sub.f__3__v = t.sum; + final begin + begin + $display("stmt"); + end + end + always @([any] in) begin + begin + $display("stmt"); + end + end + always @(posedge clk) begin + begin + $display("posedge clk"); + pubflat_r <= pubflat_w; + end + end + always @(negedge clk) begin + begin + $display("negedge clk, pfr = %x", pubflat_r); + end + end + signed int [31:0] cyc; + signed int [31:0] fo; + signed int [31:0] sum; + signed real r; + string str; + always @(posedge clk) begin + begin + cyc <= (cyc + 'sh1); + r <= (r + 0.01); + fo = cyc; + sub.inc(fosum)sum = sub.f(sum); + $display("[%0t] sum = %~", $timesum, sum); + $display("a?= %d", ($c('sh1) ? $c('sh14) + : $c('sh1e))); + $c(;); + $display("%d", $c(0)); + $fopen(72'h2f6465762f6e756c6c); + $fclose(fd); + $fopen(72'h2f6465762f6e756c6c, 8'h72); + $fgetc(fd); + $fflush(fd); + $fscanf(fd, "%d", sum); + ; + $fdisplay(32'h69203d20, "%~", sum); + $fwrite(fd, "hello"); + $readmemh(fd, array); + $readmemh(fd, array, 'sh0); + $readmemh(fd, array, 'sh0, 'sh0); + sum = 'sh0; + begin : unnamedblk3 + signed int [31:0] i; + i = 'sh0; + begin : label0 + while ((i < cyc)) begin + begin + sum = (sum + i); + if ((sum > 'sha)) begin + disable label0; + end + else begin + sum = (sum + 'sh1); + end + end + i = (i + 'h1); + end + end + end + if ((cyc == 'sh63)) begin + $finish; + end + if ((cyc == 'sh64)) begin + $stop; + end + case (in) + 'sh1: begin $display("1"); + end + default: begin $display("default"); + end + endcase + priority case (in) + 'sh1: begin $display("1"); + end + default: begin $display("default"); + end + endcase + unique case (in) + 'sh1: begin $display("1"); + end + default: begin $display("default"); + end + endcase + unique0 case (in) + 'sh1: begin $display("1"); + end + default: begin $display("default"); + end + endcase + if (in) begin + $display("1"); + end + else begin + $display("0"); + end + priority if (in) begin + $display("1"); + end + else begin + $display("0"); + end + unique if (in) begin + $display("1"); + end + else begin + $display("0"); + end + unique0 if (in) begin + $display("1"); + end + else begin + $display("0"); + end + $display("%~%~", $past(cyc)$past(cyc, 'sh1), + $past(cyc, 'sh1)); + str = $sformatf("cyc=%~", cyc); + ; + $display("str = %@", str); + $display("%% [%t] [%^] to=%o td=%d", $time + $realtime$time$time, $realtime + $time$time, $time$time, $time); + $sscanf(40'h666f6f3d35, "foo=%d", i); + ; + $printtimescale; + if ((i != 'sh5)) begin + $stop; + end + sum = + ???? // RAND + ; + sum = + ???? // RAND + 'sha; + sum = + ???? // RAND + ; + sum = + ???? // RAND + 'sha; + if ((PKG_PARAM != 'sh1)) begin + $stop; + end + sub.r = 62; + $display("%g", $log10(r)); + $display("%g", $ln(r)); + $display("%g", $exp(r)); + $display("%g", $sqrt(r)); + $display("%g", $floor(r)); + $display("%g", $ceil(r)); + $display("%g", $sin(r)); + $display("%g", $cos(r)); + $display("%g", $tan(r)); + $display("%g", $asin(r)); + $display("%g", $acos(r)); + $display("%g", $atan(r)); + $display("%g", $sinh(r)); + $display("%g", $cosh(r)); + $display("%g", $tanh(r)); + $display("%g", $asinh(r)); + $display("%g", $acosh(r)); + $display("%g", $atanh(r)); + force sum = 'sha; + __Vrepeat0 = 'sh2; + while ((__Vrepeat0 > 32'h0)) begin + if ((sum != 'sha)) begin + $stop; + end + __Vrepeat0 = (__Vrepeat0 - 32'h1); + end + release sum; + end + end + /*verilator public_flat_rw @(posedge clk) pubflat*/ + signed integer [31:0] __Vrepeat0; +endmodule +package Vt_debug_emitv___024unit; + class Vt_debug_emitv_Cls; + signed int [31:0] member; + member = 'sh1; + task method; + endtask + task new; + endtask + endclass +endpackage +module Vt_debug_emitv_sub; + task inc; + input signed int [31:0] i; + output signed int [31:0] o; + o = ({32'h1{{1'h0, i[31:1]}}} + 32'h1); + endtask + function f; + input signed int [31:0] v; begin : label0 begin : label0 - if ((32'sh0 == __Vfunc_t.sub.f__3__v)) begin - __Vfunc_t.sub.f__3__Vfuncout = 32'sh21; + if ((v == 'sh0)) begin + f = 'sh21; disable label0; end - __Vfunc_t.sub.f__3__Vfuncout = (32'h1 - + __Vfunc_t.sub.f__3__v[2]); + f = ({32'h1{{31'h0, v[2]}}} + 32'h1); disable label0; end end - t.sum = __Vfunc_t.sub.f__3__Vfuncout; - $display("[%0t] sum = %~", $timet.sum, t.sum); - $display("a?= %d", ($c(32'sh1) ? $c(32'sh14) - : $c(32'sh1e))); - $c(;); - $display("%d", $c(0)); - $fopen(72'h2f6465762f6e756c6c); - $fclose(t.fd); - $fopen(72'h2f6465762f6e756c6c, 8'h72); - $fgetc(t.fd); - $fflush(t.fd); - $fscanf(t.fd, "%d", t.sum); - ; - $fdisplay(32'h69203d20, "%~", t.sum); - $fwrite(t.fd, "hello"); - $readmemh(t.fd, t.array); - $readmemh(t.fd, t.array, 32'sh0); - $readmemh(t.fd, t.array, 32'sh0, 32'sh0); - t.sum = 32'sh0; - t.unnamedblk3.i = 32'sh0; - begin : label0 - while ((t.unnamedblk3.i < t.cyc)) begin - t.sum = (t.sum + t.unnamedblk3.i); - if ((32'sha < t.sum)) begin - disable label0; - end - else begin - t.sum = (32'sh1 + t.sum); - end - t.unnamedblk3.i = (32'h1 + t.unnamedblk3.i); - end - end - if ((32'sh63 == t.cyc)) begin - $finish; - end - if ((32'sh64 == t.cyc)) begin - $stop; - end - if (in) begin - $display("1"); - end - else begin - $display("default"); - end - if (in) begin - $display("1"); - end - else begin - $display("default"); - end - if (in) begin - $display("1"); - end - else begin - $display("default"); - end - if (in) begin - $display("1"); - end - else begin - $display("default"); - end - if (in) begin - $display("1"); - end - else begin - $display("0"); - end - priority if (in) begin - $display("1"); - end - else begin - $display("0"); - end - unique if (in) begin - $display("1"); - end - else begin - $display("0"); - end - unique0 if (in) begin - $display("1"); - end - else begin - $display("0"); - end - $display("%~%~", t._Vpast_0_0t._Vpast_1_0, - t._Vpast_1_0); - t.str = $sformatf("cyc=%~", t.cyc); - ; - $display("str = %@", t.str); - $display("%% [%t] [%^] to=%o td=%d", $time$realtime - $time$time, $realtime$time$time, $time - $time, $time); - $sscanf(40'h666f6f3d35, "foo=%d", t.i); - ; - $printtimescale; - if ((32'sh5 != t.i)) begin - $stop; - end - t.sum = - ???? // RAND - 32'sha; - $display("%g", $log10(t.r)); - $display("%g", $ln(t.r)); - $display("%g", $exp(t.r)); - $display("%g", $sqrt(t.r)); - $display("%g", $floor(t.r)); - $display("%g", $ceil(t.r)); - $display("%g", $sin(t.r)); - $display("%g", $cos(t.r)); - $display("%g", $tan(t.r)); - $display("%g", $asin(t.r)); - $display("%g", $acos(t.r)); - $display("%g", $atan(t.r)); - $display("%g", $sinh(t.r)); - $display("%g", $cosh(t.r)); - $display("%g", $tanh(t.r)); - $display("%g", $asinh(t.r)); - $display("%g", $acosh(t.r)); - $display("%g", $atanh(t.r)); - end - /*verilator public_flat_rw @(posedge clk)@(negedge - clk) t.pubflat*/ - always @(posedge clk)@(negedge clk) begin - __Vdly__t._Vpast_0_0 <= t.cyc; - end - always @(posedge clk)@(negedge clk) begin - __Vdly__t._Vpast_1_0 <= t.cyc; - end - __Vdly__t._Vpast_1_0 = t._Vpast_1_0; - t._Vpast_1_0 = __Vdly__t._Vpast_1_0; - __Vdly__t._Vpast_0_0 = t._Vpast_0_0; - t._Vpast_0_0 = __Vdly__t._Vpast_0_0; - __Vdly__t.r = t.r; - t.r = __Vdly__t.r; - __Vdly__t.cyc = t.cyc; - t.cyc = __Vdly__t.cyc; - __Vdly__t.pubflat_r = t.pubflat_r; - t.pubflat_r = __Vdly__t.pubflat_r; - always @(negedge clk) begin - $display("negedge clk, pfr = %x", t.pubflat_r); - end - signed int [31:0] __Vtask_t.sub.inc__2__i; - signed int [31:0] __Vtask_t.sub.inc__2__o; - signed int [31:0] __Vfunc_t.sub.f__3__Vfuncout; - signed int [31:0] __Vfunc_t.sub.f__3__v; - logic [15:0] __Vdly__t.pubflat_r; - signed int [31:0] __Vdly__t.cyc; - signed real __Vdly__t.r; - signed int [31:0] __Vdly__t._Vpast_0_0; - signed int [31:0] __Vdly__t._Vpast_1_0; + endfunction + signed real r; endmodule -package Vt_debug_emitv___024unit; -endpackage package Vt_debug_emitv_Pkg; + signed logic [31:0] PKG_PARAM; endpackage -class Vt_debug_emitv___024unit__03a__03aCls; -signed int [31:0] member; - -???? // CFUNC '__VnoInFunc_method' - -???? // CFUNC 'new' -$_CSTMT(_ctor_var_reset(vlSymsp); -); -$unit::Cls.member = 32'sh1; -endclass -/*class*/package Vt_debug_emitv___024unit__03a__03aCls__Vclpkg; -end/*class*/package diff --git a/test_regress/t/t_debug_emitv.pl b/test_regress/t/t_debug_emitv.pl index 06a25f291..863c22c75 100755 --- a/test_regress/t/t_debug_emitv.pl +++ b/test_regress/t/t_debug_emitv.pl @@ -16,7 +16,7 @@ lint( v_flags => ["--lint-only --dump-treei 9 --dump-treei-V3EmitV 9 --debug-emitv"], ); -files_identical("$Self->{obj_dir}/$Self->{VM_PREFIX}__preorder.v", $Self->{golden_filename}); +files_identical(glob_one("$Self->{obj_dir}/$Self->{VM_PREFIX}_*_width.tree.v"), $Self->{golden_filename}); ok(1); 1; diff --git a/test_regress/t/t_debug_emitv.v b/test_regress/t/t_debug_emitv.v index f8ebe44ac..989888d8c 100644 --- a/test_regress/t/t_debug_emitv.v +++ b/test_regress/t/t_debug_emitv.v @@ -197,6 +197,10 @@ module t (/*AUTOARG*/ $display("%g", $asinh(r)); $display("%g", $acosh(r)); $display("%g", $atanh(r)); + + force sum = 10; + repeat (2) if (sum != 10) $stop; + release sum; end endmodule diff --git a/test_regress/t/t_dedupe_clk_gate.pl b/test_regress/t/t_dedupe_clk_gate.pl index c4a09eb65..ccc0816ac 100755 --- a/test_regress/t/t_dedupe_clk_gate.pl +++ b/test_regress/t/t_dedupe_clk_gate.pl @@ -17,7 +17,7 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 4); } diff --git a/test_regress/t/t_depth_flop.pl b/test_regress/t/t_depth_flop.pl new file mode 100755 index 000000000..dabf3116e --- /dev/null +++ b/test_regress/t/t_depth_flop.pl @@ -0,0 +1,18 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vltmt => 1); # Note issue shows up with --threads + +compile( + verilator_flags2 => ['--compiler clang --threads 2 -Wno-UNOPTTHREADS'], + ); + +ok(1); +1; diff --git a/test_regress/t/t_depth_flop.v b/test_regress/t/t_depth_flop.v new file mode 100644 index 000000000..f6aa674c0 --- /dev/null +++ b/test_regress/t/t_depth_flop.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Outputs + out, + // Inputs + clk_0, clk_1, clk_2, clk_3, clk_4, clk_5, clk_6, clk_7, clk_8, clk_9, clk_10, + clk_11, clk_12, clk_13, clk_14, clk_15, clk_16, clk_17, clk_18, clk_19, + rstn_0, rstn_1, rstn_2, rstn_3, rstn_4, rstn_5, rstn_6, rstn_7, rstn_8, + rstn_9, rstn_10, rstn_11, rstn_12, rstn_13, rstn_14, rstn_15, rstn_16, + rstn_17, rstn_18, rstn_19 + ); + + input clk_0; + input clk_1; + input clk_2; + input clk_3; + input clk_4; + input clk_5; + input clk_6; + input clk_7; + input clk_8; + input clk_9; + input clk_10; + input clk_11; + input clk_12; + input clk_13; + input clk_14; + input clk_15; + input clk_16; + input clk_17; + input clk_18; + input clk_19; + input rstn_0; + input rstn_1; + input rstn_2; + input rstn_3; + input rstn_4; + input rstn_5; + input rstn_6; + input rstn_7; + input rstn_8; + input rstn_9; + input rstn_10; + input rstn_11; + input rstn_12; + input rstn_13; + input rstn_14; + input rstn_15; + input rstn_16; + input rstn_17; + input rstn_18; + input rstn_19; + + // verilator lint_off MULTIDRIVEN + output reg out [0:29-1]; + + always_ff @(posedge clk_0, negedge rstn_0) if ((rstn_0 == 0)) out[0] <= 0; + always_ff @(posedge clk_1, negedge rstn_1) if ((rstn_1 == 0)) out[1] <= 0; + always_ff @(posedge clk_2, negedge rstn_2) if ((rstn_2 == 0)) out[2] <= 0; + always_ff @(posedge clk_3, negedge rstn_3) if ((rstn_3 == 0)) out[3] <= 0; + always_ff @(posedge clk_4, negedge rstn_4) if ((rstn_4 == 0)) out[4] <= 0; + always_ff @(posedge clk_5, negedge rstn_5) if ((rstn_5 == 0)) out[5] <= 0; + always_ff @(posedge clk_6, negedge rstn_6) if ((rstn_6 == 0)) out[6] <= 0; + always_ff @(posedge clk_7, negedge rstn_7) if ((rstn_7 == 0)) out[7] <= 0; + always_ff @(posedge clk_8, negedge rstn_8) if ((rstn_8 == 0)) out[8] <= 0; + always_ff @(posedge clk_9, negedge rstn_9) if ((rstn_9 == 0)) out[9] <= 0; + always_ff @(posedge clk_10, negedge rstn_10) if ((rstn_10 == 0)) out[10] <= 0; + always_ff @(posedge clk_11, negedge rstn_11) if ((rstn_11 == 0)) out[11] <= 0; + always_ff @(posedge clk_12, negedge rstn_12) if ((rstn_12 == 0)) out[12] <= 0; + always_ff @(posedge clk_13, negedge rstn_13) if ((rstn_13 == 0)) out[13] <= 0; + always_ff @(posedge clk_14, negedge rstn_14) if ((rstn_14 == 0)) out[14] <= 0; + always_ff @(posedge clk_15, negedge rstn_15) if ((rstn_15 == 0)) out[15] <= 0; + always_ff @(posedge clk_16, negedge rstn_16) if ((rstn_16 == 0)) out[16] <= 0; + always_ff @(posedge clk_17, negedge rstn_17) if ((rstn_17 == 0)) out[17] <= 0; + always_ff @(posedge clk_18, negedge rstn_18) if ((rstn_18 == 0)) out[18] <= 0; + always_ff @(posedge clk_19, negedge rstn_19) if ((rstn_19 == 0)) out[19] <= 0; + +endmodule diff --git a/test_regress/t/t_display_io.pl b/test_regress/t/t_display_io.pl new file mode 100755 index 000000000..2cb5eeaff --- /dev/null +++ b/test_regress/t/t_display_io.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_display_io.v b/test_regress/t/t_display_io.v new file mode 100644 index 000000000..d9315fb54 --- /dev/null +++ b/test_regress/t/t_display_io.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: $display() test for %l +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Outputs + o, + // Inputs + i + ); + + input logic [95:0] i; + output logic [95:0] o; + + string a_s; + + initial begin + o = ~i; + $sformat(a_s, "%h", i); + $display(a_s); + $sformat(a_s, "%h", o); + $display(a_s); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_dist_header_cc.pl b/test_regress/t/t_dist_header_cc.pl new file mode 100755 index 000000000..e51a12901 --- /dev/null +++ b/test_regress/t/t_dist_header_cc.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +use Cwd; + +scenarios(dist => 1); + +my $root = ".."; + +if (!-r "$root/.git") { + skip("Not in a git repository"); +} else { + run(cmd => ["cd $root/src/obj_dbg && $ENV{MAKE} -j 4 -k -f ../Makefile_obj VL_NOOPT=1 header_cc"], + check_finished => 0); +} + +ok(1); +1; diff --git a/test_regress/t/t_dist_portability.pl b/test_regress/t/t_dist_portability.pl index b436e5cb5..58b8a6e00 100755 --- a/test_regress/t/t_dist_portability.pl +++ b/test_regress/t/t_dist_portability.pl @@ -18,7 +18,6 @@ my $Debug; if (!-r "$root/.git") { skip("Not in a git repository"); } else { - uint(); printfll(); cstr(); vsnprintf(); @@ -27,31 +26,6 @@ if (!-r "$root/.git") { ok(1); -sub uint { - ### Must trim output before and after our file list - #my $files = "*/*.c* */*.h test_regress/t/*.c* test_regress/t/*.h"; - # src isn't clean, and probably doesn't need to be (yet?) - my $files = "include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h"; - my $cmd = "cd $root && fgrep -n int $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - $line =~ s!//.*$!!; - next if $line !~ /uint\d+_t\b/; - next if $line =~ /vl[su]int\d+_t/; - next if $line =~ /typedef/; - next if $line =~ m!include/svdpi.h!; # Not ours - if ($line =~ /^([^:]+)/) { - $names{$1} = 1; - print "$line\n"; - } - } - if (keys %names) { - error("Files with uint32*_t instead of vluint32s: ", join(' ', sort keys %names)); - } -} - sub printfll { my $files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h"; my $cmd = "cd $root && fgrep -n ll $files | sort"; @@ -69,7 +43,7 @@ sub printfll { } } if (keys %names) { - error("Files with %ll instead of VL_PRI64: ", join(' ', sort keys %names)); + error("Files with %ll instead of PRIx64: ", join(' ', sort keys %names)); } } diff --git a/test_regress/t/t_dpi_export_c.cpp b/test_regress/t/t_dpi_export_c.cpp index bcebfce0f..9493e4af6 100644 --- a/test_regress/t/t_dpi_export_c.cpp +++ b/test_regress/t/t_dpi_export_c.cpp @@ -9,31 +9,26 @@ // //************************************************************************* +#include +#include #include #include #include "svdpi.h" -// clang-format off -#ifdef _WIN32 -# define T_PRI64 "I64" -#else // Linux or compliant Unix flavors -# define T_PRI64 "ll" -#endif - //====================================================================== #if defined(VERILATOR) -# ifdef T_DPI_EXPORT_NOOPT -# include "Vt_dpi_export_noopt__Dpi.h" -# else -# include "Vt_dpi_export__Dpi.h" -# endif -#elif defined(VCS) -# include "../vc_hdrs.h" -#elif defined(CADENCE) -# define NEED_EXTERNS +#ifdef T_DPI_EXPORT_NOOPT +#include "Vt_dpi_export_noopt__Dpi.h" #else -# error "Unknown simulator for DPI test" +#include "Vt_dpi_export__Dpi.h" +#endif +#elif defined(VCS) +#include "../vc_hdrs.h" +#elif defined(CADENCE) +#define NEED_EXTERNS +#else +#error "Unknown simulator for DPI test" #endif // clang-format on @@ -73,11 +68,11 @@ extern void dpix_t_time(const svLogicVecVal* i, svLogicVecVal* o); #define CHECK_RESULT(type, got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d:", __FILE__, __LINE__); \ - union { type a; long long l; } u; \ + union { type a; uint64_t l; } u; \ u.l = 0; u.a = got; if (u.a) {/*used*/} \ - printf(" GOT = %" T_PRI64 "x", u.l); \ + printf(" GOT = %" PRIx64, u.l); \ u.l = 0; u.a = exp; if (u.a) {/*used*/} \ - printf(" EXP = %" T_PRI64 "x\n", u.l); \ + printf(" EXP = %" PRIx64 "\n", u.l); \ return __LINE__; \ } // clang-format on diff --git a/test_regress/t/t_dpi_var.pl b/test_regress/t/t_dpi_var.pl index 7f3485f5a..f96ebbdda 100755 --- a/test_regress/t/t_dpi_var.pl +++ b/test_regress/t/t_dpi_var.pl @@ -18,10 +18,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_dpi_var_vlt.pl b/test_regress/t/t_dpi_var_vlt.pl index 476882c77..10c8d696f 100755 --- a/test_regress/t/t_dpi_var_vlt.pl +++ b/test_regress/t/t_dpi_var_vlt.pl @@ -20,10 +20,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_dynarray.v b/test_regress/t/t_dynarray.v index 68fe7fb25..72eeb7246 100644 --- a/test_regress/t/t_dynarray.v +++ b/test_regress/t/t_dynarray.v @@ -133,6 +133,10 @@ module t (/*AUTOARG*/ `checkh(a[2], 3); `checkh(a[3], 4); + i = 0; + foreach (a[j]) i += int'(a[j]); + `checkh(i, 1 + 2 + 3 + 4); + // test wide dynamic array p256 = new [11]; `checkh(p256.size, 11); diff --git a/test_regress/t/t_enum_huge_methods.pl b/test_regress/t/t_enum_huge_methods.pl new file mode 100755 index 000000000..b46d46042 --- /dev/null +++ b/test_regress/t/t_enum_huge_methods.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_enum_huge_methods.v b/test_regress/t/t_enum_huge_methods.v new file mode 100644 index 000000000..3fd9eb1d6 --- /dev/null +++ b/test_regress/t/t_enum_huge_methods.v @@ -0,0 +1,73 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + typedef enum logic [59:0] { + E01 = 60'h1, + ELARGE = 60'h1234_4567_abcd + } my_t; + + integer cyc = 0; + my_t e; + + string all; + int i_cast; + + // Check runtime + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + e <= E01; + end + else if (cyc == 1) begin + `checks(e.name, "E01"); + `checkh(e.next, ELARGE); + e <= ELARGE; + end + else if (cyc == 3) begin + `checks(e.name, "ELARGE"); + `checkh(e.next, E01); + `checkh(e.prev, E01); + e <= E01; + end + // + else if (cyc == 10) begin + i_cast <= $cast(e, 60'h1234); + end + else if (cyc == 11) begin + `checkh(i_cast, 0); + i_cast <= $cast(e, 60'h1); + end + else if (cyc == 12) begin + `checkh(i_cast, 1); + i_cast <= $cast(e, 60'h1234_4567_abcd); + end + else if (cyc == 13) begin + `checkh(i_cast, 1); + end + // + else if (cyc == 20) begin + e <= my_t'('h11); // Unknown + end + else if (cyc == 21) begin + `checks(e.name, ""); // Unknown + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_enum_huge_methods_bad.out b/test_regress/t/t_enum_huge_methods_bad.out new file mode 100644 index 000000000..885a3cd7f --- /dev/null +++ b/test_regress/t/t_enum_huge_methods_bad.out @@ -0,0 +1,9 @@ +%Error: t/t_enum_huge_methods_bad.v:15:11: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd + 15 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:14: Unsupported: enum next/prev/name method on enum with > 64 bits + : ... In instance t + 30 | $display(e.name); + | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_enum_huge_methods_bad.pl b/test_regress/t/t_enum_huge_methods_bad.pl new file mode 100755 index 000000000..b5861b2ab --- /dev/null +++ b/test_regress/t/t_enum_huge_methods_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_enum_huge_methods_bad.v b/test_regress/t/t_enum_huge_methods_bad.v new file mode 100644 index 000000000..8502a98c0 --- /dev/null +++ b/test_regress/t/t_enum_huge_methods_bad.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + typedef enum logic [159:0] { + E01 = 160'h1, + ELARGE = 160'h1234_4567_abcd_1234_4567_abcd + } my_t; + + my_t e; + + int cyc; + + // Check runtime + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + e <= E01; + end + else if (cyc==1) begin + $display(e.name); + e <= ELARGE; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_enum_large_methods.v b/test_regress/t/t_enum_large_methods.v index bd9eb5da5..84255f66e 100644 --- a/test_regress/t/t_enum_large_methods.v +++ b/test_regress/t/t_enum_large_methods.v @@ -42,9 +42,9 @@ module t (/*AUTOARG*/ e <= E01; end else if (cyc==20) begin - e <= 'h11; // Unknown + e <= my_t'('h11); // Unknown end - else if (cyc==20) begin + else if (cyc==21) begin `checks(e.name, ""); // Unknown end else if (cyc==99) begin diff --git a/test_regress/t/t_enum_public.v b/test_regress/t/t_enum_public.v index dfae146c5..60ed94800 100644 --- a/test_regress/t/t_enum_public.v +++ b/test_regress/t/t_enum_public.v @@ -8,6 +8,9 @@ package p3; typedef enum logic [2:0] { ZERO = 3'b0, ONE = 3'b1 } e3_t /*verilator public*/; + typedef enum logic [2:0] { + TWO = 3'd2, + XES = 3'b?1? } has_x_t /*verilator public*/; endpackage package p62; diff --git a/test_regress/t/t_enum_type_bad.pl b/test_regress/t/t_enum_type_bad.pl new file mode 100755 index 000000000..aa2cd3195 --- /dev/null +++ b/test_regress/t/t_enum_type_bad.pl @@ -0,0 +1,18 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + fails => 0, # But should fail + ); + +ok(1); +1; diff --git a/test_regress/t/t_enum_type_bad.v b/test_regress/t/t_enum_type_bad.v new file mode 100644 index 000000000..84608dbe5 --- /dev/null +++ b/test_regress/t/t_enum_type_bad.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + typedef enum {ZERO, ONE, TWO} e_t; + + typedef enum {THREE=3, FOUR, FIVE} o_t; + + typedef struct packed { + e_t m_e; + o_t m_o; + } struct_t; + + initial begin + e_t e; + o_t o; + struct_t str; + + e = ONE; + e = e_t'(1); + e = e; + + e = 1; // Bad + o = e; // Bad + + str.m_e = ONE; + str.m_o = THREE; + e = str.m_e; + o = str.m_o; + o = str.m_e; // Bad + + end +endmodule diff --git a/test_regress/t/t_enumeration.pl b/test_regress/t/t_enumeration.pl index 9d56f5047..b46d46042 100755 --- a/test_regress/t/t_enumeration.pl +++ b/test_regress/t/t_enumeration.pl @@ -9,7 +9,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); -$Self->{vlt_all} and unsupported("Verilator unsupported, bug460"); compile( ); diff --git a/test_regress/t/t_enumeration.v b/test_regress/t/t_enumeration.v index 50c051c3c..e8f5a5585 100644 --- a/test_regress/t/t_enumeration.v +++ b/test_regress/t/t_enumeration.v @@ -48,7 +48,7 @@ module t (/*AUTOARG*/ rainbow7 <= rainbow7.first(); // check number if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end - if (rainbow7 !== 3'bxxx ) begin $display("%b", rainbow7 ); $stop(); end + // if (rainbow7 !== 3'bxxx ) begin $display("%b", rainbow7 ); $stop(); end end else if (cnt== 1) begin if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end @@ -147,7 +147,7 @@ module t (/*AUTOARG*/ switch <= switch.first(); // check number if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end - if (switch !== 1'bx) begin $display("%b", switch ); $stop(); end + // if (switch !== 1'bx) begin $display("%b", switch ); $stop(); end end else if (cnt== 1) begin if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end @@ -196,7 +196,7 @@ module t (/*AUTOARG*/ family <= family.first(); // check number if (family.num() !== 15 ) begin $display("%d", family.num() ); $stop(); end - if (family !== 32'dx ) begin $display("%b", family ); $stop(); end + // if (family !== 32'dx ) begin $display("%b", family ); $stop(); end end else if (cnt== 1) begin if (family !== 0 ) begin $display("%b", family ); $stop(); end diff --git a/test_regress/t/t_flag_csplit_eval.pl b/test_regress/t/t_flag_csplit_eval.pl index dfd67259c..325f38067 100755 --- a/test_regress/t/t_flag_csplit_eval.pl +++ b/test_regress/t/t_flag_csplit_eval.pl @@ -15,25 +15,21 @@ sub check_evals { local $/; undef $/; my $wholefile = <$fh>; - if ($wholefile =~ /___eval[0-9]+/) { + if ($wholefile =~ /___eval__[0-9]+\(.*\)\s*{/) { ++$got; } } - $got >= 3 or error("Too few _eval functions found: $got"); + $got >= 2 or error("Too few _eval functions found: $got"); } scenarios(vlt_all => 1); compile( - v_flags2 => ["--output-split 1 --output-split-cfuncs 1 --exe ../$Self->{main_filename}"], -# verilator_make_gmake => 0, - ); - -# Very slow to compile, so generally skip it -execute( - check_finished => 1, + v_flags2 => ["--output-split 1 --output-split-cfuncs 20"], + verilator_make_gmake => 0, # Slow to compile, so skip it ); check_evals(); + ok(1); 1; diff --git a/test_regress/t/t_flag_csplit_eval.v b/test_regress/t/t_flag_csplit_eval.v index 685fc7612..53c7976d9 100644 --- a/test_regress/t/t_flag_csplit_eval.v +++ b/test_regress/t/t_flag_csplit_eval.v @@ -22,6 +22,14 @@ module t (/*AUTOARG*/ final if (cnt0 == 0) $stop; final if (cnt1 != 0) $stop; + // Some dummy statements to make the code larger + generate + genvar i; + for (i = 0 ; i < 100; i = i + 1) begin + always @(posedge clk) $c("/*", i, "*/"); + end + endgenerate + always_comb begin if (cnt0==99) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_flag_parameter_pkg.pl b/test_regress/t/t_flag_parameter_pkg.pl new file mode 100755 index 000000000..c0493da3e --- /dev/null +++ b/test_regress/t/t_flag_parameter_pkg.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['-GPARAM_A=1'], + ms_flags2 => ['-GPARAM_A=1'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_flag_parameter_pkg.v b/test_regress/t/t_flag_parameter_pkg.v new file mode 100644 index 000000000..b5c67e4ff --- /dev/null +++ b/test_regress/t/t_flag_parameter_pkg.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2021 by Adrien Le Masle. +// SPDX-License-Identifier: CC0-1.0 + +package pack_a; + parameter PARAM_A = 0; +endpackage : pack_a + +//module t; +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + parameter PARAM_A = 0; + + initial begin + $display(PARAM_A); + if (PARAM_A != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_force.pl b/test_regress/t/t_force.pl new file mode 100755 index 000000000..2cb5eeaff --- /dev/null +++ b/test_regress/t/t_force.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force.v b/test_regress/t/t_force.v new file mode 100644 index 000000000..16270e39d --- /dev/null +++ b/test_regress/t/t_force.v @@ -0,0 +1,102 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + + reg [3:0] in; + tri [3:0] bus = in; + + int never_driven; + int never_forced; + + task force_bus; + force bus[1:0] = 2'b10; + endtask + + task release_bus; + release bus; + endtask + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + in <= 4'b0101; + end + else if (cyc == 1) begin + `checkh(in, 4'b0101); + end + // Check forces with no driver + if (cyc == 1) begin + force never_driven = 32'h888; + end + else if (cyc == 2) begin + `checkh(never_driven, 32'h888); + end + // Check release with no force + else if (cyc == 10) begin + never_forced <= 5432; + end + else if (cyc == 11) begin + `checkh(never_forced, 5432); + end + else if (cyc == 12) begin + release never_forced; // no-op + end + else if (cyc == 13) begin + `checkh(never_forced, 5432); + end + // + // bus + else if (cyc == 10) begin + `checkh(bus, 4'b0101); + force bus = 4'b0111; + end + else if (cyc == 11) begin + `checkh(bus, 4'b0111); + force bus = 4'b1111; + end + else if (cyc == 12) begin + `checkh(bus, 4'b1111); + release bus; + end + else if (cyc == 13) begin + `checkh(bus, 4'b0101); + end + else if (cyc == 20) begin + force_bus(); + end + else if (cyc == 21) begin + `checkh(bus, 4'b0110); + end + else if (cyc == 22) begin + release bus[0]; + end + else if (cyc == 23) begin + `checkh(bus, 4'b0111); + release_bus(); + end + else if (cyc == 24) begin + `checkh(in, 4'b0101); + `checkh(bus, 4'b0101); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_force_bad_rw.out b/test_regress/t/t_force_bad_rw.out new file mode 100644 index 000000000..caa8482e2 --- /dev/null +++ b/test_regress/t/t_force_bad_rw.out @@ -0,0 +1,5 @@ +%Error: t/t_force_bad_rw.v:14:20: Unsupported: Signals used via read-write reference cannot be forced + : ... In instance t.unnamedblk1.unnamedblk1.index + 14 | foreach (ass[index]) begin + | ^~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_force_bad_rw.pl b/test_regress/t/t_force_bad_rw.pl new file mode 100755 index 000000000..b9057722c --- /dev/null +++ b/test_regress/t/t_force_bad_rw.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +compile( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force_bad_rw.v b/test_regress/t/t_force_bad_rw.v new file mode 100644 index 000000000..b7323431f --- /dev/null +++ b/test_regress/t/t_force_bad_rw.v @@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + int ass[int]; + + initial begin + ass[2] = 20; + + foreach (ass[index]) begin + force index = 0; + $display("ii %d\n", index); + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_force_mid.out b/test_regress/t/t_force_mid.out new file mode 100644 index 000000000..93552b55d --- /dev/null +++ b/test_regress/t/t_force_mid.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_force_mid.v:18:17: Unsupported: Force/Release on primary input/output net 'tried' + : ... Suggest assign it to/from a temporary net and force/release that + 18 | output [3:0] tried; + | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_func_bad3.pl b/test_regress/t/t_force_mid.pl similarity index 98% rename from test_regress/t/t_func_bad3.pl rename to test_regress/t/t_force_mid.pl index 877e6133a..c213189c1 100755 --- a/test_regress/t/t_func_bad3.pl +++ b/test_regress/t/t_force_mid.pl @@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); -compile( +lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_force_mid.v b/test_regress/t/t_force_mid.v new file mode 100644 index 000000000..f9031dd8b --- /dev/null +++ b/test_regress/t/t_force_mid.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t(/*AUTOARG*/ + // Outputs + tried, + // Inputs + clk + ); + + input clk; + output [3:0] tried; + + integer cyc = 0; + + assign tried = 4'b0101; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + if (tried != 4'b0101) $stop; + end + else if (cyc == 1) begin + force tried = 4'b1010; + end + else if (cyc == 2) begin + if (tried != 4'b1010) $stop; + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_force_multi.pl b/test_regress/t/t_force_multi.pl new file mode 100755 index 000000000..2cb5eeaff --- /dev/null +++ b/test_regress/t/t_force_multi.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force_multi.v b/test_regress/t/t_force_multi.v new file mode 100644 index 000000000..30e3fbd88 --- /dev/null +++ b/test_regress/t/t_force_multi.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + + logic [3:0] busa; + logic [3:0] busb; + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + busa <= 4'b0101; + busb <= 4'b0111; + end + else if (cyc == 1) begin + force {busa, busb} = 8'b1111_1101; + end + else if (cyc == 2) begin + `checkh(busa, 4'b1111); + `checkh(busb, 4'b1101); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_force_release_net.pl b/test_regress/t/t_force_release_net.pl new file mode 100755 index 000000000..7b483d32e --- /dev/null +++ b/test_regress/t/t_force_release_net.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile(); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force_release_net.v b/test_regress/t/t_force_release_net.v new file mode 100644 index 000000000..0edff5b13 --- /dev/null +++ b/test_regress/t/t_force_release_net.v @@ -0,0 +1,130 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + int cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + wire net_1; + wire [7:0] net_8; + assign net_1 = ~cyc[0]; + assign net_8 = ~cyc[1 +: 8]; + + always @ (posedge clk) begin + $display("%d pre : %x %x", cyc, net_8, net_1); + + case (cyc) + 4: begin + `checkh (net_1, 0); + `checkh (net_8, ~cyc[1 +: 8]); + end + 5: begin + `checkh (net_1, 0); + `checkh (net_8, 8'h5f); + end + 6: begin + `checkh (net_1, 1); + `checkh (net_8, 8'h5f); + end + 7, 8: begin + `checkh (net_1, 1); + `checkh (net_8, 8'hf5); + end + 9: begin + `checkh (net_1, ~cyc[0]); + `checkh (net_8, 8'hf5); + end + 11, 12: begin + `checkh (net_1, 1); + `checkh (net_8, 8'h5a); + end + 13, 14: begin + `checkh (net_1, 0); + `checkh (net_8, 8'ha5); + end + default: begin + `checkh ({net_8, net_1}, ~cyc[0 +: 9]); + end + endcase + +`ifndef REVERSE + if (cyc == 3) force net_1 = 0; + if (cyc == 5) force net_1 = 1; + if (cyc == 8) release net_1; + + if (cyc == 4) force net_8 = 8'h5f; + if (cyc == 6) force net_8 = 8'hf5; + if (cyc == 9) release net_8; + + if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010; + if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0; + if (cyc == 14) release {net_1, net_8}; +`else + if (cyc == 8) release net_1; + if (cyc == 5) force net_1 = 1; + if (cyc == 3) force net_1 = 0; + + if (cyc == 9) release net_8; + if (cyc == 6) force net_8 = 8'hf5; + if (cyc == 4) force net_8 = 8'h5f; + + if (cyc == 14) release {net_1, net_8}; + if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0; + if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010; +`endif + + $display("%d post: %x %x", cyc, net_8, net_1); + + case (cyc) + 3: begin + `checkh (net_1, 0); + `checkh (net_8, ~cyc[1 +: 8]); + end + 4: begin + `checkh (net_1, 0); + `checkh (net_8, 8'h5f); + end + 5: begin + `checkh (net_1, 1); + `checkh (net_8, 8'h5f); + end + 6, 7: begin + `checkh (net_1, 1); + `checkh (net_8, 8'hf5); + end + 8: begin + `checkh (net_1, ~cyc[0]); + `checkh (net_8, 8'hf5); + end + 10, 11: begin + `checkh (net_1, 1); + `checkh (net_8, 8'h5a); + end + 12, 13: begin + `checkh (net_1, 0); + `checkh (net_8, 8'ha5); + end + default: begin + `checkh ({net_8, net_1}, ~cyc[0 +: 9]); + end + endcase + + if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_force_release_net_reverse.pl b/test_regress/t/t_force_release_net_reverse.pl new file mode 100755 index 000000000..709491b91 --- /dev/null +++ b/test_regress/t/t_force_release_net_reverse.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_force_release_net.v"); + +compile( + verilator_flags2 => ['+define+REVERSE'] + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force_release_net_trace.out b/test_regress/t/t_force_release_net_trace.out new file mode 100755 index 000000000..8e4f066fc --- /dev/null +++ b/test_regress/t/t_force_release_net_trace.out @@ -0,0 +1,213 @@ +$version Generated by VerilatedVcd $end +$date Sun Dec 19 14:44:51 2021 $end +$timescale 1ps $end + + $scope module top $end + $var wire 1 # clk $end + $scope module t $end + $var wire 1 # clk $end + $var wire 32 $ cyc [31:0] $end + $var wire 1 % net_1 $end + $var wire 8 & net_8 [7:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0# +b00000000000000000000000000000000 $ +1% +b11111111 & +#10 +1# +b00000000000000000000000000000001 $ +0% +#15 +0# +#20 +1# +b00000000000000000000000000000010 $ +1% +b11111110 & +#25 +0# +#30 +1# +b00000000000000000000000000000011 $ +0% +#35 +0# +#40 +1# +b00000000000000000000000000000100 $ +b11111101 & +#45 +0# +#50 +1# +b00000000000000000000000000000101 $ +b01011111 & +#55 +0# +#60 +1# +b00000000000000000000000000000110 $ +1% +#65 +0# +#70 +1# +b00000000000000000000000000000111 $ +b11110101 & +#75 +0# +#80 +1# +b00000000000000000000000000001000 $ +#85 +0# +#90 +1# +b00000000000000000000000000001001 $ +0% +#95 +0# +#100 +1# +b00000000000000000000000000001010 $ +1% +b11111010 & +#105 +0# +#110 +1# +b00000000000000000000000000001011 $ +b01011010 & +#115 +0# +#120 +1# +b00000000000000000000000000001100 $ +#125 +0# +#130 +1# +b00000000000000000000000000001101 $ +0% +b10100101 & +#135 +0# +#140 +1# +b00000000000000000000000000001110 $ +#145 +0# +#150 +1# +b00000000000000000000000000001111 $ +b11111000 & +#155 +0# +#160 +1# +b00000000000000000000000000010000 $ +1% +b11110111 & +#165 +0# +#170 +1# +b00000000000000000000000000010001 $ +0% +#175 +0# +#180 +1# +b00000000000000000000000000010010 $ +1% +b11110110 & +#185 +0# +#190 +1# +b00000000000000000000000000010011 $ +0% +#195 +0# +#200 +1# +b00000000000000000000000000010100 $ +1% +b11110101 & +#205 +0# +#210 +1# +b00000000000000000000000000010101 $ +0% +#215 +0# +#220 +1# +b00000000000000000000000000010110 $ +1% +b11110100 & +#225 +0# +#230 +1# +b00000000000000000000000000010111 $ +0% +#235 +0# +#240 +1# +b00000000000000000000000000011000 $ +1% +b11110011 & +#245 +0# +#250 +1# +b00000000000000000000000000011001 $ +0% +#255 +0# +#260 +1# +b00000000000000000000000000011010 $ +1% +b11110010 & +#265 +0# +#270 +1# +b00000000000000000000000000011011 $ +0% +#275 +0# +#280 +1# +b00000000000000000000000000011100 $ +1% +b11110001 & +#285 +0# +#290 +1# +b00000000000000000000000000011101 $ +0% +#295 +0# +#300 +1# +b00000000000000000000000000011110 $ +1% +b11110000 & +#305 +0# +#310 +1# +b00000000000000000000000000011111 $ +0% diff --git a/test_regress/t/t_force_release_net_trace.pl b/test_regress/t/t_force_release_net_trace.pl new file mode 100755 index 000000000..6a0f17b04 --- /dev/null +++ b/test_regress/t/t_force_release_net_trace.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_force_release_net.v"); + +compile( + verilator_flags2 => ['--trace'] + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_force_release_var.pl b/test_regress/t/t_force_release_var.pl new file mode 100755 index 000000000..7b483d32e --- /dev/null +++ b/test_regress/t/t_force_release_var.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile(); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force_release_var.v b/test_regress/t/t_force_release_var.v new file mode 100644 index 000000000..6f2791e63 --- /dev/null +++ b/test_regress/t/t_force_release_var.v @@ -0,0 +1,138 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + int cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + reg var_1 = 0; + reg [7:0] var_8 = 0; + always @(posedge clk) begin + var_1 <= cyc[0]; + var_8 <= cyc[1 +: 8]; + end + + always @ (posedge clk) begin + $display("%d pre : %x %x", cyc, var_8, var_1); + + case (cyc) + 0: begin + // Uninitialized + end + 14: begin + `checkh (var_1, 1); + `checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1); + end + 15: begin + `checkh (var_1, 1); + `checkh (var_8, 8'hf5); + end + 16: begin + `checkh (var_1, 0); + `checkh (var_8, 8'hf5); + end + 17, 18: begin + `checkh (var_1, 0); + `checkh (var_8, 8'h5f); + end + 19: begin + `checkh (var_1, ~cyc[0]); + `checkh (var_8, 8'h5f); + end + 21, 22: begin + `checkh (var_1, 1); + `checkh (var_8, 8'h5a); + end + 23, 24: begin + `checkh (var_1, 0); + `checkh (var_8, 8'ha5); + end + default: begin + `checkh ({var_8, var_1}, cyc[0 +: 9] - 1); + end + endcase + +`ifndef REVERSE + if (cyc == 13) force var_1 = 1; + if (cyc == 15) force var_1 = 0; + if (cyc == 18) release var_1; + + if (cyc == 14) force var_8 = 8'hf5; + if (cyc == 16) force var_8 = 8'h5f; + if (cyc == 19) release var_8; + + if (cyc == 20) force {var_1, var_8} = 9'b1_0101_1010; + if (cyc == 22) force {var_8, var_1} = 9'b1010_0101_0; + if (cyc == 24) release {var_1, var_8}; +`else + if (cyc == 18) release var_1; + if (cyc == 15) force var_1 = 0; + if (cyc == 13) force var_1 = 1; + + if (cyc == 19) release var_8; + if (cyc == 16) force var_8 = 8'h5f; + if (cyc == 14) force var_8 = 8'hf5; + + if (cyc == 24) release {var_1, var_8}; + if (cyc == 22) force {var_8, var_1} = 9'b1010_0101_0; + if (cyc == 20) force {var_1, var_8} = 9'b1_0101_1010; +`endif + + $display("%d post: %x %x", cyc, var_8, var_1); + + case (cyc) + 0: begin + // Uninitialized + end + 13: begin + `checkh (var_1, 1); + `checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1); + end + 14: begin + `checkh (var_1, 1); + `checkh (var_8, 8'hf5); + end + 15: begin + `checkh (var_1, 0); + `checkh (var_8, 8'hf5); + end + 16, 17, 18: begin + `checkh (var_1, 0); + `checkh (var_8, 8'h5f); + end + 19: begin + `checkh (var_1, ~cyc[0]); + `checkh (var_8, 8'h5f); + end + 20, 21: begin + `checkh (var_1, 1); + `checkh (var_8, 8'h5a); + end + 22, 23, 24: begin + `checkh (var_1, 0); + `checkh (var_8, 8'ha5); + end + default: begin + `checkh ({var_8, var_1}, cyc[0 +: 9] - 1); + end + endcase + + if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_force_release_var_reverse.pl b/test_regress/t/t_force_release_var_reverse.pl new file mode 100755 index 000000000..7b31629df --- /dev/null +++ b/test_regress/t/t_force_release_var_reverse.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_force_release_var.v"); + +compile( + verilator_flags2 => ['+define+REVERSE'] + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force_release_var_trace.out b/test_regress/t/t_force_release_var_trace.out new file mode 100755 index 000000000..42d114f66 --- /dev/null +++ b/test_regress/t/t_force_release_var_trace.out @@ -0,0 +1,211 @@ +$version Generated by VerilatedVcd $end +$date Sun Dec 19 14:45:16 2021 $end +$timescale 1ps $end + + $scope module top $end + $var wire 1 # clk $end + $scope module t $end + $var wire 1 # clk $end + $var wire 32 $ cyc [31:0] $end + $var wire 1 % var_1 $end + $var wire 8 & var_8 [7:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0# +b00000000000000000000000000000000 $ +0% +b00000000 & +#10 +1# +b00000000000000000000000000000001 $ +#15 +0# +#20 +1# +b00000000000000000000000000000010 $ +1% +#25 +0# +#30 +1# +b00000000000000000000000000000011 $ +0% +b00000001 & +#35 +0# +#40 +1# +b00000000000000000000000000000100 $ +1% +#45 +0# +#50 +1# +b00000000000000000000000000000101 $ +0% +b00000010 & +#55 +0# +#60 +1# +b00000000000000000000000000000110 $ +1% +#65 +0# +#70 +1# +b00000000000000000000000000000111 $ +0% +b00000011 & +#75 +0# +#80 +1# +b00000000000000000000000000001000 $ +1% +#85 +0# +#90 +1# +b00000000000000000000000000001001 $ +0% +b00000100 & +#95 +0# +#100 +1# +b00000000000000000000000000001010 $ +1% +#105 +0# +#110 +1# +b00000000000000000000000000001011 $ +0% +b00000101 & +#115 +0# +#120 +1# +b00000000000000000000000000001100 $ +1% +#125 +0# +#130 +1# +b00000000000000000000000000001101 $ +0% +b00000110 & +#135 +0# +#140 +1# +b00000000000000000000000000001110 $ +1% +#145 +0# +#150 +1# +b00000000000000000000000000001111 $ +b11110101 & +#155 +0# +#160 +1# +b00000000000000000000000000010000 $ +0% +#165 +0# +#170 +1# +b00000000000000000000000000010001 $ +b01011111 & +#175 +0# +#180 +1# +b00000000000000000000000000010010 $ +#185 +0# +#190 +1# +b00000000000000000000000000010011 $ +#195 +0# +#200 +1# +b00000000000000000000000000010100 $ +1% +b00001001 & +#205 +0# +#210 +1# +b00000000000000000000000000010101 $ +b01011010 & +#215 +0# +#220 +1# +b00000000000000000000000000010110 $ +#225 +0# +#230 +1# +b00000000000000000000000000010111 $ +0% +b10100101 & +#235 +0# +#240 +1# +b00000000000000000000000000011000 $ +#245 +0# +#250 +1# +b00000000000000000000000000011001 $ +b00001100 & +#255 +0# +#260 +1# +b00000000000000000000000000011010 $ +1% +#265 +0# +#270 +1# +b00000000000000000000000000011011 $ +0% +b00001101 & +#275 +0# +#280 +1# +b00000000000000000000000000011100 $ +1% +#285 +0# +#290 +1# +b00000000000000000000000000011101 $ +0% +b00001110 & +#295 +0# +#300 +1# +b00000000000000000000000000011110 $ +1% +#305 +0# +#310 +1# +b00000000000000000000000000011111 $ +0% +b00001111 & diff --git a/test_regress/t/t_force_release_var_trace.pl b/test_regress/t/t_force_release_var_trace.pl new file mode 100755 index 000000000..2e7da6c27 --- /dev/null +++ b/test_regress/t/t_force_release_var_trace.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_force_release_var.v"); + +compile( + verilator_flags2 => ['--trace'] + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_force_subnet.pl b/test_regress/t/t_force_subnet.pl new file mode 100755 index 000000000..2cb5eeaff --- /dev/null +++ b/test_regress/t/t_force_subnet.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force_subnet.v b/test_regress/t/t_force_subnet.v new file mode 100644 index 000000000..0adbf5fc0 --- /dev/null +++ b/test_regress/t/t_force_subnet.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + + logic [7:0] subnet; + sub1 sub1(.*); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + `checkh(subnet, 8'h11); + force sub1.subnet = 8'h01; // sub1.subnet same as subnet + end + else if (cyc == 11) begin + `checkh(subnet, 8'h01); + force subnet = 8'h10; // sub1.subnet same as subnet + end + else if (cyc == 12) begin + `checkh(subnet, 8'h10); + release subnet; // sub1.subnet same as subnet + end + else if (cyc == 13) begin + `checkh(subnet, 8'h11); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub1(output logic [7:0] subnet); + assign subnet = 8'h11; +endmodule diff --git a/test_regress/t/t_force_subvar.pl b/test_regress/t/t_force_subvar.pl new file mode 100755 index 000000000..2cb5eeaff --- /dev/null +++ b/test_regress/t/t_force_subvar.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_force_subvar.v b/test_regress/t/t_force_subvar.v new file mode 100644 index 000000000..13726af61 --- /dev/null +++ b/test_regress/t/t_force_subvar.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + + sub sub(); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + // procedural var sub.subvar + if (cyc == 50) begin + `checkh(sub.subvar, 32'h666); + force sub.subvar = 32'hffff; + end + else if (cyc == 51) begin + `checkh(sub.subvar, 32'hffff); + sub.subvar = 32'h543; // Ignored as still forced + end + else if (cyc == 52) begin + `checkh(sub.subvar, 32'hffff); + end + else if (cyc == 53) begin + release sub.subvar; + end + else if (cyc == 54) begin + `checkh(sub.subvar, 32'hffff); // Retains value until next procedural change + sub.subvar = 32'h544; + end + else if (cyc == 56) begin + `checkh(sub.subvar, 32'h544); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub; + int subvar; + initial subvar = 32'h666; +endmodule diff --git a/test_regress/t/t_force_tri.out b/test_regress/t/t_force_tri.out new file mode 100644 index 000000000..97b0dd018 --- /dev/null +++ b/test_regress/t/t_force_tri.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_force_tri.v:27:10: Unsupported tristate construct: ASSIGNFORCE + : ... In instance t + 27 | force bus = 4'bzz10; + | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_func_bad2.pl b/test_regress/t/t_force_tri.pl similarity index 98% rename from test_regress/t/t_func_bad2.pl rename to test_regress/t/t_force_tri.pl index 877e6133a..c213189c1 100755 --- a/test_regress/t/t_func_bad2.pl +++ b/test_regress/t/t_force_tri.pl @@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); -compile( +lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_force_tri.v b/test_regress/t/t_force_tri.v new file mode 100644 index 000000000..62dbd1938 --- /dev/null +++ b/test_regress/t/t_force_tri.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + + logic [3:0] bus; + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + bus <= 4'b0101; + end + else if (cyc == 1) begin + force bus = 4'bzz10; + end + else if (cyc == 2) begin + `checkh(bus, 4'bzz10); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_forceable_net.cpp b/test_regress/t/t_forceable_net.cpp new file mode 100644 index 000000000..da9388a75 --- /dev/null +++ b/test_regress/t/t_forceable_net.cpp @@ -0,0 +1,118 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include "verilatedos.h" +#include "verilated.h" +#if VM_TRACE +#include "verilated_vcd_c.h" +#endif + +#include VM_PREFIX_INCLUDE +#include VM_PREFIX_ROOT_INCLUDE + +int main(int argc, char** argv) { + const std::unique_ptr contextp{new VerilatedContext}; + contextp->commandArgs(argc, argv); + contextp->debug(0); + srand48(5); + + const std::unique_ptr topp{new VM_PREFIX{"top"}}; + + topp->clk = false; + topp->rst = true; + topp->eval(); +#if VM_TRACE + contextp->traceEverOn(true); + std::unique_ptr tfp{new VerilatedVcdC}; + topp->trace(tfp.get(), 99); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); + tfp->dump(contextp->time()); +#endif + contextp->timeInc(5); + + topp->clk = true; + topp->eval(); + topp->rst = false; + topp->eval(); +#if VM_TRACE + tfp->dump(contextp->time()); +#endif + contextp->timeInc(5); + + while (contextp->time() < 1000 && !contextp->gotFinish()) { + topp->clk = !topp->clk; + topp->eval(); + + if (topp->clk) { + bool needsSecondEval = false; + + if (topp->cyc == 3) { + topp->rootp->t__DOT__net_1__VforceEn = 1; + topp->rootp->t__DOT__net_1__VforceVal = 0; + needsSecondEval = true; + } + if (topp->cyc == 5) { + topp->rootp->t__DOT__net_1__VforceVal = 1; + needsSecondEval = true; + } + if (topp->cyc == 8) { + topp->rootp->t__DOT__net_1__VforceEn = 0; + needsSecondEval = true; + } + + if (topp->cyc == 4) { + topp->rootp->t__DOT__net_8__VforceEn = 0xff; + topp->rootp->t__DOT__net_8__VforceVal = 0x5f; + needsSecondEval = true; + } + if (topp->cyc == 6) { + topp->rootp->t__DOT__net_8__VforceVal = 0xf5; + needsSecondEval = true; + } + if (topp->cyc == 9) { + topp->rootp->t__DOT__net_8__VforceEn = 0; + needsSecondEval = true; + } + + if (topp->cyc == 10) { + topp->rootp->t__DOT__net_1__VforceEn = 1; + topp->rootp->t__DOT__net_8__VforceEn = 0xff; + topp->rootp->t__DOT__net_1__VforceVal = 1; + topp->rootp->t__DOT__net_8__VforceVal = 0x5a; + needsSecondEval = true; + } + if (topp->cyc == 12) { + topp->rootp->t__DOT__net_1__VforceVal = 0; + topp->rootp->t__DOT__net_8__VforceVal = 0xa5; + needsSecondEval = true; + } + if (topp->cyc == 14) { + topp->rootp->t__DOT__net_1__VforceEn = 0; + topp->rootp->t__DOT__net_8__VforceEn = 0; + needsSecondEval = true; + } + + if (needsSecondEval) topp->eval(); + } +#if VM_TRACE + tfp->dump(contextp->time()); +#endif + contextp->timeInc(5); + } + + if (!contextp->gotFinish()) { + vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); + } + + topp->final(); +#if VM_TRACE + tfp->close(); +#endif + + return 0; +} diff --git a/test_regress/t/t_forceable_net.v b/test_regress/t/t_forceable_net.v new file mode 100644 index 000000000..c84645a38 --- /dev/null +++ b/test_regress/t/t_forceable_net.v @@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t ( + input wire clk, + input wire rst, + output reg [31:0] cyc + ); + + always @(posedge clk) begin + if (rst) begin + cyc <= 0; + end else begin + cyc <= cyc +1; + end + end + +`ifdef CMT + wire net_1 /* verilator forceable */; + wire [7:0] net_8 /* verilator forceable */; +`else + wire net_1; + wire [7:0] net_8; +`endif + + assign net_1 = ~cyc[0]; + assign net_8 = ~cyc[1 +: 8]; + + always @ (posedge clk) begin + $display("%d: %x %x", cyc, net_8, net_1); + + if (!rst) begin + case (cyc) + 3: begin + `checkh (net_1, 0); + `checkh (net_8, ~cyc[1 +: 8]); + end + 4: begin + `checkh (net_1, 0); + `checkh (net_8, 8'h5f); + end + 5: begin + `checkh (net_1, 1); + `checkh (net_8, 8'h5f); + end + 6, 7: begin + `checkh (net_1, 1); + `checkh (net_8, 8'hf5); + end + 8: begin + `checkh (net_1, ~cyc[0]); + `checkh (net_8, 8'hf5); + end + 10, 11: begin + `checkh (net_1, 1); + `checkh (net_8, 8'h5a); + end + 12, 13: begin + `checkh (net_1, 0); + `checkh (net_8, 8'ha5); + end + default: begin + `checkh ({net_8, net_1}, ~cyc[0 +: 9]); + end + endcase + end + + if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_forceable_net.vlt b/test_regress/t/t_forceable_net.vlt new file mode 100644 index 000000000..e551de233 --- /dev/null +++ b/test_regress/t/t_forceable_net.vlt @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +`verilator_config + +forceable -module "*" -var "net_*" diff --git a/test_regress/t/t_forceable_net_cmt.pl b/test_regress/t/t_forceable_net_cmt.pl new file mode 100755 index 000000000..ff2553af1 --- /dev/null +++ b/test_regress/t/t_forceable_net_cmt.pl @@ -0,0 +1,30 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_forceable_net.v"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + '-DCMT=1', + '--exe', + "$Self->{t_dir}/t_forceable_net.cpp" + ], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_forceable_net_cmt_trace.pl b/test_regress/t/t_forceable_net_cmt_trace.pl new file mode 100755 index 000000000..af5581da8 --- /dev/null +++ b/test_regress/t/t_forceable_net_cmt_trace.pl @@ -0,0 +1,34 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_forceable_net.v"); +golden_filename("t/t_forceable_net_trace.vcd"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + '-DCMT=1', + '--exe', + '--trace', + "$Self->{t_dir}/t_forceable_net.cpp" + ], + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_forceable_net_trace.vcd b/test_regress/t/t_forceable_net_trace.vcd new file mode 100644 index 000000000..faef0833b --- /dev/null +++ b/test_regress/t/t_forceable_net_trace.vcd @@ -0,0 +1,223 @@ +$version Generated by VerilatedVcd $end +$date Sun Dec 19 19:39:17 2021 $end +$timescale 1ps $end + + $scope module top $end + $var wire 1 # clk $end + $var wire 32 % cyc [31:0] $end + $var wire 1 $ rst $end + $scope module t $end + $var wire 1 # clk $end + $var wire 32 % cyc [31:0] $end + $var wire 1 & net_1 $end + $var wire 8 ' net_8 [7:0] $end + $var wire 1 $ rst $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0# +1$ +b00000000000000000000000000000000 % +1& +b11111111 ' +#5 +1# +0$ +#10 +0# +#15 +1# +b00000000000000000000000000000001 % +0& +#20 +0# +#25 +1# +b00000000000000000000000000000010 % +1& +b11111110 ' +#30 +0# +#35 +1# +b00000000000000000000000000000011 % +0& +#40 +0# +#45 +1# +b00000000000000000000000000000100 % +b01011111 ' +#50 +0# +#55 +1# +b00000000000000000000000000000101 % +1& +#60 +0# +#65 +1# +b00000000000000000000000000000110 % +b11110101 ' +#70 +0# +#75 +1# +b00000000000000000000000000000111 % +#80 +0# +#85 +1# +b00000000000000000000000000001000 % +#90 +0# +#95 +1# +b00000000000000000000000000001001 % +0& +b11111011 ' +#100 +0# +#105 +1# +b00000000000000000000000000001010 % +1& +b01011010 ' +#110 +0# +#115 +1# +b00000000000000000000000000001011 % +#120 +0# +#125 +1# +b00000000000000000000000000001100 % +0& +b10100101 ' +#130 +0# +#135 +1# +b00000000000000000000000000001101 % +#140 +0# +#145 +1# +b00000000000000000000000000001110 % +1& +b11111000 ' +#150 +0# +#155 +1# +b00000000000000000000000000001111 % +0& +#160 +0# +#165 +1# +b00000000000000000000000000010000 % +1& +b11110111 ' +#170 +0# +#175 +1# +b00000000000000000000000000010001 % +0& +#180 +0# +#185 +1# +b00000000000000000000000000010010 % +1& +b11110110 ' +#190 +0# +#195 +1# +b00000000000000000000000000010011 % +0& +#200 +0# +#205 +1# +b00000000000000000000000000010100 % +1& +b11110101 ' +#210 +0# +#215 +1# +b00000000000000000000000000010101 % +0& +#220 +0# +#225 +1# +b00000000000000000000000000010110 % +1& +b11110100 ' +#230 +0# +#235 +1# +b00000000000000000000000000010111 % +0& +#240 +0# +#245 +1# +b00000000000000000000000000011000 % +1& +b11110011 ' +#250 +0# +#255 +1# +b00000000000000000000000000011001 % +0& +#260 +0# +#265 +1# +b00000000000000000000000000011010 % +1& +b11110010 ' +#270 +0# +#275 +1# +b00000000000000000000000000011011 % +0& +#280 +0# +#285 +1# +b00000000000000000000000000011100 % +1& +b11110001 ' +#290 +0# +#295 +1# +b00000000000000000000000000011101 % +0& +#300 +0# +#305 +1# +b00000000000000000000000000011110 % +1& +b11110000 ' +#310 +0# +#315 +1# +b00000000000000000000000000011111 % +0& diff --git a/test_regress/t/t_forceable_net_vlt.pl b/test_regress/t/t_forceable_net_vlt.pl new file mode 100755 index 000000000..595b70dc8 --- /dev/null +++ b/test_regress/t/t_forceable_net_vlt.pl @@ -0,0 +1,30 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_forceable_net.v"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + '--exe', + "$Self->{t_dir}/t_forceable_net.cpp", + "$Self->{t_dir}/t_forceable_net.vlt" + ], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_forceable_net_vlt_trace.pl b/test_regress/t/t_forceable_net_vlt_trace.pl new file mode 100755 index 000000000..eb0d52d78 --- /dev/null +++ b/test_regress/t/t_forceable_net_vlt_trace.pl @@ -0,0 +1,34 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_forceable_net.v"); +golden_filename("t/t_forceable_net_trace.vcd"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + '--exe', + '--trace', + "$Self->{t_dir}/t_forceable_net.cpp", + "$Self->{t_dir}/t_forceable_net.vlt" + ], + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_forceable_var.cpp b/test_regress/t/t_forceable_var.cpp new file mode 100644 index 000000000..931903300 --- /dev/null +++ b/test_regress/t/t_forceable_var.cpp @@ -0,0 +1,118 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include "verilatedos.h" +#include "verilated.h" +#if VM_TRACE +#include "verilated_vcd_c.h" +#endif + +#include VM_PREFIX_INCLUDE +#include VM_PREFIX_ROOT_INCLUDE + +int main(int argc, char** argv) { + const std::unique_ptr contextp{new VerilatedContext}; + contextp->commandArgs(argc, argv); + contextp->debug(0); + srand48(5); + + const std::unique_ptr topp{new VM_PREFIX{"top"}}; + + topp->clk = false; + topp->rst = true; + topp->eval(); +#if VM_TRACE + contextp->traceEverOn(true); + std::unique_ptr tfp{new VerilatedVcdC}; + topp->trace(tfp.get(), 99); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); + tfp->dump(contextp->time()); +#endif + contextp->timeInc(5); + + topp->clk = true; + topp->eval(); + topp->rst = false; + topp->eval(); +#if VM_TRACE + tfp->dump(contextp->time()); +#endif + contextp->timeInc(5); + + while (contextp->time() < 1000 && !contextp->gotFinish()) { + topp->clk = !topp->clk; + topp->eval(); + + if (topp->clk) { + bool needsSecondEval = false; + + if (topp->cyc == 13) { + topp->rootp->t__DOT__var_1__VforceEn = 1; + topp->rootp->t__DOT__var_1__VforceVal = 1; + needsSecondEval = true; + } + if (topp->cyc == 15) { + topp->rootp->t__DOT__var_1__VforceVal = 0; + needsSecondEval = true; + } + if (topp->cyc == 18) { + topp->rootp->t__DOT__var_1__VforceEn = 0; + needsSecondEval = true; + } + + if (topp->cyc == 14) { + topp->rootp->t__DOT__var_8__VforceEn = 0xff; + topp->rootp->t__DOT__var_8__VforceVal = 0xf5; + needsSecondEval = true; + } + if (topp->cyc == 16) { + topp->rootp->t__DOT__var_8__VforceVal = 0x5f; + needsSecondEval = true; + } + if (topp->cyc == 19) { + topp->rootp->t__DOT__var_8__VforceEn = 0; + needsSecondEval = true; + } + + if (topp->cyc == 20) { + topp->rootp->t__DOT__var_1__VforceEn = 1; + topp->rootp->t__DOT__var_8__VforceEn = 0xff; + topp->rootp->t__DOT__var_1__VforceVal = 1; + topp->rootp->t__DOT__var_8__VforceVal = 0x5a; + needsSecondEval = true; + } + if (topp->cyc == 22) { + topp->rootp->t__DOT__var_1__VforceVal = 0; + topp->rootp->t__DOT__var_8__VforceVal = 0xa5; + needsSecondEval = true; + } + if (topp->cyc == 24) { + topp->rootp->t__DOT__var_1__VforceEn = 0; + topp->rootp->t__DOT__var_8__VforceEn = 0; + needsSecondEval = true; + } + + if (needsSecondEval) topp->eval(); + } +#if VM_TRACE + tfp->dump(contextp->time()); +#endif + contextp->timeInc(5); + } + + if (!contextp->gotFinish()) { + vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); + } + + topp->final(); +#if VM_TRACE + tfp->close(); +#endif + + return 0; +} diff --git a/test_regress/t/t_forceable_var.v b/test_regress/t/t_forceable_var.v new file mode 100644 index 000000000..fbd7164c6 --- /dev/null +++ b/test_regress/t/t_forceable_var.v @@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t ( + input wire clk, + input wire rst, + output reg [31:0] cyc + ); + + always @(posedge clk) begin + if (rst) begin + cyc <= 0; + end else begin + cyc <= cyc +1; + end + end + +`ifdef CMT + reg var_1 /* verilator forceable */; + reg [7:0] var_8 /* verilator forceable */; +`else + reg var_1; + reg [7:0] var_8; +`endif + + always @(posedge clk) begin + if (rst) begin + var_1 <= 0; + var_8 <= 0; + end else begin + var_1 <= cyc[0]; + var_8 <= cyc[1 +: 8]; + end + end + + always @ (posedge clk) begin + $display("%d: %x %x", cyc, var_8, var_1); + + if (!rst) begin + case (cyc) + 0: begin // Reset values + `checkh (var_1, 0); + `checkh (var_8, 0); + end + 13: begin + `checkh (var_1, 1); + `checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1); + end + 14: begin + `checkh (var_1, 1); + `checkh (var_8, 8'hf5); + end + 15: begin + `checkh (var_1, 0); + `checkh (var_8, 8'hf5); + end + 16, 17: begin + `checkh (var_1, 0); + `checkh (var_8, 8'h5f); + end + 18: begin + `checkh (var_1, ~cyc[0]); + `checkh (var_8, 8'h5f); + end + 20, 21: begin + `checkh (var_1, 1); + `checkh (var_8, 8'h5a); + end + 22, 23: begin + `checkh (var_1, 0); + `checkh (var_8, 8'ha5); + end + default: begin + `checkh ({var_8, var_1}, cyc[0 +: 9] - 1); + end + endcase + end + + if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_forceable_var.vlt b/test_regress/t/t_forceable_var.vlt new file mode 100644 index 000000000..c64f48200 --- /dev/null +++ b/test_regress/t/t_forceable_var.vlt @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +`verilator_config + +forceable -module "*" -var "var_*" diff --git a/test_regress/t/t_forceable_var_cmt.pl b/test_regress/t/t_forceable_var_cmt.pl new file mode 100755 index 000000000..ba21c8b9b --- /dev/null +++ b/test_regress/t/t_forceable_var_cmt.pl @@ -0,0 +1,30 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_forceable_var.v"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + '-DCMT=1', + '--exe', + "$Self->{t_dir}/t_forceable_var.cpp" + ], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_forceable_var_cmt_trace.pl b/test_regress/t/t_forceable_var_cmt_trace.pl new file mode 100755 index 000000000..51443e81c --- /dev/null +++ b/test_regress/t/t_forceable_var_cmt_trace.pl @@ -0,0 +1,34 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_forceable_var.v"); +golden_filename("t/t_forceable_var_trace.vcd"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + '-DCMT=1', + '--exe', + '--trace', + "$Self->{t_dir}/t_forceable_var.cpp" + ], + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_forceable_var_trace.vcd b/test_regress/t/t_forceable_var_trace.vcd new file mode 100644 index 000000000..2aaaa7dac --- /dev/null +++ b/test_regress/t/t_forceable_var_trace.vcd @@ -0,0 +1,223 @@ +$version Generated by VerilatedVcd $end +$date Sun Dec 19 19:26:33 2021 $end +$timescale 1ps $end + + $scope module top $end + $var wire 1 # clk $end + $var wire 32 % cyc [31:0] $end + $var wire 1 $ rst $end + $scope module t $end + $var wire 1 # clk $end + $var wire 32 % cyc [31:0] $end + $var wire 1 $ rst $end + $var wire 1 & var_1 $end + $var wire 8 ' var_8 [7:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0# +1$ +b00000000000000000000000000000000 % +0& +b00000000 ' +#5 +1# +0$ +#10 +0# +#15 +1# +b00000000000000000000000000000001 % +#20 +0# +#25 +1# +b00000000000000000000000000000010 % +1& +#30 +0# +#35 +1# +b00000000000000000000000000000011 % +0& +b00000001 ' +#40 +0# +#45 +1# +b00000000000000000000000000000100 % +1& +#50 +0# +#55 +1# +b00000000000000000000000000000101 % +0& +b00000010 ' +#60 +0# +#65 +1# +b00000000000000000000000000000110 % +1& +#70 +0# +#75 +1# +b00000000000000000000000000000111 % +0& +b00000011 ' +#80 +0# +#85 +1# +b00000000000000000000000000001000 % +1& +#90 +0# +#95 +1# +b00000000000000000000000000001001 % +0& +b00000100 ' +#100 +0# +#105 +1# +b00000000000000000000000000001010 % +1& +#110 +0# +#115 +1# +b00000000000000000000000000001011 % +0& +b00000101 ' +#120 +0# +#125 +1# +b00000000000000000000000000001100 % +1& +#130 +0# +#135 +1# +b00000000000000000000000000001101 % +b00000110 ' +#140 +0# +#145 +1# +b00000000000000000000000000001110 % +b11110101 ' +#150 +0# +#155 +1# +b00000000000000000000000000001111 % +0& +#160 +0# +#165 +1# +b00000000000000000000000000010000 % +b01011111 ' +#170 +0# +#175 +1# +b00000000000000000000000000010001 % +#180 +0# +#185 +1# +b00000000000000000000000000010010 % +1& +#190 +0# +#195 +1# +b00000000000000000000000000010011 % +0& +b00001001 ' +#200 +0# +#205 +1# +b00000000000000000000000000010100 % +1& +b01011010 ' +#210 +0# +#215 +1# +b00000000000000000000000000010101 % +#220 +0# +#225 +1# +b00000000000000000000000000010110 % +0& +b10100101 ' +#230 +0# +#235 +1# +b00000000000000000000000000010111 % +#240 +0# +#245 +1# +b00000000000000000000000000011000 % +1& +b00001011 ' +#250 +0# +#255 +1# +b00000000000000000000000000011001 % +0& +b00001100 ' +#260 +0# +#265 +1# +b00000000000000000000000000011010 % +1& +#270 +0# +#275 +1# +b00000000000000000000000000011011 % +0& +b00001101 ' +#280 +0# +#285 +1# +b00000000000000000000000000011100 % +1& +#290 +0# +#295 +1# +b00000000000000000000000000011101 % +0& +b00001110 ' +#300 +0# +#305 +1# +b00000000000000000000000000011110 % +1& +#310 +0# +#315 +1# +b00000000000000000000000000011111 % +0& +b00001111 ' diff --git a/test_regress/t/t_forceable_var_vlt.pl b/test_regress/t/t_forceable_var_vlt.pl new file mode 100755 index 000000000..c0b9f7b79 --- /dev/null +++ b/test_regress/t/t_forceable_var_vlt.pl @@ -0,0 +1,30 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_forceable_var.v"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + '--exe', + "$Self->{t_dir}/t_forceable_var.cpp", + "$Self->{t_dir}/t_forceable_var.vlt" + ], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_forceable_var_vlt_trace.pl b/test_regress/t/t_forceable_var_vlt_trace.pl new file mode 100755 index 000000000..932307bb5 --- /dev/null +++ b/test_regress/t/t_forceable_var_vlt_trace.pl @@ -0,0 +1,34 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_forceable_var.v"); +golden_filename("t/t_forceable_var_trace.vcd"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + '--exe', + '--trace', + "$Self->{t_dir}/t_forceable_var.cpp", + "$Self->{t_dir}/t_forceable_var.vlt" + ], + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v index 3d9b26afa..826abc114 100644 --- a/test_regress/t/t_foreach.v +++ b/test_regress/t/t_foreach.v @@ -16,6 +16,8 @@ module t (/*AUTOARG*/); reg [2:1] [4:3] array [5:6] [7:8]; reg [1:2] [3:4] larray [6:5] [8:7]; bit [31:0] depth1_array [0:0]; + int oned [3:1]; + int twod [3:1][9:8]; typedef struct packed { reg [1:0] [63:0] subarray; @@ -69,8 +71,15 @@ module t (/*AUTOARG*/); end `checkh(sum, 64'h0030128ab2a8e557); - // + // comma syntax + sum = 0; + foreach (array[,index_b]) begin + $display(index_b); + sum = crc(sum, 0, index_b, 0, 0); + end + `checkh(sum, 64'h0000000006000000); + // sum = 0; foreach (larray[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); @@ -110,6 +119,39 @@ module t (/*AUTOARG*/); `checkh(add, 'h19); `endif + add = 0; + foreach (oned[i]) begin + ++add; + break; + end + `checkh(add, 1); // 9 + + add = 0; + foreach (oned[i]) begin + ++add; + continue; + add += 100; + end + `checkh(add, 3); // 9, 8, 7 + + add = 0; + foreach (twod[i, j]) begin + ++add; + break; + end + // See https://www.accellera.org/images/eda/sv-bc/10303.html + `checkh(add, 1); // 3,9 + + add = 0; + foreach (twod[i, j]) begin + ++add; + continue; + add += 100; + end + `checkh(add, 6); + + foreach (twod[i, j]); // Null body check + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_foreach_bad.out b/test_regress/t/t_foreach_bad.out index cbb916320..799c765f5 100644 --- a/test_regress/t/t_foreach_bad.out +++ b/test_regress/t/t_foreach_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_foreach_bad.v:14:7: Syntax error; foreach missing bracketed index variable (IEEE 1800-2017 12.7.3) +%Error: t/t_foreach_bad.v:14:7: Syntax error; foreach missing bracketed loop variable (IEEE 1800-2017 12.7.3) 14 | foreach (array); | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_foreach_class.pl b/test_regress/t/t_foreach_class.pl new file mode 100755 index 000000000..b46d46042 --- /dev/null +++ b/test_regress/t/t_foreach_class.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_foreach_class.v b/test_regress/t/t_foreach_class.v new file mode 100644 index 000000000..0f53bb3f4 --- /dev/null +++ b/test_regress/t/t_foreach_class.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +class Cls; + int q[$]; + function new(); + q.push_back(1); + q.push_back(2); + q.push_back(3); + endfunction +endclass + +module t (/*AUTOARG*/); + + int two[5:6]; + + if (1) begin : named + Cls c; + end + + function [63:0] crc(input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); + crc = {sum[62:0],sum[63]} ^ {20'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; + endfunction + + bit [63:0] sum; + + initial begin + named.c = new; + sum = 0; + foreach (named.c.q[i]) begin + foreach (two[j]) begin + // $display(i, j); + sum = crc(sum, i, named.c.q[i], j, 0); + end + end + `checkh(sum, 64'h000000a02d0fc000); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_foreach_iface.pl b/test_regress/t/t_foreach_iface.pl new file mode 100755 index 000000000..1aa73f80a --- /dev/null +++ b/test_regress/t/t_foreach_iface.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_foreach_iface.v b/test_regress/t/t_foreach_iface.v new file mode 100644 index 000000000..0412c6821 --- /dev/null +++ b/test_regress/t/t_foreach_iface.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Pawel Jewstafjew (Pawel.Jewstafjew@gmail.com). +// SPDX-License-Identifier: CC0-1.0 + +interface Iface (input bit [31:0] regs [1]); + initial begin + string instance_path = $sformatf("%m"); + $display("Iface path %s\n", instance_path); + $write("*-* All Finished *-*\n"); + $finish; + end + + bit [0:0] ppp; + always_comb begin + // Ok: + //for (int index = 1 ; index < 2 ; ++index) begin + foreach (regs[index]) begin + ppp[index] = 1; + end + end + +endinterface + +module top (input bit [31:0] regs [1]); + Iface t1(.regs(regs)); +endmodule diff --git a/test_regress/t/t_foreach_type_bad.out b/test_regress/t/t_foreach_type_bad.out new file mode 100644 index 000000000..df9bcdd48 --- /dev/null +++ b/test_regress/t/t_foreach_type_bad.out @@ -0,0 +1,13 @@ +%Error: t/t_foreach_type_bad.v:19:18: Illegal to foreach loop on 'CLASSREFDTYPE 'Cls'' + 19 | foreach (c[i]); + | ^ +%Error: t/t_foreach_type_bad.v:21:18: Illegal to foreach loop on basic 'BASICDTYPE 'real'' + 21 | foreach (r[i]); + | ^ +%Error: t/t_foreach_type_bad.v:23:21: Illegal to foreach loop on basic 'BASICDTYPE 'bit'' + 23 | foreach (b[i, j, k]); + | ^ +%Error: t/t_foreach_type_bad.v:25:18: Illegal to foreach loop on basic 'BASICDTYPE 'real'' + 25 | foreach (r[, i]); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_foreach_type_bad.pl b/test_regress/t/t_foreach_type_bad.pl new file mode 100755 index 000000000..a60503a1f --- /dev/null +++ b/test_regress/t/t_foreach_type_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_foreach_type_bad.v b/test_regress/t/t_foreach_type_bad.v new file mode 100644 index 000000000..fbcf3a425 --- /dev/null +++ b/test_regress/t/t_foreach_type_bad.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Cls; +endclass + +module t (/*AUTOARG*/); + + real r; + + bit b[2]; + + Cls c; + + initial begin + foreach (c[i]); // bad type + + foreach (r[i]); // no loop var + + foreach (b[i, j, k]); // extra loop var + + foreach (r[, i]); // no loop var and extra + + $stop; + end + +endmodule diff --git a/test_regress/t/t_func_bad2.out b/test_regress/t/t_func_bad2.out deleted file mode 100644 index ee66206cb..000000000 --- a/test_regress/t/t_func_bad2.out +++ /dev/null @@ -1,6 +0,0 @@ -%Error-UNSUPPORTED: t/t_func_bad2.v:8:13: Unsupported: Recursive function or task call - : ... In instance t - 8 | function recurse; - | ^~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Exiting due to diff --git a/test_regress/t/t_func_bad2.v b/test_regress/t/t_func_bad2.v deleted file mode 100644 index 19ead4dd4..000000000 --- a/test_regress/t/t_func_bad2.v +++ /dev/null @@ -1,18 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t; - function recurse; - input i; - recurse = recurse2(i); - endfunction - - function recurse2; - input i; - recurse2 = recurse(i); - endfunction - -endmodule diff --git a/test_regress/t/t_func_bad3.out b/test_regress/t/t_func_bad3.out deleted file mode 100644 index 628c1a173..000000000 --- a/test_regress/t/t_func_bad3.out +++ /dev/null @@ -1,5 +0,0 @@ -%Error-UNSUPPORTED: t/t_func_bad3.v:12:27: Unsupported: Recursive function call 'recurse_self' - 12 | else recurse_self = recurse_self(i - 1) + 1; - | ^~~~~~~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Exiting due to diff --git a/test_regress/t/t_func_dotted_inl0.pl b/test_regress/t/t_func_dotted_inl0.pl index 000ae222d..f286aa790 100755 --- a/test_regress/t/t_func_dotted_inl0.pl +++ b/test_regress/t/t_func_dotted_inl0.pl @@ -18,10 +18,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_func_dotted_inl0_vlt.pl b/test_regress/t/t_func_dotted_inl0_vlt.pl index 321df222d..711fb0708 100755 --- a/test_regress/t/t_func_dotted_inl0_vlt.pl +++ b/test_regress/t/t_func_dotted_inl0_vlt.pl @@ -18,10 +18,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_func_dotted_inl2.pl b/test_regress/t/t_func_dotted_inl2.pl index 6f6d98c4c..2dede96b9 100755 --- a/test_regress/t/t_func_dotted_inl2.pl +++ b/test_regress/t/t_func_dotted_inl2.pl @@ -18,8 +18,8 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_func_dotted_inl2_vlt.pl b/test_regress/t/t_func_dotted_inl2_vlt.pl index 378a9e7ae..5e8ee23b4 100755 --- a/test_regress/t/t_func_dotted_inl2_vlt.pl +++ b/test_regress/t/t_func_dotted_inl2_vlt.pl @@ -18,8 +18,8 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_func_public.v b/test_regress/t/t_func_public.v index d97a93b34..00a58e67e 100644 --- a/test_regress/t/t_func_public.v +++ b/test_regress/t/t_func_public.v @@ -32,6 +32,13 @@ module t (clk); $write("Hello in publicTop\n"); endtask + task test_task(input [19:0] in [2], output [19:0] out [2]); + // Issue 3316 + // verilator public + out[0] = in[1]; + out[1] = in[0]; + endtask + endmodule module tpub ( diff --git a/test_regress/t/t_func_recurse.out b/test_regress/t/t_func_recurse.out new file mode 100644 index 000000000..81f9b9dde --- /dev/null +++ b/test_regress/t/t_func_recurse.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_func_recurse.v:9:27: Unsupported: Recursive function or task call: 'recurse_self' + : ... In instance t + 9 | function automatic int recurse_self; + | ^~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_func_recurse.pl b/test_regress/t/t_func_recurse.pl new file mode 100755 index 000000000..be66c40e6 --- /dev/null +++ b/test_regress/t/t_func_recurse.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_func_recurse.v b/test_regress/t/t_func_recurse.v new file mode 100644 index 000000000..2b03f09e4 --- /dev/null +++ b/test_regress/t/t_func_recurse.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + function automatic int recurse_self; + input int i; + if (i == 0) recurse_self = 0; + else recurse_self = i + recurse_self(i - 1) * 2; + endfunction + + initial begin + if (recurse_self(0) != 0) $stop; + if (recurse_self(3) != (3 + 2*(2 + 2*(1)))) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_func_recurse2.out b/test_regress/t/t_func_recurse2.out new file mode 100644 index 000000000..b93b57e47 --- /dev/null +++ b/test_regress/t/t_func_recurse2.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_func_recurse2.v:9:27: Unsupported: Recursive function or task call: 'recurse_1' + : ... In instance t + 9 | function automatic int recurse_1; + | ^~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_func_recurse2.pl b/test_regress/t/t_func_recurse2.pl new file mode 100755 index 000000000..be66c40e6 --- /dev/null +++ b/test_regress/t/t_func_recurse2.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_func_recurse2.v b/test_regress/t/t_func_recurse2.v new file mode 100644 index 000000000..6ef719186 --- /dev/null +++ b/test_regress/t/t_func_recurse2.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + function automatic int recurse_1; + input int i; + if (i == 0) recurse_1 = 0; + else recurse_1 = i + recurse_2(i); + endfunction + + function automatic int recurse_2; + input int i; + return recurse_1(i - 1) * 2; + endfunction + + initial begin + if (recurse_1(0) != 0) $stop; + if (recurse_1(3) != (3 + 2*(2 + 2*(1)))) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_func_recurse_param.out b/test_regress/t/t_func_recurse_param.out new file mode 100644 index 000000000..102d49d6f --- /dev/null +++ b/test_regress/t/t_func_recurse_param.out @@ -0,0 +1,16 @@ +%Error-UNSUPPORTED: t/t_func_recurse_param.v:9:27: Unsupported: Recursive function or task call: 'recurse_self' + : ... In instance t + 9 | function automatic int recurse_self; + | ^~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: t/t_func_recurse_param.v:15:26: Expecting expression to be constant, but can't determine constant for FUNCREF 'recurse_self' + : ... In instance t + t/t_func_recurse_param.v:9:27: ... Location of non-constant FUNC 'recurse_self': Unsupported: Recursive constant functions + 15 | localparam int ZERO = recurse_self(0); + | ^~~~~~~~~~~~ +%Error: t/t_func_recurse_param.v:16:28: Expecting expression to be constant, but can't determine constant for FUNCREF 'recurse_self' + : ... In instance t + t/t_func_recurse_param.v:9:27: ... Location of non-constant FUNC 'recurse_self': Unsupported: Recursive constant functions + 16 | localparam int ELEVEN = recurse_self(3); + | ^~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_func_recurse_param.pl b/test_regress/t/t_func_recurse_param.pl new file mode 100755 index 000000000..be66c40e6 --- /dev/null +++ b/test_regress/t/t_func_recurse_param.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_func_recurse_param.v b/test_regress/t/t_func_recurse_param.v new file mode 100644 index 000000000..0082b0f20 --- /dev/null +++ b/test_regress/t/t_func_recurse_param.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + function automatic int recurse_self; + input int i; + if (i == 0) recurse_self = 0; + else recurse_self = i + recurse_self(i - 1) * 2; + endfunction + + localparam int ZERO = recurse_self(0); + localparam int ELEVEN = recurse_self(3); + + initial begin + if (ZERO != 0) $stop; + if (ELEVEN != 11) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_func_recurse_param_bad.out b/test_regress/t/t_func_recurse_param_bad.out new file mode 100644 index 000000000..121ee90f9 --- /dev/null +++ b/test_regress/t/t_func_recurse_param_bad.out @@ -0,0 +1,11 @@ +%Error-UNSUPPORTED: t/t_func_recurse_param_bad.v:9:27: Unsupported: Recursive function or task call: 'recurse_self' + : ... In instance t + 9 | function automatic int recurse_self; + | ^~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: t/t_func_recurse_param_bad.v:15:26: Expecting expression to be constant, but can't determine constant for FUNCREF 'recurse_self' + : ... In instance t + t/t_func_recurse_param_bad.v:9:27: ... Location of non-constant FUNC 'recurse_self': Unsupported: Recursive constant functions + 15 | localparam int HUGE = recurse_self(10000); + | ^~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_func_recurse_param_bad.pl b/test_regress/t/t_func_recurse_param_bad.pl new file mode 100755 index 000000000..a5846c699 --- /dev/null +++ b/test_regress/t/t_func_recurse_param_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_func_bad3.v b/test_regress/t/t_func_recurse_param_bad.v similarity index 50% rename from test_regress/t/t_func_bad3.v rename to test_regress/t/t_func_recurse_param_bad.v index 9b8d672f0..eb7ff29b2 100644 --- a/test_regress/t/t_func_bad3.v +++ b/test_regress/t/t_func_recurse_param_bad.v @@ -6,10 +6,18 @@ module t; - function recurse_self; - input i; + function automatic int recurse_self; + input int i; if (i == 0) recurse_self = 0; - else recurse_self = recurse_self(i - 1) + 1; + else recurse_self = i + recurse_self(i - 1) * 2; endfunction + localparam int HUGE = recurse_self(10000); // too much recursion + + initial begin + $display(HUGE); + $write("*-* All Finished *-*\n"); + $finish; + end + endmodule diff --git a/test_regress/t/t_func_tasknsvar_bad.out b/test_regress/t/t_func_tasknsvar_bad.out index 723df5dc4..241d8b71a 100644 --- a/test_regress/t/t_func_tasknsvar_bad.out +++ b/test_regress/t/t_func_tasknsvar_bad.out @@ -2,7 +2,7 @@ 16 | foo(bus_we_select_from[2]); | ^ ... For error description see https://verilator.org/warn/TASKNSVAR?v=latest -%Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varScopep && !m_varScopep->brokeExists()' @ ../V3AstNodes.cpp:51 +%Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ../V3AstNodes.cpp:64 10 | sig = '1; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_hier_block_sc_trace_fst.out b/test_regress/t/t_hier_block_sc_trace_fst.out new file mode 100644 index 000000000..0594e8107 --- /dev/null +++ b/test_regress/t/t_hier_block_sc_trace_fst.out @@ -0,0 +1,6919 @@ +$date + Tue Feb 22 23:52:17 2022 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var wire 8 " out0 [7:0] $end +$var wire 8 # out1 [7:0] $end +$var wire 8 $ out2 [7:0] $end +$var wire 8 % out3 [7:0] $end +$var wire 8 & out3_2 [7:0] $end +$var wire 8 ' out5 [7:0] $end +$var wire 8 ( out6 [7:0] $end +$var int 32 ) count [31:0] $end +$scope module i_delay0 $end +$var wire 1 ! clk $end +$var wire 8 % in [7:0] $end +$var wire 8 ' out [7:0] $end +$upscope $end +$scope module i_delay1 $end +$var wire 1 ! clk $end +$var wire 8 ' in [7:0] $end +$var wire 8 ( out [7:0] $end +$upscope $end +$scope module i_sub0 $end +$var wire 1 ! clk $end +$var wire 8 % in [7:0] $end +$var wire 8 " out [7:0] $end +$scope module i_sub0 $end +$var wire 1 ! clk $end +$var wire 8 % in [7:0] $end +$var wire 8 " out [7:0] $end +$upscope $end +$upscope $end +$scope module i_sub1 $end +$var wire 1 ! clk $end +$var wire 8 " in [7:0] $end +$var wire 8 # out [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var wire 1 ! clk $end +$var wire 8 # in [7:0] $end +$var wire 8 $ out [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 1 ! clk $end +$var wire 8 $ in [7:0] $end +$var wire 8 % out [7:0] $end +$upscope $end +$scope module i_sub3_2 $end +$var wire 1 ! clk $end +$var wire 8 $ in [7:0] $end +$var wire 8 & out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_delay0 $end +$var wire 1 * clk $end +$var wire 8 + in [7:0] $end +$var wire 8 , out [7:0] $end +$scope module delay_2 $end +$var parameter 32 - WIDTH [31:0] $end +$var wire 1 * clk $end +$var wire 8 + in [7:0] $end +$var wire 8 , out [7:0] $end +$var logic 8 . tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 / N [31:0] $end +$var parameter 32 - WIDTH [31:0] $end +$var wire 1 * clk $end +$var wire 8 . in [7:0] $end +$var wire 8 , out [7:0] $end +$var logic 8 0 tmp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_delay1 $end +$var wire 1 1 clk $end +$var wire 8 2 in [7:0] $end +$var wire 8 3 out [7:0] $end +$scope module delay_9 $end +$var parameter 32 4 WIDTH [31:0] $end +$var wire 1 1 clk $end +$var wire 8 2 in [7:0] $end +$var wire 8 3 out [7:0] $end +$var logic 8 5 tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 6 N [31:0] $end +$var parameter 32 4 WIDTH [31:0] $end +$var wire 1 1 clk $end +$var wire 8 5 in [7:0] $end +$var wire 8 3 out [7:0] $end +$var logic 8 7 tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 8 N [31:0] $end +$var parameter 32 4 WIDTH [31:0] $end +$var wire 1 1 clk $end +$var wire 8 7 in [7:0] $end +$var wire 8 3 out [7:0] $end +$var logic 8 9 tmp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub0.i_sub0 $end +$var wire 1 : clk $end +$var wire 8 ; in [7:0] $end +$var wire 8 < out [7:0] $end +$scope module sub0 $end +$var wire 1 : clk $end +$var wire 8 ; in [7:0] $end +$var wire 8 < out [7:0] $end +$var logic 8 = ff [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub1 $end +$var wire 1 > clk $end +$var wire 8 ? in [7:0] $end +$var wire 8 @ out [7:0] $end +$scope module sub1 $end +$var wire 1 > clk $end +$var wire 8 ? in [7:0] $end +$var wire 8 @ out [7:0] $end +$var logic 8 A ff [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2 $end +$var wire 1 B clk $end +$var wire 8 C in [7:0] $end +$var wire 8 D out [7:0] $end +$scope module sub2 $end +$var wire 1 B clk $end +$var wire 8 C in [7:0] $end +$var wire 8 D out [7:0] $end +$var logic 8 E ff [7:0] $end +$scope module i_sub3 $end +$var wire 8 E in_wire [7:0] $end +$var wire 8 F out_1 [7:0] $end +$var wire 8 G out_2 [7:0] $end +$scope module i_sub3 $end +$var wire 1 B clk $end +$var wire 8 E in [7:0] $end +$var wire 8 F out [7:0] $end +$upscope $end +$scope module i_sub3_2 $end +$var wire 1 B clk $end +$var wire 8 E in [7:0] $end +$var wire 8 G out [7:0] $end +$upscope $end +$scope interface in $end +$var wire 1 B clk $end +$var logic 8 E data [7:0] $end +$upscope $end +$scope interface out $end +$var wire 1 B clk $end +$var logic 8 F data [7:0] $end +$upscope $end +$upscope $end +$scope interface in_ifs $end +$var wire 1 B clk $end +$var logic 8 E data [7:0] $end +$upscope $end +$scope interface out_ifs $end +$var wire 1 B clk $end +$var logic 8 F data [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end +$var wire 1 H clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end +$scope module sub3_c $end +$var parameter 32 K UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 L UNPACKED_ARRAY[1] [31:0] $end +$var wire 1 H clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end +$var logic 8 M ff [7:0] $end +$var wire 8 N out4 [7:0] $end +$var wire 8 O out4_2 [7:0] $end +$scope module i_sub4_0 $end +$var wire 1 H clk $end +$var wire 8 M in [7:0] $end +$var wire 8 N out [7:0] $end +$upscope $end +$scope module i_sub4_1 $end +$var wire 1 H clk $end +$var wire 8 M in [7:0] $end +$var wire 8 O out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end +$var wire 1 P clk $end +$var wire 8 Q in [7:0] $end +$var wire 8 R out [7:0] $end +$scope module sub4_2 $end +$var wire 1 P clk $end +$var wire 8 Q in [7:0] $end +$var wire 8 R out [7:0] $end +$var logic 8 S ff [7:0] $end +$var logic 128 T sub5_in[0][0] [127:0] $end +$var logic 128 U sub5_in[0][1] [127:0] $end +$var logic 128 V sub5_in[0][2] [127:0] $end +$var logic 128 W sub5_in[1][0] [127:0] $end +$var logic 128 X sub5_in[1][1] [127:0] $end +$var logic 128 Y sub5_in[1][2] [127:0] $end +$var wire 8 Z sub5_out[0][0] [7:0] $end +$var wire 8 [ sub5_out[0][1] [7:0] $end +$var wire 8 \ sub5_out[0][2] [7:0] $end +$var wire 8 ] sub5_out[1][0] [7:0] $end +$var wire 8 ^ sub5_out[1][1] [7:0] $end +$var wire 8 _ sub5_out[1][2] [7:0] $end +$var int 32 ` count [31:0] $end +$scope module i_sub5 $end +$var wire 1 P clk $end +$var wire 128 a in[0][0] [127:0] $end +$var wire 128 b in[0][1] [127:0] $end +$var wire 128 c in[0][2] [127:0] $end +$var wire 128 d in[1][0] [127:0] $end +$var wire 128 e in[1][1] [127:0] $end +$var wire 128 f in[1][2] [127:0] $end +$var wire 8 g out[0][0] [7:0] $end +$var wire 8 h out[0][1] [7:0] $end +$var wire 8 i out[0][2] [7:0] $end +$var wire 8 j out[1][0] [7:0] $end +$var wire 8 k out[1][1] [7:0] $end +$var wire 8 l out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 m i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 n j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 o exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end +$var wire 1 p clk $end +$var wire 128 q in[0][0] [127:0] $end +$var wire 128 r in[0][1] [127:0] $end +$var wire 128 s in[0][2] [127:0] $end +$var wire 128 t in[1][0] [127:0] $end +$var wire 128 u in[1][1] [127:0] $end +$var wire 128 v in[1][2] [127:0] $end +$var wire 8 w out[0][0] [7:0] $end +$var wire 8 x out[0][1] [7:0] $end +$var wire 8 y out[0][2] [7:0] $end +$var wire 8 z out[1][0] [7:0] $end +$var wire 8 { out[1][1] [7:0] $end +$var wire 8 | out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 p clk $end +$var wire 128 q in[0][0] [127:0] $end +$var wire 128 r in[0][1] [127:0] $end +$var wire 128 s in[0][2] [127:0] $end +$var wire 128 t in[1][0] [127:0] $end +$var wire 128 u in[1][1] [127:0] $end +$var wire 128 v in[1][2] [127:0] $end +$var wire 8 w out[0][0] [7:0] $end +$var wire 8 x out[0][1] [7:0] $end +$var wire 8 y out[0][2] [7:0] $end +$var wire 8 z out[1][0] [7:0] $end +$var wire 8 { out[1][1] [7:0] $end +$var wire 8 | out[1][2] [7:0] $end +$var int 32 } count [31:0] $end +$var wire 8 ~ val0[0] [7:0] $end +$var wire 8 !! val0[1] [7:0] $end +$var wire 8 "! val1[0] [7:0] $end +$var wire 8 #! val1[1] [7:0] $end +$var wire 8 $! val2[0] [7:0] $end +$var wire 8 %! val2[1] [7:0] $end +$var wire 8 &! val3[0] [7:0] $end +$var wire 8 '! val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 (! P0 [31:0] $end +$var parameter 32 )! P1 [31:0] $end +$var wire 8 *! out[0] [7:0] $end +$var wire 8 +! out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 (! P0 [31:0] $end +$var parameter 32 )! P1 [31:0] $end +$var wire 8 ,! out[0] [7:0] $end +$var wire 8 -! out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 (! P0 [31:0] $end +$var parameter 32 )! P1 [31:0] $end +$var wire 8 .! out[0] [7:0] $end +$var wire 8 /! out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 0! out[0] [7:0] $end +$var wire 8 1! out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 2! i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 3! j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 4! exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end +$var wire 8 5! out[0] [7:0] $end +$var wire 8 6! out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 7! P0 [31:0] $end +$var wire 8 5! out[0] [7:0] $end +$var wire 8 6! out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end +$var wire 1 8! clk $end +$var wire 8 9! in [7:0] $end +$var wire 8 :! out [7:0] $end +$scope module sub4_b $end +$var wire 1 8! clk $end +$var wire 8 9! in [7:0] $end +$var wire 8 :! out [7:0] $end +$var logic 8 ;! ff [7:0] $end +$var logic 128 ! sub5_in[0][2] [127:0] $end +$var logic 128 ?! sub5_in[1][0] [127:0] $end +$var logic 128 @! sub5_in[1][1] [127:0] $end +$var logic 128 A! sub5_in[1][2] [127:0] $end +$var wire 8 B! sub5_out[0][0] [7:0] $end +$var wire 8 C! sub5_out[0][1] [7:0] $end +$var wire 8 D! sub5_out[0][2] [7:0] $end +$var wire 8 E! sub5_out[1][0] [7:0] $end +$var wire 8 F! sub5_out[1][1] [7:0] $end +$var wire 8 G! sub5_out[1][2] [7:0] $end +$var int 32 H! count [31:0] $end +$scope module i_sub5 $end +$var wire 1 8! clk $end +$var wire 128 I! in[0][0] [127:0] $end +$var wire 128 J! in[0][1] [127:0] $end +$var wire 128 K! in[0][2] [127:0] $end +$var wire 128 L! in[1][0] [127:0] $end +$var wire 128 M! in[1][1] [127:0] $end +$var wire 128 N! in[1][2] [127:0] $end +$var wire 8 O! out[0][0] [7:0] $end +$var wire 8 P! out[0][1] [7:0] $end +$var wire 8 Q! out[0][2] [7:0] $end +$var wire 8 R! out[1][0] [7:0] $end +$var wire 8 S! out[1][1] [7:0] $end +$var wire 8 T! out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 U! i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 V! j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 W! exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end +$var wire 1 X! clk $end +$var wire 128 Y! in[0][0] [127:0] $end +$var wire 128 Z! in[0][1] [127:0] $end +$var wire 128 [! in[0][2] [127:0] $end +$var wire 128 \! in[1][0] [127:0] $end +$var wire 128 ]! in[1][1] [127:0] $end +$var wire 128 ^! in[1][2] [127:0] $end +$var wire 8 _! out[0][0] [7:0] $end +$var wire 8 `! out[0][1] [7:0] $end +$var wire 8 a! out[0][2] [7:0] $end +$var wire 8 b! out[1][0] [7:0] $end +$var wire 8 c! out[1][1] [7:0] $end +$var wire 8 d! out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 X! clk $end +$var wire 128 Y! in[0][0] [127:0] $end +$var wire 128 Z! in[0][1] [127:0] $end +$var wire 128 [! in[0][2] [127:0] $end +$var wire 128 \! in[1][0] [127:0] $end +$var wire 128 ]! in[1][1] [127:0] $end +$var wire 128 ^! in[1][2] [127:0] $end +$var wire 8 _! out[0][0] [7:0] $end +$var wire 8 `! out[0][1] [7:0] $end +$var wire 8 a! out[0][2] [7:0] $end +$var wire 8 b! out[1][0] [7:0] $end +$var wire 8 c! out[1][1] [7:0] $end +$var wire 8 d! out[1][2] [7:0] $end +$var int 32 e! count [31:0] $end +$var wire 8 f! val0[0] [7:0] $end +$var wire 8 g! val0[1] [7:0] $end +$var wire 8 h! val1[0] [7:0] $end +$var wire 8 i! val1[1] [7:0] $end +$var wire 8 j! val2[0] [7:0] $end +$var wire 8 k! val2[1] [7:0] $end +$var wire 8 l! val3[0] [7:0] $end +$var wire 8 m! val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 n! P0 [31:0] $end +$var parameter 32 o! P1 [31:0] $end +$var wire 8 p! out[0] [7:0] $end +$var wire 8 q! out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 n! P0 [31:0] $end +$var parameter 32 o! P1 [31:0] $end +$var wire 8 r! out[0] [7:0] $end +$var wire 8 s! out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 n! P0 [31:0] $end +$var parameter 32 o! P1 [31:0] $end +$var wire 8 t! out[0] [7:0] $end +$var wire 8 u! out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 v! out[0] [7:0] $end +$var wire 8 w! out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 x! i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 y! j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 z! exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end +$var wire 8 {! out[0] [7:0] $end +$var wire 8 |! out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 }! P0 [31:0] $end +$var wire 8 {! out[0] [7:0] $end +$var wire 8 |! out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2 $end +$var wire 1 ~! clk $end +$var wire 8 !" in [7:0] $end +$var wire 8 "" out [7:0] $end +$scope module sub3_2 $end +$var parameter 32 #" UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 $" UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 %" UNUSED [15:0] $end +$var wire 1 ~! clk $end +$var wire 8 !" in [7:0] $end +$var wire 8 "" out [7:0] $end +$var logic 8 &" ff [7:0] $end +$var wire 8 '" out4 [7:0] $end +$var wire 8 (" out4_2 [7:0] $end +$scope module i_sub4_0 $end +$var wire 1 ~! clk $end +$var wire 8 &" in [7:0] $end +$var wire 8 '" out [7:0] $end +$upscope $end +$scope module i_sub4_1 $end +$var wire 1 ~! clk $end +$var wire 8 &" in [7:0] $end +$var wire 8 (" out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end +$var wire 1 )" clk $end +$var wire 8 *" in [7:0] $end +$var wire 8 +" out [7:0] $end +$scope module sub4_2 $end +$var wire 1 )" clk $end +$var wire 8 *" in [7:0] $end +$var wire 8 +" out [7:0] $end +$var logic 8 ," ff [7:0] $end +$var logic 128 -" sub5_in[0][0] [127:0] $end +$var logic 128 ." sub5_in[0][1] [127:0] $end +$var logic 128 /" sub5_in[0][2] [127:0] $end +$var logic 128 0" sub5_in[1][0] [127:0] $end +$var logic 128 1" sub5_in[1][1] [127:0] $end +$var logic 128 2" sub5_in[1][2] [127:0] $end +$var wire 8 3" sub5_out[0][0] [7:0] $end +$var wire 8 4" sub5_out[0][1] [7:0] $end +$var wire 8 5" sub5_out[0][2] [7:0] $end +$var wire 8 6" sub5_out[1][0] [7:0] $end +$var wire 8 7" sub5_out[1][1] [7:0] $end +$var wire 8 8" sub5_out[1][2] [7:0] $end +$var int 32 9" count [31:0] $end +$scope module i_sub5 $end +$var wire 1 )" clk $end +$var wire 128 :" in[0][0] [127:0] $end +$var wire 128 ;" in[0][1] [127:0] $end +$var wire 128 <" in[0][2] [127:0] $end +$var wire 128 =" in[1][0] [127:0] $end +$var wire 128 >" in[1][1] [127:0] $end +$var wire 128 ?" in[1][2] [127:0] $end +$var wire 8 @" out[0][0] [7:0] $end +$var wire 8 A" out[0][1] [7:0] $end +$var wire 8 B" out[0][2] [7:0] $end +$var wire 8 C" out[1][0] [7:0] $end +$var wire 8 D" out[1][1] [7:0] $end +$var wire 8 E" out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 F" i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 G" j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 H" exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end +$var wire 1 I" clk $end +$var wire 128 J" in[0][0] [127:0] $end +$var wire 128 K" in[0][1] [127:0] $end +$var wire 128 L" in[0][2] [127:0] $end +$var wire 128 M" in[1][0] [127:0] $end +$var wire 128 N" in[1][1] [127:0] $end +$var wire 128 O" in[1][2] [127:0] $end +$var wire 8 P" out[0][0] [7:0] $end +$var wire 8 Q" out[0][1] [7:0] $end +$var wire 8 R" out[0][2] [7:0] $end +$var wire 8 S" out[1][0] [7:0] $end +$var wire 8 T" out[1][1] [7:0] $end +$var wire 8 U" out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 I" clk $end +$var wire 128 J" in[0][0] [127:0] $end +$var wire 128 K" in[0][1] [127:0] $end +$var wire 128 L" in[0][2] [127:0] $end +$var wire 128 M" in[1][0] [127:0] $end +$var wire 128 N" in[1][1] [127:0] $end +$var wire 128 O" in[1][2] [127:0] $end +$var wire 8 P" out[0][0] [7:0] $end +$var wire 8 Q" out[0][1] [7:0] $end +$var wire 8 R" out[0][2] [7:0] $end +$var wire 8 S" out[1][0] [7:0] $end +$var wire 8 T" out[1][1] [7:0] $end +$var wire 8 U" out[1][2] [7:0] $end +$var int 32 V" count [31:0] $end +$var wire 8 W" val0[0] [7:0] $end +$var wire 8 X" val0[1] [7:0] $end +$var wire 8 Y" val1[0] [7:0] $end +$var wire 8 Z" val1[1] [7:0] $end +$var wire 8 [" val2[0] [7:0] $end +$var wire 8 \" val2[1] [7:0] $end +$var wire 8 ]" val3[0] [7:0] $end +$var wire 8 ^" val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 _" P0 [31:0] $end +$var parameter 32 `" P1 [31:0] $end +$var wire 8 a" out[0] [7:0] $end +$var wire 8 b" out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 _" P0 [31:0] $end +$var parameter 32 `" P1 [31:0] $end +$var wire 8 c" out[0] [7:0] $end +$var wire 8 d" out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 _" P0 [31:0] $end +$var parameter 32 `" P1 [31:0] $end +$var wire 8 e" out[0] [7:0] $end +$var wire 8 f" out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 g" out[0] [7:0] $end +$var wire 8 h" out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 i" i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 j" j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 k" exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end +$var wire 8 l" out[0] [7:0] $end +$var wire 8 m" out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 n" P0 [31:0] $end +$var wire 8 l" out[0] [7:0] $end +$var wire 8 m" out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end +$var wire 1 o" clk $end +$var wire 8 p" in [7:0] $end +$var wire 8 q" out [7:0] $end +$scope module sub4_b $end +$var wire 1 o" clk $end +$var wire 8 p" in [7:0] $end +$var wire 8 q" out [7:0] $end +$var logic 8 r" ff [7:0] $end +$var logic 128 s" sub5_in[0][0] [127:0] $end +$var logic 128 t" sub5_in[0][1] [127:0] $end +$var logic 128 u" sub5_in[0][2] [127:0] $end +$var logic 128 v" sub5_in[1][0] [127:0] $end +$var logic 128 w" sub5_in[1][1] [127:0] $end +$var logic 128 x" sub5_in[1][2] [127:0] $end +$var wire 8 y" sub5_out[0][0] [7:0] $end +$var wire 8 z" sub5_out[0][1] [7:0] $end +$var wire 8 {" sub5_out[0][2] [7:0] $end +$var wire 8 |" sub5_out[1][0] [7:0] $end +$var wire 8 }" sub5_out[1][1] [7:0] $end +$var wire 8 ~" sub5_out[1][2] [7:0] $end +$var int 32 !# count [31:0] $end +$scope module i_sub5 $end +$var wire 1 o" clk $end +$var wire 128 "# in[0][0] [127:0] $end +$var wire 128 ## in[0][1] [127:0] $end +$var wire 128 $# in[0][2] [127:0] $end +$var wire 128 %# in[1][0] [127:0] $end +$var wire 128 &# in[1][1] [127:0] $end +$var wire 128 '# in[1][2] [127:0] $end +$var wire 8 (# out[0][0] [7:0] $end +$var wire 8 )# out[0][1] [7:0] $end +$var wire 8 *# out[0][2] [7:0] $end +$var wire 8 +# out[1][0] [7:0] $end +$var wire 8 ,# out[1][1] [7:0] $end +$var wire 8 -# out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 .# i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 /# j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 0# exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end +$var wire 1 1# clk $end +$var wire 128 2# in[0][0] [127:0] $end +$var wire 128 3# in[0][1] [127:0] $end +$var wire 128 4# in[0][2] [127:0] $end +$var wire 128 5# in[1][0] [127:0] $end +$var wire 128 6# in[1][1] [127:0] $end +$var wire 128 7# in[1][2] [127:0] $end +$var wire 8 8# out[0][0] [7:0] $end +$var wire 8 9# out[0][1] [7:0] $end +$var wire 8 :# out[0][2] [7:0] $end +$var wire 8 ;# out[1][0] [7:0] $end +$var wire 8 <# out[1][1] [7:0] $end +$var wire 8 =# out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 1# clk $end +$var wire 128 2# in[0][0] [127:0] $end +$var wire 128 3# in[0][1] [127:0] $end +$var wire 128 4# in[0][2] [127:0] $end +$var wire 128 5# in[1][0] [127:0] $end +$var wire 128 6# in[1][1] [127:0] $end +$var wire 128 7# in[1][2] [127:0] $end +$var wire 8 8# out[0][0] [7:0] $end +$var wire 8 9# out[0][1] [7:0] $end +$var wire 8 :# out[0][2] [7:0] $end +$var wire 8 ;# out[1][0] [7:0] $end +$var wire 8 <# out[1][1] [7:0] $end +$var wire 8 =# out[1][2] [7:0] $end +$var int 32 ># count [31:0] $end +$var wire 8 ?# val0[0] [7:0] $end +$var wire 8 @# val0[1] [7:0] $end +$var wire 8 A# val1[0] [7:0] $end +$var wire 8 B# val1[1] [7:0] $end +$var wire 8 C# val2[0] [7:0] $end +$var wire 8 D# val2[1] [7:0] $end +$var wire 8 E# val3[0] [7:0] $end +$var wire 8 F# val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 G# P0 [31:0] $end +$var parameter 32 H# P1 [31:0] $end +$var wire 8 I# out[0] [7:0] $end +$var wire 8 J# out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 G# P0 [31:0] $end +$var parameter 32 H# P1 [31:0] $end +$var wire 8 K# out[0] [7:0] $end +$var wire 8 L# out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 G# P0 [31:0] $end +$var parameter 32 H# P1 [31:0] $end +$var wire 8 M# out[0] [7:0] $end +$var wire 8 N# out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 O# out[0] [7:0] $end +$var wire 8 P# out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 Q# i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 R# j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 S# exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end +$var wire 8 T# out[0] [7:0] $end +$var wire 8 U# out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 V# P0 [31:0] $end +$var wire 8 T# out[0] [7:0] $end +$var wire 8 U# out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3 $end +$var wire 1 W# clk $end +$var wire 8 X# in [7:0] $end +$var wire 8 Y# out [7:0] $end +$scope module sub3_d $end +$var parameter 32 Z# UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 [# UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 \# UNUSED [15:0] $end +$var wire 1 W# clk $end +$var wire 8 X# in [7:0] $end +$var wire 8 Y# out [7:0] $end +$var logic 8 ]# ff [7:0] $end +$var wire 8 ^# out4 [7:0] $end +$var wire 8 _# out4_2 [7:0] $end +$scope module i_sub4_0 $end +$var wire 1 W# clk $end +$var wire 8 ]# in [7:0] $end +$var wire 8 ^# out [7:0] $end +$upscope $end +$scope module i_sub4_1 $end +$var wire 1 W# clk $end +$var wire 8 ]# in [7:0] $end +$var wire 8 _# out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_0 $end +$var wire 1 `# clk $end +$var wire 8 a# in [7:0] $end +$var wire 8 b# out [7:0] $end +$scope module sub4_2 $end +$var wire 1 `# clk $end +$var wire 8 a# in [7:0] $end +$var wire 8 b# out [7:0] $end +$var logic 8 c# ff [7:0] $end +$var logic 128 d# sub5_in[0][0] [127:0] $end +$var logic 128 e# sub5_in[0][1] [127:0] $end +$var logic 128 f# sub5_in[0][2] [127:0] $end +$var logic 128 g# sub5_in[1][0] [127:0] $end +$var logic 128 h# sub5_in[1][1] [127:0] $end +$var logic 128 i# sub5_in[1][2] [127:0] $end +$var wire 8 j# sub5_out[0][0] [7:0] $end +$var wire 8 k# sub5_out[0][1] [7:0] $end +$var wire 8 l# sub5_out[0][2] [7:0] $end +$var wire 8 m# sub5_out[1][0] [7:0] $end +$var wire 8 n# sub5_out[1][1] [7:0] $end +$var wire 8 o# sub5_out[1][2] [7:0] $end +$var int 32 p# count [31:0] $end +$scope module i_sub5 $end +$var wire 1 `# clk $end +$var wire 128 q# in[0][0] [127:0] $end +$var wire 128 r# in[0][1] [127:0] $end +$var wire 128 s# in[0][2] [127:0] $end +$var wire 128 t# in[1][0] [127:0] $end +$var wire 128 u# in[1][1] [127:0] $end +$var wire 128 v# in[1][2] [127:0] $end +$var wire 8 w# out[0][0] [7:0] $end +$var wire 8 x# out[0][1] [7:0] $end +$var wire 8 y# out[0][2] [7:0] $end +$var wire 8 z# out[1][0] [7:0] $end +$var wire 8 {# out[1][1] [7:0] $end +$var wire 8 |# out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 }# i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 ~# j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 !$ exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end +$var wire 1 "$ clk $end +$var wire 128 #$ in[0][0] [127:0] $end +$var wire 128 $$ in[0][1] [127:0] $end +$var wire 128 %$ in[0][2] [127:0] $end +$var wire 128 &$ in[1][0] [127:0] $end +$var wire 128 '$ in[1][1] [127:0] $end +$var wire 128 ($ in[1][2] [127:0] $end +$var wire 8 )$ out[0][0] [7:0] $end +$var wire 8 *$ out[0][1] [7:0] $end +$var wire 8 +$ out[0][2] [7:0] $end +$var wire 8 ,$ out[1][0] [7:0] $end +$var wire 8 -$ out[1][1] [7:0] $end +$var wire 8 .$ out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 "$ clk $end +$var wire 128 #$ in[0][0] [127:0] $end +$var wire 128 $$ in[0][1] [127:0] $end +$var wire 128 %$ in[0][2] [127:0] $end +$var wire 128 &$ in[1][0] [127:0] $end +$var wire 128 '$ in[1][1] [127:0] $end +$var wire 128 ($ in[1][2] [127:0] $end +$var wire 8 )$ out[0][0] [7:0] $end +$var wire 8 *$ out[0][1] [7:0] $end +$var wire 8 +$ out[0][2] [7:0] $end +$var wire 8 ,$ out[1][0] [7:0] $end +$var wire 8 -$ out[1][1] [7:0] $end +$var wire 8 .$ out[1][2] [7:0] $end +$var int 32 /$ count [31:0] $end +$var wire 8 0$ val0[0] [7:0] $end +$var wire 8 1$ val0[1] [7:0] $end +$var wire 8 2$ val1[0] [7:0] $end +$var wire 8 3$ val1[1] [7:0] $end +$var wire 8 4$ val2[0] [7:0] $end +$var wire 8 5$ val2[1] [7:0] $end +$var wire 8 6$ val3[0] [7:0] $end +$var wire 8 7$ val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 8$ P0 [31:0] $end +$var parameter 32 9$ P1 [31:0] $end +$var wire 8 :$ out[0] [7:0] $end +$var wire 8 ;$ out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 8$ P0 [31:0] $end +$var parameter 32 9$ P1 [31:0] $end +$var wire 8 <$ out[0] [7:0] $end +$var wire 8 =$ out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 8$ P0 [31:0] $end +$var parameter 32 9$ P1 [31:0] $end +$var wire 8 >$ out[0] [7:0] $end +$var wire 8 ?$ out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 @$ out[0] [7:0] $end +$var wire 8 A$ out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 B$ i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 C$ j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 D$ exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end +$var wire 8 E$ out[0] [7:0] $end +$var wire 8 F$ out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 G$ P0 [31:0] $end +$var wire 8 E$ out[0] [7:0] $end +$var wire 8 F$ out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_1 $end +$var wire 1 H$ clk $end +$var wire 8 I$ in [7:0] $end +$var wire 8 J$ out [7:0] $end +$scope module sub4_b $end +$var wire 1 H$ clk $end +$var wire 8 I$ in [7:0] $end +$var wire 8 J$ out [7:0] $end +$var logic 8 K$ ff [7:0] $end +$var logic 128 L$ sub5_in[0][0] [127:0] $end +$var logic 128 M$ sub5_in[0][1] [127:0] $end +$var logic 128 N$ sub5_in[0][2] [127:0] $end +$var logic 128 O$ sub5_in[1][0] [127:0] $end +$var logic 128 P$ sub5_in[1][1] [127:0] $end +$var logic 128 Q$ sub5_in[1][2] [127:0] $end +$var wire 8 R$ sub5_out[0][0] [7:0] $end +$var wire 8 S$ sub5_out[0][1] [7:0] $end +$var wire 8 T$ sub5_out[0][2] [7:0] $end +$var wire 8 U$ sub5_out[1][0] [7:0] $end +$var wire 8 V$ sub5_out[1][1] [7:0] $end +$var wire 8 W$ sub5_out[1][2] [7:0] $end +$var int 32 X$ count [31:0] $end +$scope module i_sub5 $end +$var wire 1 H$ clk $end +$var wire 128 Y$ in[0][0] [127:0] $end +$var wire 128 Z$ in[0][1] [127:0] $end +$var wire 128 [$ in[0][2] [127:0] $end +$var wire 128 \$ in[1][0] [127:0] $end +$var wire 128 ]$ in[1][1] [127:0] $end +$var wire 128 ^$ in[1][2] [127:0] $end +$var wire 8 _$ out[0][0] [7:0] $end +$var wire 8 `$ out[0][1] [7:0] $end +$var wire 8 a$ out[0][2] [7:0] $end +$var wire 8 b$ out[1][0] [7:0] $end +$var wire 8 c$ out[1][1] [7:0] $end +$var wire 8 d$ out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 e$ i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 f$ j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 g$ exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end 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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n$ +b00000000000000000000000000010001 u$ +b00000001 o +b00000001 W! +b00000001 H" +b00000001 0# +b00000001 !$ +b00000001 g$ +b00011101 $ +b00011101 D +b00011101 F +b00011101 G +b00011101 J +b00011101 N +b00011101 O +b00011101 R +b00011101 S +b00011101 :! +b00011101 ;! +b00011101 !" +b00011101 X# +b00010101 ( +b00010101 3 +b00010101 9 +b00011011 % +b00011011 & +b00011011 + +b00011011 ; +b00011011 "" +b00011011 '" +b00011011 (" +b00011011 +" +b00011011 ," +b00011011 q" +b00011011 r" +b00011011 Y# +b00011011 ^# +b00011011 _# +b00011011 b# +b00011011 c# +b00011011 J$ +b00011011 K$ +b00011001 C +b00011001 A +b00011001 @ +b00011001 # +b00011000 ' +b00011000 , +b00011000 0 +b00011000 2 +#171 +#172 +#173 +#174 diff --git a/test_regress/t/t_hier_block_sc_trace_fst.pl b/test_regress/t/t_hier_block_sc_trace_fst.pl new file mode 100755 index 000000000..6c8dd260e --- /dev/null +++ b/test_regress/t/t_hier_block_sc_trace_fst.pl @@ -0,0 +1,44 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +clean_objs(); + +top_filename("t/t_hier_block.v"); + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performace wise, but ok. +scenarios(vlt_all => 1); + +compile( + v_flags2 => ['t/t_hier_block.cpp'], + verilator_flags2 => ['--sc', + '--stats', + '--hierarchical', + ($Self->{vltmt} ? ' --threads 6' : ''), + '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + "--CFLAGS", '"-O0 -ggdb"', + "--trace-fst" + ], + ); + +execute( + check_finished => 1, + ); + +file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); +file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); +file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); +file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 13); +file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); + +fst_identical($Self->trace_filename, $Self->{golden_filename}); +ok(1); +1; diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.out b/test_regress/t/t_hier_block_sc_trace_vcd.out new file mode 100644 index 000000000..6e0c6affa --- /dev/null +++ b/test_regress/t/t_hier_block_sc_trace_vcd.out @@ -0,0 +1,6913 @@ +$version Generated by VerilatedVcd $end +$date Sun Dec 19 12:27:52 2021 $end +$timescale 1ps $end + + $scope module top $end + $scope module t $end + $var wire 1 # clk $end + $var wire 32 + count [31:0] $end + $var wire 8 $ out0 [7:0] $end + $var wire 8 % out1 [7:0] $end + $var wire 8 & out2 [7:0] $end + $var wire 8 ' out3 [7:0] $end + $var wire 8 * out3_2 [7:0] $end + $var wire 8 ( out5 [7:0] $end + $var wire 8 ) out6 [7:0] $end + $scope module i_delay0 $end + $var wire 1 # clk $end + $var wire 8 ' in [7:0] $end + $var wire 8 ( out [7:0] $end + $upscope $end + $scope module i_delay1 $end + $var wire 1 # clk $end + $var wire 8 ( in [7:0] $end + $var wire 8 ) out [7:0] $end + $upscope $end + $scope module i_sub0 $end + $var wire 1 # clk $end + $var wire 8 ' in [7:0] $end + $var wire 8 $ out [7:0] $end + $scope module i_sub0 $end + $var wire 1 # clk $end + $var wire 8 ' in [7:0] $end + $var wire 8 $ out [7:0] $end + $upscope $end + $upscope $end + $scope module i_sub1 $end + $var wire 1 # clk $end + $var wire 8 $ in [7:0] $end + $var wire 8 % out [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 1 # clk $end + $var wire 8 % in [7:0] $end + $var wire 8 & out [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 1 # clk $end + $var wire 8 & in [7:0] $end + $var wire 8 ' out [7:0] $end + $upscope $end + $scope module i_sub3_2 $end + $var wire 1 # clk $end + $var wire 8 & in [7:0] $end + $var wire 8 * out [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_delay0 $end + $var wire 1 - clk $end + $var wire 8 . in [7:0] $end + $var wire 8 / out [7:0] $end + $scope module delay_2 $end + $var wire 32 2 WIDTH [31:0] $end + $var wire 1 - clk $end + $var wire 8 . in [7:0] $end + $var wire 8 / out [7:0] $end + $var wire 8 0 tmp [7:0] $end + $scope module genblk1 $end + $scope module i_delay $end + $var wire 32 3 N [31:0] $end + $var wire 32 2 WIDTH [31:0] $end + $var wire 1 - clk $end + $var wire 8 0 in [7:0] $end + $var wire 8 / out [7:0] $end + $var wire 8 1 tmp [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_delay1 $end + $var wire 1 8 clk $end + $var wire 8 9 in [7:0] $end + $var wire 8 : out [7:0] $end + $scope module delay_9 $end + $var wire 32 ; WIDTH [31:0] $end + $var wire 1 8 clk $end + $var wire 8 9 in [7:0] $end + $var wire 8 : out [7:0] $end + $var wire 8 5 tmp [7:0] $end + $scope module genblk1 $end + $scope module i_delay $end + $var wire 32 < N [31:0] $end + $var wire 32 ; WIDTH [31:0] $end + $var wire 1 8 clk $end + $var wire 8 5 in [7:0] $end + $var wire 8 : out [7:0] $end + $var wire 8 6 tmp [7:0] $end + $scope module genblk1 $end + $scope module i_delay $end + $var wire 32 = N [31:0] $end + $var wire 32 ; WIDTH [31:0] $end + $var wire 1 8 clk $end + $var wire 8 6 in [7:0] $end + $var wire 8 : out [7:0] $end + $var wire 8 7 tmp [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub0.i_sub0 $end + $var wire 1 ? clk $end + $var wire 8 @ in [7:0] $end + $var wire 8 A out [7:0] $end + $scope module sub0 $end + $var wire 1 ? clk $end + $var wire 8 B ff [7:0] $end + $var wire 8 @ in [7:0] $end + $var wire 8 A out [7:0] $end + $upscope $end + $upscope $end + $scope module top.t.i_sub1 $end + $var wire 1 D clk $end + $var wire 8 E in [7:0] $end + $var wire 8 F out [7:0] $end + $scope module sub1 $end + $var wire 1 D clk $end + $var wire 8 G ff [7:0] $end + $var wire 8 E in [7:0] $end + $var wire 8 F out [7:0] $end + $upscope $end + $upscope $end + $scope module top.t.i_sub2 $end + $var wire 1 I clk $end + $var wire 8 J in [7:0] $end + $var wire 8 K out [7:0] $end + $scope module sub2 $end + $var wire 1 I clk $end + $var wire 8 L ff [7:0] $end + $var wire 8 J in [7:0] $end + $var wire 8 K out [7:0] $end + $scope module i_sub3 $end + $var wire 8 L in_wire [7:0] $end + $var wire 8 M out_1 [7:0] $end + $var wire 8 N out_2 [7:0] $end + $scope module i_sub3 $end + $var wire 1 I clk $end + $var wire 8 L in [7:0] $end + $var wire 8 M out [7:0] $end + $upscope $end + $scope module i_sub3_2 $end + $var wire 1 I clk $end + $var wire 8 L in [7:0] $end + $var wire 8 N out [7:0] $end + $upscope $end + $scope interface in $end + $var wire 1 I clk $end + $var wire 8 L data [7:0] $end + $upscope $end + $scope interface out $end + $var wire 1 I clk $end + $var wire 8 M data [7:0] $end + $upscope $end + $upscope $end + $scope interface in_ifs $end + $var wire 1 I clk $end + $var wire 8 L data [7:0] $end + $upscope $end + $scope interface out_ifs $end + $var wire 1 I clk $end + $var wire 8 M data [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end + $var wire 1 P clk $end + $var wire 8 Q in [7:0] $end + $var wire 8 R out [7:0] $end + $scope module sub3_c $end + $var wire 32 V UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 W UNPACKED_ARRAY[1] [31:0] $end + $var wire 1 P clk $end + $var wire 8 S ff [7:0] $end + $var wire 8 Q in [7:0] $end + $var wire 8 R out [7:0] $end + $var wire 8 T out4 [7:0] $end + $var wire 8 U out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 1 P clk $end + $var wire 8 S in [7:0] $end + $var wire 8 T out [7:0] $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 1 P clk $end + $var wire 8 S in [7:0] $end + $var wire 8 U out [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end + $var wire 1 ! out [7:0] $end + $scope module sub4_2 $end + $var wire 1 ! out [7:0] $end + $var wire 128 Z sub5_in[0][0] [127:0] $end + $var wire 128 ^ sub5_in[0][1] [127:0] $end + $var wire 128 b sub5_in[0][2] [127:0] $end + $var wire 128 f sub5_in[1][0] [127:0] $end + $var wire 128 j sub5_in[1][1] [127:0] $end + $var wire 128 n sub5_in[1][2] [127:0] $end + $var wire 8 0! sub5_out[0][0] [7:0] $end + $var wire 8 1! sub5_out[0][1] [7:0] $end + $var wire 8 2! sub5_out[0][2] [7:0] $end + $var wire 8 3! sub5_out[1][0] [7:0] $end + $var wire 8 4! sub5_out[1][1] [7:0] $end + $var wire 8 5! sub5_out[1][2] [7:0] $end + $scope module i_sub5 $end + $var wire 1 & UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 ?& UNUSED [15:0] $end + $var wire 1 7& clk $end + $var wire 8 :& ff [7:0] $end + $var wire 8 8& in [7:0] $end + $var wire 8 9& out [7:0] $end + $var wire 8 ;& out4 [7:0] $end + $var wire 8 <& out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 1 7& clk $end + $var wire 8 :& in [7:0] $end + $var wire 8 ;& out [7:0] $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 1 7& clk $end + $var wire 8 :& in [7:0] $end + $var wire 8 <& out [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end + $var wire 1 $' clk $end + $var wire 8 %' in [7:0] $end + $var wire 8 &' out [7:0] $end + $scope module sub4_2 $end + $var wire 1 $' clk $end + $var wire 32 Z& count [31:0] $end + $var wire 8 A& ff [7:0] $end + $var wire 8 %' in [7:0] $end + $var wire 8 &' out [7:0] $end + $var wire 128 B& sub5_in[0][0] [127:0] $end + $var wire 128 F& sub5_in[0][1] [127:0] $end + $var wire 128 J& sub5_in[0][2] [127:0] $end + $var wire 128 N& sub5_in[1][0] [127:0] $end + $var wire 128 R& sub5_in[1][1] [127:0] $end + $var wire 128 V& sub5_in[1][2] [127:0] $end + $var wire 8 v& sub5_out[0][0] [7:0] $end + $var wire 8 w& sub5_out[0][1] [7:0] $end + $var wire 8 x& sub5_out[0][2] [7:0] $end + $var wire 8 y& sub5_out[1][0] [7:0] $end + $var wire 8 z& sub5_out[1][1] [7:0] $end + $var wire 8 {& sub5_out[1][2] [7:0] $end + $scope module i_sub5 $end + $var wire 1 $' clk $end + $var wire 128 ^& in[0][0] [127:0] $end + $var wire 128 b& in[0][1] [127:0] $end + $var wire 128 f& in[0][2] [127:0] $end + $var wire 128 j& in[1][0] [127:0] $end + $var wire 128 n& in[1][1] [127:0] $end + $var wire 128 r& in[1][2] [127:0] $end + $var wire 8 |& out[0][0] [7:0] $end + $var wire 8 }& out[0][1] [7:0] $end + $var wire 8 ~& out[0][2] [7:0] $end + $var wire 8 !' out[1][0] [7:0] $end + $var wire 8 "' out[1][1] [7:0] $end + $var wire 8 #' out[1][2] [7:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 [& i [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 \& j [31:0] $end + $scope module unnamedblk3 $end + $var wire 8 ]& exp [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end + $var wire 1 ?' clk $end + $var wire 128 @' in[0][0] [127:0] $end + $var wire 128 D' in[0][1] [127:0] $end + $var wire 128 H' in[0][2] [127:0] $end + $var wire 128 L' in[1][0] [127:0] $end + $var wire 128 P' in[1][1] [127:0] $end + $var wire 128 T' in[1][2] [127:0] $end + $var wire 8 X' out[0][0] [7:0] $end + $var wire 8 Y' out[0][1] [7:0] $end + $var wire 8 Z' out[0][2] [7:0] $end + $var wire 8 [' out[1][0] [7:0] $end + $var wire 8 \' out[1][1] [7:0] $end + $var wire 8 ]' out[1][2] [7:0] $end + $scope module sub5 $end + $var wire 1 ?' clk $end + $var wire 32 8' count [31:0] $end + $var wire 128 @' in[0][0] [127:0] $end + $var wire 128 D' in[0][1] [127:0] $end + $var wire 128 H' in[0][2] [127:0] $end + $var wire 128 L' in[1][0] [127:0] $end + $var wire 128 P' in[1][1] [127:0] $end + $var wire 128 T' in[1][2] [127:0] $end + $var wire 8 X' out[0][0] [7:0] $end + $var wire 8 Y' out[0][1] [7:0] $end + $var wire 8 Z' out[0][2] [7:0] $end + $var wire 8 [' out[1][0] [7:0] $end + $var wire 8 \' out[1][1] [7:0] $end + $var wire 8 ]' out[1][2] [7:0] $end + $var wire 8 (' val0[0] [7:0] $end + $var wire 8 )' val0[1] [7:0] $end + $var wire 8 *' val1[0] [7:0] $end + $var wire 8 +' val1[1] [7:0] $end + $var wire 8 ,' val2[0] [7:0] $end + $var wire 8 -' val2[1] [7:0] $end + $var wire 8 .' val3[0] [7:0] $end + $var wire 8 /' val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 ^' P0 [31:0] $end + $var wire 32 _' P1 [31:0] $end + $var wire 8 0' out[0] [7:0] $end + $var wire 8 1' out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 ^' P0 [31:0] $end + $var wire 32 _' P1 [31:0] $end + $var wire 8 2' out[0] [7:0] $end + $var wire 8 3' out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 ^' P0 [31:0] $end + $var wire 32 _' P1 [31:0] $end + $var wire 8 4' out[0] [7:0] $end + $var wire 8 5' out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 8 6' out[0] [7:0] $end + $var wire 8 7' out[1] [7:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 9' i [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 :' j [31:0] $end + $scope module unnamedblk3 $end + $var wire 128 ;' exp [127:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end + $var wire 8 a' out[0] [7:0] $end + $var wire 8 b' out[1] [7:0] $end + $scope module sub6_9 $end + $var wire 32 c' P0 [31:0] $end + $var wire 8 a' out[0] [7:0] $end + $var wire 8 b' out[1] [7:0] $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end + $var wire 1 H( clk $end + $var wire 8 I( in [7:0] $end + $var wire 8 J( out [7:0] $end + $scope module sub4_b $end + $var wire 1 H( clk $end + $var wire 32 ~' count [31:0] $end + $var wire 8 e' ff [7:0] $end + $var wire 8 I( in [7:0] $end + $var wire 8 J( out [7:0] $end + $var wire 128 f' sub5_in[0][0] [127:0] $end + $var wire 128 j' sub5_in[0][1] [127:0] $end + $var wire 128 n' sub5_in[0][2] [127:0] $end + $var wire 128 r' sub5_in[1][0] [127:0] $end + $var wire 128 v' sub5_in[1][1] [127:0] $end + $var wire 128 z' sub5_in[1][2] [127:0] $end + $var wire 8 <( sub5_out[0][0] [7:0] $end + $var wire 8 =( sub5_out[0][1] [7:0] $end + $var wire 8 >( sub5_out[0][2] [7:0] $end + $var wire 8 ?( sub5_out[1][0] [7:0] $end + $var wire 8 @( sub5_out[1][1] [7:0] $end + $var wire 8 A( sub5_out[1][2] [7:0] $end + $scope module i_sub5 $end + $var wire 1 H( clk $end + $var wire 128 $( in[0][0] [127:0] $end + $var wire 128 (( in[0][1] [127:0] $end + $var wire 128 ,( in[0][2] [127:0] $end + $var wire 128 0( in[1][0] [127:0] $end + $var wire 128 4( in[1][1] [127:0] $end + $var wire 128 8( in[1][2] [127:0] $end + $var wire 8 B( out[0][0] [7:0] $end + $var wire 8 C( out[0][1] [7:0] $end + $var wire 8 D( out[0][2] [7:0] $end + $var wire 8 E( out[1][0] [7:0] $end + $var wire 8 F( out[1][1] [7:0] $end + $var wire 8 G( out[1][2] [7:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 !( i [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 "( j [31:0] $end + $scope module unnamedblk3 $end + $var wire 8 #( exp [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end + $var wire 1 c( clk $end + $var wire 128 d( in[0][0] [127:0] $end + $var wire 128 h( in[0][1] [127:0] $end + $var wire 128 l( in[0][2] [127:0] $end + $var wire 128 p( in[1][0] [127:0] $end + $var wire 128 t( in[1][1] [127:0] $end + $var wire 128 x( in[1][2] [127:0] $end + $var wire 8 |( out[0][0] [7:0] $end + $var wire 8 }( out[0][1] [7:0] $end + $var wire 8 ~( out[0][2] [7:0] $end + $var wire 8 !) out[1][0] [7:0] $end + $var wire 8 ") out[1][1] [7:0] $end + $var wire 8 #) out[1][2] [7:0] $end + $scope module sub5 $end + $var wire 1 c( clk $end + $var wire 32 \( count [31:0] $end + $var wire 128 d( in[0][0] [127:0] $end + $var wire 128 h( in[0][1] [127:0] $end + $var wire 128 l( in[0][2] [127:0] $end + $var wire 128 p( in[1][0] [127:0] $end + $var wire 128 t( in[1][1] [127:0] $end + $var wire 128 x( in[1][2] [127:0] $end + $var wire 8 |( out[0][0] [7:0] $end + $var wire 8 }( out[0][1] [7:0] $end + $var wire 8 ~( out[0][2] [7:0] $end + $var wire 8 !) out[1][0] [7:0] $end + $var wire 8 ") out[1][1] [7:0] $end + $var wire 8 #) out[1][2] [7:0] $end + $var wire 8 L( val0[0] [7:0] $end + $var wire 8 M( val0[1] [7:0] $end + $var wire 8 N( val1[0] [7:0] $end + $var wire 8 O( val1[1] [7:0] $end + $var wire 8 P( val2[0] [7:0] $end + $var wire 8 Q( val2[1] [7:0] $end + $var wire 8 R( val3[0] [7:0] $end + $var wire 8 S( val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 $) P0 [31:0] $end + $var wire 32 %) P1 [31:0] $end + $var wire 8 T( out[0] [7:0] $end + $var wire 8 U( out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 $) P0 [31:0] $end + $var wire 32 %) P1 [31:0] $end + $var wire 8 V( out[0] [7:0] $end + $var wire 8 W( out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 $) P0 [31:0] $end + $var wire 32 %) P1 [31:0] $end + $var wire 8 X( out[0] [7:0] $end + $var wire 8 Y( out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 8 Z( out[0] [7:0] $end + $var wire 8 [( out[1] [7:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 ]( i [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 ^( j [31:0] $end + $scope module unnamedblk3 $end + $var wire 128 _( exp [127:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end + $var wire 8 ') out[0] [7:0] $end + $var wire 8 () out[1] [7:0] $end + $scope module sub6_9 $end + $var wire 32 )) P0 [31:0] $end + $var wire 8 ') out[0] [7:0] $end + $var wire 8 () out[1] [7:0] $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3_2 $end + $var wire 1 C# clk $end + $var wire 8 D# in [7:0] $end + $var wire 8 E# out [7:0] $end + $scope module sub3_2 $end + $var wire 32 I# UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 J# UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 K# UNUSED [15:0] $end + $var wire 1 C# clk $end + $var wire 8 F# ff [7:0] $end + $var wire 8 D# in [7:0] $end + $var wire 8 E# out [7:0] $end + $var wire 8 G# out4 [7:0] $end + $var wire 8 H# out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 1 C# clk $end + $var wire 8 F# in [7:0] $end + $var wire 8 G# out [7:0] $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 1 C# clk $end + $var wire 8 F# in [7:0] $end + $var wire 8 H# out [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end + $var wire 1 0$ clk $end + $var wire 8 1$ in [7:0] $end + $var wire 8 2$ out [7:0] $end + $scope module sub4_2 $end + $var wire 1 0$ clk $end + $var wire 32 f# count [31:0] $end + $var wire 8 M# ff [7:0] $end + $var wire 8 1$ in [7:0] $end + $var wire 8 2$ out [7:0] $end + $var wire 128 N# sub5_in[0][0] [127:0] $end + $var wire 128 R# sub5_in[0][1] [127:0] $end + $var wire 128 V# sub5_in[0][2] [127:0] $end + $var wire 128 Z# sub5_in[1][0] [127:0] $end + $var wire 128 ^# sub5_in[1][1] [127:0] $end + $var wire 128 b# sub5_in[1][2] [127:0] $end + $var wire 8 $$ sub5_out[0][0] [7:0] $end + $var wire 8 %$ sub5_out[0][1] [7:0] $end + $var wire 8 &$ sub5_out[0][2] [7:0] $end + $var wire 8 '$ sub5_out[1][0] [7:0] $end + $var wire 8 ($ sub5_out[1][1] [7:0] $end + $var wire 8 )$ sub5_out[1][2] [7:0] $end + $scope module i_sub5 $end + $var wire 1 0$ clk $end + $var wire 128 j# in[0][0] [127:0] $end + $var wire 128 n# in[0][1] [127:0] $end + $var wire 128 r# in[0][2] [127:0] $end + $var wire 128 v# in[1][0] [127:0] $end + $var wire 128 z# in[1][1] [127:0] $end + $var wire 128 ~# in[1][2] [127:0] $end + $var wire 8 *$ out[0][0] [7:0] $end + $var wire 8 +$ out[0][1] [7:0] $end + $var wire 8 ,$ out[0][2] [7:0] $end + $var wire 8 -$ out[1][0] [7:0] $end + $var wire 8 .$ out[1][1] [7:0] $end + $var wire 8 /$ out[1][2] [7:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 g# i [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 h# j [31:0] $end + $scope module unnamedblk3 $end + $var wire 8 i# exp [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end + $var wire 1 K$ clk $end + $var wire 128 L$ in[0][0] [127:0] $end + $var wire 128 P$ in[0][1] [127:0] $end + $var wire 128 T$ in[0][2] [127:0] $end + $var wire 128 X$ in[1][0] [127:0] $end + $var wire 128 \$ in[1][1] [127:0] $end + $var wire 128 `$ in[1][2] [127:0] $end + $var wire 8 d$ out[0][0] [7:0] $end + $var wire 8 e$ out[0][1] [7:0] $end + $var wire 8 f$ out[0][2] [7:0] $end + $var wire 8 g$ out[1][0] [7:0] $end + $var wire 8 h$ out[1][1] [7:0] $end + $var wire 8 i$ out[1][2] [7:0] $end + $scope module sub5 $end + $var wire 1 K$ clk $end + $var wire 32 D$ count [31:0] $end + $var wire 128 L$ in[0][0] [127:0] $end + $var wire 128 P$ in[0][1] [127:0] $end + $var wire 128 T$ in[0][2] [127:0] $end + $var wire 128 X$ in[1][0] [127:0] $end + $var wire 128 \$ in[1][1] [127:0] $end + $var wire 128 `$ in[1][2] [127:0] $end + $var wire 8 d$ out[0][0] [7:0] $end + $var wire 8 e$ out[0][1] [7:0] $end + $var wire 8 f$ out[0][2] [7:0] $end + $var wire 8 g$ out[1][0] [7:0] $end + $var wire 8 h$ out[1][1] [7:0] $end + $var wire 8 i$ out[1][2] [7:0] $end + $var wire 8 4$ val0[0] [7:0] $end + $var wire 8 5$ val0[1] [7:0] $end + $var wire 8 6$ val1[0] [7:0] $end + $var wire 8 7$ val1[1] [7:0] $end + $var wire 8 8$ val2[0] [7:0] $end + $var wire 8 9$ val2[1] [7:0] $end + $var wire 8 :$ val3[0] [7:0] $end + $var wire 8 ;$ val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 j$ P0 [31:0] $end + $var wire 32 k$ P1 [31:0] $end + $var wire 8 <$ out[0] [7:0] $end + $var wire 8 =$ out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 j$ P0 [31:0] $end + $var wire 32 k$ P1 [31:0] $end + $var wire 8 >$ out[0] [7:0] $end + $var wire 8 ?$ out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 j$ P0 [31:0] $end + $var wire 32 k$ P1 [31:0] $end + $var wire 8 @$ out[0] [7:0] $end + $var wire 8 A$ out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 8 B$ out[0] [7:0] $end + $var wire 8 C$ out[1] [7:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 E$ i [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 F$ j [31:0] $end + $scope module unnamedblk3 $end + $var wire 128 G$ exp [127:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end + $var wire 8 m$ out[0] [7:0] $end + $var wire 8 n$ out[1] [7:0] $end + $scope module sub6_9 $end + $var wire 32 o$ P0 [31:0] $end + $var wire 8 m$ out[0] [7:0] $end + $var wire 8 n$ out[1] [7:0] $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end + $var wire 1 T% clk $end + $var wire 8 U% in [7:0] $end + $var wire 8 V% out [7:0] $end + $scope module sub4_b $end + $var wire 1 T% clk $end + $var wire 32 ,% count [31:0] $end + $var wire 8 q$ ff [7:0] $end + $var wire 8 U% in [7:0] $end + $var wire 8 V% out [7:0] $end + $var wire 128 r$ sub5_in[0][0] [127:0] $end + $var wire 128 v$ sub5_in[0][1] [127:0] $end + $var wire 128 z$ sub5_in[0][2] [127:0] $end + $var wire 128 ~$ sub5_in[1][0] [127:0] $end + $var wire 128 $% sub5_in[1][1] [127:0] $end + $var wire 128 (% sub5_in[1][2] [127:0] $end + $var wire 8 H% sub5_out[0][0] [7:0] $end + $var wire 8 I% sub5_out[0][1] [7:0] $end + $var wire 8 J% sub5_out[0][2] [7:0] $end + $var wire 8 K% sub5_out[1][0] [7:0] $end + $var wire 8 L% sub5_out[1][1] [7:0] $end + $var wire 8 M% sub5_out[1][2] [7:0] $end + $scope module i_sub5 $end + $var wire 1 T% clk $end + $var wire 128 0% in[0][0] [127:0] $end + $var wire 128 4% in[0][1] [127:0] $end + $var wire 128 8% in[0][2] [127:0] $end + $var wire 128 <% in[1][0] [127:0] $end + $var wire 128 @% in[1][1] [127:0] $end + $var wire 128 D% in[1][2] [127:0] $end + $var wire 8 N% out[0][0] [7:0] $end + $var wire 8 O% out[0][1] [7:0] $end + $var wire 8 P% out[0][2] [7:0] $end + $var wire 8 Q% out[1][0] [7:0] $end + $var wire 8 R% out[1][1] [7:0] $end + $var wire 8 S% out[1][2] [7:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 -% i [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 .% j [31:0] $end + $scope module unnamedblk3 $end + $var wire 8 /% exp [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end + $var wire 1 o% clk $end + $var wire 128 p% in[0][0] [127:0] $end + $var wire 128 t% in[0][1] [127:0] $end + $var wire 128 x% in[0][2] [127:0] $end + $var wire 128 |% in[1][0] [127:0] $end + $var wire 128 "& in[1][1] [127:0] $end + $var wire 128 && in[1][2] [127:0] $end + $var wire 8 *& out[0][0] [7:0] $end + $var wire 8 +& out[0][1] [7:0] $end + $var wire 8 ,& out[0][2] [7:0] $end + $var wire 8 -& out[1][0] [7:0] $end + $var wire 8 .& out[1][1] [7:0] $end + $var wire 8 /& out[1][2] [7:0] $end + $scope module sub5 $end + $var wire 1 o% clk $end + $var wire 32 h% count [31:0] $end + $var wire 128 p% in[0][0] [127:0] $end + $var wire 128 t% in[0][1] [127:0] $end + $var wire 128 x% in[0][2] [127:0] $end + $var wire 128 |% in[1][0] [127:0] $end + $var wire 128 "& in[1][1] [127:0] $end + $var wire 128 && in[1][2] [127:0] $end + $var wire 8 *& out[0][0] [7:0] $end + $var wire 8 +& out[0][1] [7:0] $end + $var wire 8 ,& out[0][2] [7:0] $end + $var wire 8 -& out[1][0] [7:0] $end + $var wire 8 .& out[1][1] [7:0] $end + $var wire 8 /& out[1][2] [7:0] $end + $var wire 8 X% val0[0] [7:0] $end + $var wire 8 Y% val0[1] [7:0] $end + $var wire 8 Z% val1[0] [7:0] $end + $var wire 8 [% val1[1] [7:0] $end + $var wire 8 \% val2[0] [7:0] $end + $var wire 8 ]% val2[1] [7:0] $end + $var wire 8 ^% val3[0] [7:0] $end + $var wire 8 _% val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 0& P0 [31:0] $end + $var wire 32 1& P1 [31:0] $end + $var wire 8 `% out[0] [7:0] $end + $var wire 8 a% out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 0& P0 [31:0] $end + $var wire 32 1& P1 [31:0] $end + $var wire 8 b% out[0] [7:0] $end + $var wire 8 c% out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 0& P0 [31:0] $end + $var wire 32 1& P1 [31:0] $end + $var wire 8 d% out[0] [7:0] $end + $var wire 8 e% out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 8 f% out[0] [7:0] $end + $var wire 8 g% out[1] [7:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 i% i [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 j% j [31:0] $end + $scope module unnamedblk3 $end + $var wire 128 k% exp [127:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end + $var wire 8 3& out[0] [7:0] $end + $var wire 8 4& out[1] [7:0] $end + $scope module sub6_9 $end + $var wire 32 5& P0 [31:0] $end + $var wire 8 3& out[0] [7:0] $end + $var wire 8 4& out[1] [7:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0# +b00000000 $ +b00000000 % +b00000000 & +b00000000 ' +b00000000 ( +b00000000 ) +b00000000 * +b00000000000000000000000000000000 + +0- +b00000000 . +b00000000 / +b00000000 0 +b00000000 1 +b00000000000000000000000000001000 2 +b00000000000000000000000000000001 3 +b00000000 5 +b00000000 6 +b00000000 7 +08 +b00000000 9 +b00000000 : +b00000000000000000000000000001000 ; +b00000000000000000000000000000010 < +b00000000000000000000000000000001 = +0? +b00000000 @ +b00000000 A +b00000000 B +0D +b00000000 E +b00000000 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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p( +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t( +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x( +b00000000 |( +b00000000 }( +b00000000 ~( +b00000000 !) +b00000000 ") +b00000000 #) +#171 +#172 +#173 +#174 diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.pl b/test_regress/t/t_hier_block_sc_trace_vcd.pl new file mode 100755 index 000000000..3ce4b1da3 --- /dev/null +++ b/test_regress/t/t_hier_block_sc_trace_vcd.pl @@ -0,0 +1,44 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +clean_objs(); + +top_filename("t/t_hier_block.v"); + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performace wise, but ok. +scenarios(vlt_all => 1); + +compile( + v_flags2 => ['t/t_hier_block.cpp'], + verilator_flags2 => ['--sc', + '--stats', + '--hierarchical', + ($Self->{vltmt} ? ' --threads 6' : ''), + '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + "--CFLAGS", '"-O0 -ggdb"', + "--trace" + ], + ); + +execute( + check_finished => 1, + ); + +file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); +file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); +file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); +file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 13); +file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); + +vcd_identical($Self->trace_filename, $Self->{golden_filename}); +ok(1); +1; diff --git a/test_regress/t/t_hier_block_trace_fst.out b/test_regress/t/t_hier_block_trace_fst.out new file mode 100644 index 000000000..366eef0b4 --- /dev/null +++ b/test_regress/t/t_hier_block_trace_fst.out @@ -0,0 +1,6788 @@ +$date + Tue Feb 22 23:53:34 2022 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$var wire 8 " out0 [7:0] $end +$var wire 8 # out1 [7:0] $end +$var wire 8 $ out2 [7:0] $end +$var wire 8 % out3 [7:0] $end +$var wire 8 & out3_2 [7:0] $end +$var wire 8 ' out5 [7:0] $end +$var wire 8 ( out6 [7:0] $end +$var int 32 ) count [31:0] $end +$scope module i_delay0 $end +$var wire 1 ! clk $end +$var wire 8 % in [7:0] $end +$var wire 8 ' out [7:0] $end +$upscope $end +$scope module i_delay1 $end +$var wire 1 ! clk $end +$var wire 8 ' in [7:0] $end +$var wire 8 ( out [7:0] $end +$upscope $end +$scope module i_sub0 $end +$var wire 1 ! clk $end +$var wire 8 % in [7:0] $end +$var wire 8 " out [7:0] $end +$scope module i_sub0 $end +$var wire 1 ! clk $end +$var wire 8 % in [7:0] $end +$var wire 8 " out [7:0] $end +$upscope $end +$upscope $end +$scope module i_sub1 $end +$var wire 1 ! clk $end +$var wire 8 " in [7:0] $end +$var wire 8 # out [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var wire 1 ! clk $end +$var wire 8 # in [7:0] $end +$var wire 8 $ out [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 1 ! clk $end +$var wire 8 $ in [7:0] $end +$var wire 8 % out [7:0] $end +$upscope $end +$scope module i_sub3_2 $end +$var wire 1 ! clk $end +$var wire 8 $ in [7:0] $end +$var wire 8 & out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_delay0 $end +$var wire 1 * clk $end +$var wire 8 + in [7:0] $end +$var wire 8 , out [7:0] $end +$scope module delay_2 $end +$var parameter 32 - WIDTH [31:0] $end +$var wire 1 * clk $end +$var wire 8 + in [7:0] $end +$var wire 8 , out [7:0] $end +$var logic 8 . tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 / N [31:0] $end +$var parameter 32 - WIDTH [31:0] $end +$var wire 1 * clk $end +$var wire 8 . in [7:0] $end +$var wire 8 , out [7:0] $end +$var logic 8 0 tmp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_delay1 $end +$var wire 1 1 clk $end +$var wire 8 2 in [7:0] $end +$var wire 8 3 out [7:0] $end +$scope module delay_9 $end +$var parameter 32 4 WIDTH [31:0] $end +$var wire 1 1 clk $end +$var wire 8 2 in [7:0] $end +$var wire 8 3 out [7:0] $end +$var logic 8 5 tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 6 N [31:0] $end +$var parameter 32 4 WIDTH [31:0] $end +$var wire 1 1 clk $end +$var wire 8 5 in [7:0] $end +$var wire 8 3 out [7:0] $end +$var logic 8 7 tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 8 N [31:0] $end +$var parameter 32 4 WIDTH [31:0] $end +$var wire 1 1 clk $end +$var wire 8 7 in [7:0] $end +$var wire 8 3 out [7:0] $end +$var logic 8 9 tmp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub0.i_sub0 $end +$var wire 1 : clk $end +$var wire 8 ; in [7:0] $end +$var wire 8 < out [7:0] $end +$scope module sub0 $end +$var wire 1 : clk $end +$var wire 8 ; in [7:0] $end +$var wire 8 < out [7:0] $end +$var logic 8 = ff [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub1 $end +$var wire 1 > clk $end +$var wire 8 ? in [7:0] $end +$var wire 8 @ out [7:0] $end +$scope module sub1 $end +$var wire 1 > clk $end +$var wire 8 ? in [7:0] $end +$var wire 8 @ out [7:0] $end +$var logic 8 A ff [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2 $end +$var wire 1 B clk $end +$var wire 8 C in [7:0] $end +$var wire 8 D out [7:0] $end +$scope module sub2 $end +$var wire 1 B clk $end +$var wire 8 C in [7:0] $end +$var wire 8 D out [7:0] $end +$var logic 8 E ff [7:0] $end +$scope module i_sub3 $end +$var wire 8 E in_wire [7:0] $end +$var wire 8 F out_1 [7:0] $end +$var wire 8 G out_2 [7:0] $end +$scope module i_sub3 $end +$var wire 1 B clk $end +$var wire 8 E in [7:0] $end +$var wire 8 F out [7:0] $end +$upscope $end +$scope module i_sub3_2 $end +$var wire 1 B clk $end +$var wire 8 E in [7:0] $end +$var wire 8 G out [7:0] $end +$upscope $end +$scope interface in $end +$var wire 1 B clk $end +$var logic 8 E data [7:0] $end +$upscope $end +$scope interface out $end +$var wire 1 B clk $end +$var logic 8 F data [7:0] $end +$upscope $end +$upscope $end +$scope interface in_ifs $end +$var wire 1 B clk $end +$var logic 8 E data [7:0] $end +$upscope $end +$scope interface out_ifs $end +$var wire 1 B clk $end +$var logic 8 F data [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end +$var wire 1 H clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end +$scope module sub3_c $end +$var parameter 32 K UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 L UNPACKED_ARRAY[1] [31:0] $end +$var wire 1 H clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end +$var logic 8 M ff [7:0] $end +$var wire 8 N out4 [7:0] $end +$var wire 8 O out4_2 [7:0] $end +$scope module i_sub4_0 $end +$var wire 1 H clk $end +$var wire 8 M in [7:0] $end +$var wire 8 N out [7:0] $end +$upscope $end +$scope module i_sub4_1 $end +$var wire 1 H clk $end +$var wire 8 M in [7:0] $end +$var wire 8 O out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end +$var wire 1 P clk $end +$var wire 8 Q in [7:0] $end +$var wire 8 R out [7:0] $end +$scope module sub4_2 $end +$var wire 1 P clk $end +$var wire 8 Q in [7:0] $end +$var wire 8 R out [7:0] $end +$var logic 8 S ff [7:0] $end +$var logic 128 T sub5_in[0][0] [127:0] $end +$var logic 128 U sub5_in[0][1] [127:0] $end +$var logic 128 V sub5_in[0][2] [127:0] $end +$var logic 128 W sub5_in[1][0] [127:0] $end +$var logic 128 X sub5_in[1][1] [127:0] $end +$var logic 128 Y sub5_in[1][2] [127:0] $end +$var wire 8 Z sub5_out[0][0] [7:0] $end +$var wire 8 [ sub5_out[0][1] [7:0] $end +$var wire 8 \ sub5_out[0][2] [7:0] $end +$var wire 8 ] sub5_out[1][0] [7:0] $end +$var wire 8 ^ sub5_out[1][1] [7:0] $end +$var wire 8 _ sub5_out[1][2] [7:0] $end +$var int 32 ` count [31:0] $end +$scope module i_sub5 $end +$var wire 1 P clk $end +$var wire 128 a in[0][0] [127:0] $end +$var wire 128 b in[0][1] [127:0] $end +$var wire 128 c in[0][2] [127:0] $end +$var wire 128 d in[1][0] [127:0] $end +$var wire 128 e in[1][1] [127:0] $end +$var wire 128 f in[1][2] [127:0] $end +$var wire 8 g out[0][0] [7:0] $end +$var wire 8 h out[0][1] [7:0] $end +$var wire 8 i out[0][2] [7:0] $end +$var wire 8 j out[1][0] [7:0] $end +$var wire 8 k out[1][1] [7:0] $end +$var wire 8 l out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 m i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 n j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 o exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end +$var wire 1 p clk $end +$var wire 128 q in[0][0] [127:0] $end +$var wire 128 r in[0][1] [127:0] $end +$var wire 128 s in[0][2] [127:0] $end +$var wire 128 t in[1][0] [127:0] $end +$var wire 128 u in[1][1] [127:0] $end +$var wire 128 v in[1][2] [127:0] $end +$var wire 8 w out[0][0] [7:0] $end +$var wire 8 x out[0][1] [7:0] $end +$var wire 8 y out[0][2] [7:0] $end +$var wire 8 z out[1][0] [7:0] $end +$var wire 8 { out[1][1] [7:0] $end +$var wire 8 | out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 p clk $end +$var wire 128 q in[0][0] [127:0] $end +$var wire 128 r in[0][1] [127:0] $end +$var wire 128 s in[0][2] [127:0] $end +$var wire 128 t in[1][0] [127:0] $end +$var wire 128 u in[1][1] [127:0] $end +$var wire 128 v in[1][2] [127:0] $end +$var wire 8 w out[0][0] [7:0] $end +$var wire 8 x out[0][1] [7:0] $end +$var wire 8 y out[0][2] [7:0] $end +$var wire 8 z out[1][0] [7:0] $end +$var wire 8 { out[1][1] [7:0] $end +$var wire 8 | out[1][2] [7:0] $end +$var int 32 } count [31:0] $end +$var wire 8 ~ val0[0] [7:0] $end +$var wire 8 !! val0[1] [7:0] $end +$var wire 8 "! val1[0] [7:0] $end +$var wire 8 #! val1[1] [7:0] $end +$var wire 8 $! val2[0] [7:0] $end +$var wire 8 %! val2[1] [7:0] $end +$var wire 8 &! val3[0] [7:0] $end +$var wire 8 '! val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 (! P0 [31:0] $end +$var parameter 32 )! P1 [31:0] $end +$var wire 8 *! out[0] [7:0] $end +$var wire 8 +! out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 (! P0 [31:0] $end +$var parameter 32 )! P1 [31:0] $end +$var wire 8 ,! out[0] [7:0] $end +$var wire 8 -! out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 (! P0 [31:0] $end +$var parameter 32 )! P1 [31:0] $end +$var wire 8 .! out[0] [7:0] $end +$var wire 8 /! out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 0! out[0] [7:0] $end +$var wire 8 1! out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 2! i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 3! j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 4! exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end +$var wire 8 5! out[0] [7:0] $end +$var wire 8 6! out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 7! P0 [31:0] $end +$var wire 8 5! out[0] [7:0] $end +$var wire 8 6! out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end +$var wire 1 8! clk $end +$var wire 8 9! in [7:0] $end +$var wire 8 :! out [7:0] $end +$scope module sub4_b $end +$var wire 1 8! clk $end +$var wire 8 9! in [7:0] $end +$var wire 8 :! out [7:0] $end +$var logic 8 ;! ff [7:0] $end +$var logic 128 ! sub5_in[0][2] [127:0] $end +$var logic 128 ?! sub5_in[1][0] [127:0] $end +$var logic 128 @! sub5_in[1][1] [127:0] $end +$var logic 128 A! sub5_in[1][2] [127:0] $end +$var wire 8 B! sub5_out[0][0] [7:0] $end +$var wire 8 C! sub5_out[0][1] [7:0] $end +$var wire 8 D! sub5_out[0][2] [7:0] $end +$var wire 8 E! sub5_out[1][0] [7:0] $end +$var wire 8 F! sub5_out[1][1] [7:0] $end +$var wire 8 G! sub5_out[1][2] [7:0] $end +$var int 32 H! count [31:0] $end +$scope module i_sub5 $end +$var wire 1 8! clk $end +$var wire 128 I! in[0][0] [127:0] $end +$var wire 128 J! in[0][1] [127:0] $end +$var wire 128 K! in[0][2] [127:0] $end +$var wire 128 L! in[1][0] [127:0] $end +$var wire 128 M! in[1][1] [127:0] $end +$var wire 128 N! in[1][2] [127:0] $end +$var wire 8 O! out[0][0] [7:0] $end +$var wire 8 P! out[0][1] [7:0] $end +$var wire 8 Q! out[0][2] [7:0] $end +$var wire 8 R! out[1][0] [7:0] $end +$var wire 8 S! out[1][1] [7:0] $end +$var wire 8 T! out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 U! i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 V! j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 W! exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end +$var wire 1 X! clk $end +$var wire 128 Y! in[0][0] [127:0] $end +$var wire 128 Z! in[0][1] [127:0] $end +$var wire 128 [! in[0][2] [127:0] $end +$var wire 128 \! in[1][0] [127:0] $end +$var wire 128 ]! in[1][1] [127:0] $end +$var wire 128 ^! in[1][2] [127:0] $end +$var wire 8 _! out[0][0] [7:0] $end +$var wire 8 `! out[0][1] [7:0] $end +$var wire 8 a! out[0][2] [7:0] $end +$var wire 8 b! out[1][0] [7:0] $end +$var wire 8 c! out[1][1] [7:0] $end +$var wire 8 d! out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 X! clk $end +$var wire 128 Y! in[0][0] [127:0] $end +$var wire 128 Z! in[0][1] [127:0] $end +$var wire 128 [! in[0][2] [127:0] $end +$var wire 128 \! in[1][0] [127:0] $end +$var wire 128 ]! in[1][1] [127:0] $end +$var wire 128 ^! in[1][2] [127:0] $end +$var wire 8 _! out[0][0] [7:0] $end +$var wire 8 `! out[0][1] [7:0] $end +$var wire 8 a! out[0][2] [7:0] $end +$var wire 8 b! out[1][0] [7:0] $end +$var wire 8 c! out[1][1] [7:0] $end +$var wire 8 d! out[1][2] [7:0] $end +$var int 32 e! count [31:0] $end +$var wire 8 f! val0[0] [7:0] $end +$var wire 8 g! val0[1] [7:0] $end +$var wire 8 h! val1[0] [7:0] $end +$var wire 8 i! val1[1] [7:0] $end +$var wire 8 j! val2[0] [7:0] $end +$var wire 8 k! val2[1] [7:0] $end +$var wire 8 l! val3[0] [7:0] $end +$var wire 8 m! val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 n! P0 [31:0] $end +$var parameter 32 o! P1 [31:0] $end +$var wire 8 p! out[0] [7:0] $end +$var wire 8 q! out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 n! P0 [31:0] $end +$var parameter 32 o! P1 [31:0] $end +$var wire 8 r! out[0] [7:0] $end +$var wire 8 s! out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 n! P0 [31:0] $end +$var parameter 32 o! P1 [31:0] $end +$var wire 8 t! out[0] [7:0] $end +$var wire 8 u! out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 v! out[0] [7:0] $end +$var wire 8 w! out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 x! i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 y! j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 z! exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end +$var wire 8 {! out[0] [7:0] $end +$var wire 8 |! out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 }! P0 [31:0] $end +$var wire 8 {! out[0] [7:0] $end +$var wire 8 |! out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2 $end +$var wire 1 ~! clk $end +$var wire 8 !" in [7:0] $end +$var wire 8 "" out [7:0] $end +$scope module sub3_2 $end +$var parameter 32 #" UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 $" UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 %" UNUSED [15:0] $end +$var wire 1 ~! clk $end +$var wire 8 !" in [7:0] $end +$var wire 8 "" out [7:0] $end +$var logic 8 &" ff [7:0] $end +$var wire 8 '" out4 [7:0] $end +$var wire 8 (" out4_2 [7:0] $end +$scope module i_sub4_0 $end +$var wire 1 ~! clk $end +$var wire 8 &" in [7:0] $end +$var wire 8 '" out [7:0] $end +$upscope $end +$scope module i_sub4_1 $end +$var wire 1 ~! clk $end +$var wire 8 &" in [7:0] $end +$var wire 8 (" out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end +$var wire 1 )" clk $end +$var wire 8 *" in [7:0] $end +$var wire 8 +" out [7:0] $end +$scope module sub4_2 $end +$var wire 1 )" clk $end +$var wire 8 *" in [7:0] $end +$var wire 8 +" out [7:0] $end +$var logic 8 ," ff [7:0] $end +$var logic 128 -" sub5_in[0][0] [127:0] $end +$var logic 128 ." sub5_in[0][1] [127:0] $end +$var logic 128 /" sub5_in[0][2] [127:0] $end +$var logic 128 0" sub5_in[1][0] [127:0] $end +$var logic 128 1" sub5_in[1][1] [127:0] $end +$var logic 128 2" sub5_in[1][2] [127:0] $end +$var wire 8 3" sub5_out[0][0] [7:0] $end +$var wire 8 4" sub5_out[0][1] [7:0] $end +$var wire 8 5" sub5_out[0][2] [7:0] $end +$var wire 8 6" sub5_out[1][0] [7:0] $end +$var wire 8 7" sub5_out[1][1] [7:0] $end +$var wire 8 8" sub5_out[1][2] [7:0] $end +$var int 32 9" count [31:0] $end +$scope module i_sub5 $end +$var wire 1 )" clk $end +$var wire 128 :" in[0][0] [127:0] $end +$var wire 128 ;" in[0][1] [127:0] $end +$var wire 128 <" in[0][2] [127:0] $end +$var wire 128 =" in[1][0] [127:0] $end +$var wire 128 >" in[1][1] [127:0] $end +$var wire 128 ?" in[1][2] [127:0] $end +$var wire 8 @" out[0][0] [7:0] $end +$var wire 8 A" out[0][1] [7:0] $end +$var wire 8 B" out[0][2] [7:0] $end +$var wire 8 C" out[1][0] [7:0] $end +$var wire 8 D" out[1][1] [7:0] $end +$var wire 8 E" out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 F" i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 G" j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 H" exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end +$var wire 1 I" clk $end +$var wire 128 J" in[0][0] [127:0] $end +$var wire 128 K" in[0][1] [127:0] $end +$var wire 128 L" in[0][2] [127:0] $end +$var wire 128 M" in[1][0] [127:0] $end +$var wire 128 N" in[1][1] [127:0] $end +$var wire 128 O" in[1][2] [127:0] $end +$var wire 8 P" out[0][0] [7:0] $end +$var wire 8 Q" out[0][1] [7:0] $end +$var wire 8 R" out[0][2] [7:0] $end +$var wire 8 S" out[1][0] [7:0] $end +$var wire 8 T" out[1][1] [7:0] $end +$var wire 8 U" out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 I" clk $end +$var wire 128 J" in[0][0] [127:0] $end +$var wire 128 K" in[0][1] [127:0] $end +$var wire 128 L" in[0][2] [127:0] $end +$var wire 128 M" in[1][0] [127:0] $end +$var wire 128 N" in[1][1] [127:0] $end +$var wire 128 O" in[1][2] [127:0] $end +$var wire 8 P" out[0][0] [7:0] $end +$var wire 8 Q" out[0][1] [7:0] $end +$var wire 8 R" out[0][2] [7:0] $end +$var wire 8 S" out[1][0] [7:0] $end +$var wire 8 T" out[1][1] [7:0] $end +$var wire 8 U" out[1][2] [7:0] $end +$var int 32 V" count [31:0] $end +$var wire 8 W" val0[0] [7:0] $end +$var wire 8 X" val0[1] [7:0] $end +$var wire 8 Y" val1[0] [7:0] $end +$var wire 8 Z" val1[1] [7:0] $end +$var wire 8 [" val2[0] [7:0] $end +$var wire 8 \" val2[1] [7:0] $end +$var wire 8 ]" val3[0] [7:0] $end +$var wire 8 ^" val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 _" P0 [31:0] $end +$var parameter 32 `" P1 [31:0] $end +$var wire 8 a" out[0] [7:0] $end +$var wire 8 b" out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 _" P0 [31:0] $end +$var parameter 32 `" P1 [31:0] $end +$var wire 8 c" out[0] [7:0] $end +$var wire 8 d" out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 _" P0 [31:0] $end +$var parameter 32 `" P1 [31:0] $end +$var wire 8 e" out[0] [7:0] $end +$var wire 8 f" out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 g" out[0] [7:0] $end +$var wire 8 h" out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 i" i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 j" j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 k" exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end +$var wire 8 l" out[0] [7:0] $end +$var wire 8 m" out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 n" P0 [31:0] $end +$var wire 8 l" out[0] [7:0] $end +$var wire 8 m" out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end +$var wire 1 o" clk $end +$var wire 8 p" in [7:0] $end +$var wire 8 q" out [7:0] $end +$scope module sub4_b $end +$var wire 1 o" clk $end +$var wire 8 p" in [7:0] $end +$var wire 8 q" out [7:0] $end +$var logic 8 r" ff [7:0] $end +$var logic 128 s" sub5_in[0][0] [127:0] $end +$var logic 128 t" sub5_in[0][1] [127:0] $end +$var logic 128 u" sub5_in[0][2] [127:0] $end +$var logic 128 v" sub5_in[1][0] [127:0] $end +$var logic 128 w" sub5_in[1][1] [127:0] $end +$var logic 128 x" sub5_in[1][2] [127:0] $end +$var wire 8 y" sub5_out[0][0] [7:0] $end +$var wire 8 z" sub5_out[0][1] [7:0] $end +$var wire 8 {" sub5_out[0][2] [7:0] $end +$var wire 8 |" sub5_out[1][0] [7:0] $end +$var wire 8 }" sub5_out[1][1] [7:0] $end +$var wire 8 ~" sub5_out[1][2] [7:0] $end +$var int 32 !# count [31:0] $end +$scope module i_sub5 $end +$var wire 1 o" clk $end +$var wire 128 "# in[0][0] [127:0] $end +$var wire 128 ## in[0][1] [127:0] $end +$var wire 128 $# in[0][2] [127:0] $end +$var wire 128 %# in[1][0] [127:0] $end +$var wire 128 &# in[1][1] [127:0] $end +$var wire 128 '# in[1][2] [127:0] $end +$var wire 8 (# out[0][0] [7:0] $end +$var wire 8 )# out[0][1] [7:0] $end +$var wire 8 *# out[0][2] [7:0] $end +$var wire 8 +# out[1][0] [7:0] $end +$var wire 8 ,# out[1][1] [7:0] $end +$var wire 8 -# out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 .# i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 /# j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 0# exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end +$var wire 1 1# clk $end +$var wire 128 2# in[0][0] [127:0] $end +$var wire 128 3# in[0][1] [127:0] $end +$var wire 128 4# in[0][2] [127:0] $end +$var wire 128 5# in[1][0] [127:0] $end +$var wire 128 6# in[1][1] [127:0] $end +$var wire 128 7# in[1][2] [127:0] $end +$var wire 8 8# out[0][0] [7:0] $end +$var wire 8 9# out[0][1] [7:0] $end +$var wire 8 :# out[0][2] [7:0] $end +$var wire 8 ;# out[1][0] [7:0] $end +$var wire 8 <# out[1][1] [7:0] $end +$var wire 8 =# out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 1# clk $end +$var wire 128 2# in[0][0] [127:0] $end +$var wire 128 3# in[0][1] [127:0] $end +$var wire 128 4# in[0][2] [127:0] $end +$var wire 128 5# in[1][0] [127:0] $end +$var wire 128 6# in[1][1] [127:0] $end +$var wire 128 7# in[1][2] [127:0] $end +$var wire 8 8# out[0][0] [7:0] $end +$var wire 8 9# out[0][1] [7:0] $end +$var wire 8 :# out[0][2] [7:0] $end +$var wire 8 ;# out[1][0] [7:0] $end +$var wire 8 <# out[1][1] [7:0] $end +$var wire 8 =# out[1][2] [7:0] $end +$var int 32 ># count [31:0] $end +$var wire 8 ?# val0[0] [7:0] $end +$var wire 8 @# val0[1] [7:0] $end +$var wire 8 A# val1[0] [7:0] $end +$var wire 8 B# val1[1] [7:0] $end +$var wire 8 C# val2[0] [7:0] $end +$var wire 8 D# val2[1] [7:0] $end +$var wire 8 E# val3[0] [7:0] $end +$var wire 8 F# val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 G# P0 [31:0] $end +$var parameter 32 H# P1 [31:0] $end +$var wire 8 I# out[0] [7:0] $end +$var wire 8 J# out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 G# P0 [31:0] $end +$var parameter 32 H# P1 [31:0] $end +$var wire 8 K# out[0] [7:0] $end +$var wire 8 L# out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 G# P0 [31:0] $end +$var parameter 32 H# P1 [31:0] $end +$var wire 8 M# out[0] [7:0] $end +$var wire 8 N# out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 O# out[0] [7:0] $end +$var wire 8 P# out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 Q# i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 R# j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 S# exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end +$var wire 8 T# out[0] [7:0] $end +$var wire 8 U# out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 V# P0 [31:0] $end +$var wire 8 T# out[0] [7:0] $end +$var wire 8 U# out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3 $end +$var wire 1 W# clk $end +$var wire 8 X# in [7:0] $end +$var wire 8 Y# out [7:0] $end +$scope module sub3_d $end +$var parameter 32 Z# UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 [# UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 \# UNUSED [15:0] $end +$var wire 1 W# clk $end +$var wire 8 X# in [7:0] $end +$var wire 8 Y# out [7:0] $end +$var logic 8 ]# ff [7:0] $end +$var wire 8 ^# out4 [7:0] $end +$var wire 8 _# out4_2 [7:0] $end +$scope module i_sub4_0 $end +$var wire 1 W# clk $end +$var wire 8 ]# in [7:0] $end +$var wire 8 ^# out [7:0] $end +$upscope $end +$scope module i_sub4_1 $end +$var wire 1 W# clk $end +$var wire 8 ]# in [7:0] $end +$var wire 8 _# out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_0 $end +$var wire 1 `# clk $end +$var wire 8 a# in [7:0] $end +$var wire 8 b# out [7:0] $end +$scope module sub4_2 $end +$var wire 1 `# clk $end +$var wire 8 a# in [7:0] $end +$var wire 8 b# out [7:0] $end +$var logic 8 c# ff [7:0] $end +$var logic 128 d# sub5_in[0][0] [127:0] $end +$var logic 128 e# sub5_in[0][1] [127:0] $end +$var logic 128 f# sub5_in[0][2] [127:0] $end +$var logic 128 g# sub5_in[1][0] [127:0] $end +$var logic 128 h# sub5_in[1][1] [127:0] $end +$var logic 128 i# sub5_in[1][2] [127:0] $end +$var wire 8 j# sub5_out[0][0] [7:0] $end +$var wire 8 k# sub5_out[0][1] [7:0] $end +$var wire 8 l# sub5_out[0][2] [7:0] $end +$var wire 8 m# sub5_out[1][0] [7:0] $end +$var wire 8 n# sub5_out[1][1] [7:0] $end +$var wire 8 o# sub5_out[1][2] [7:0] $end +$var int 32 p# count [31:0] $end +$scope module i_sub5 $end +$var wire 1 `# clk $end +$var wire 128 q# in[0][0] [127:0] $end +$var wire 128 r# in[0][1] [127:0] $end +$var wire 128 s# in[0][2] [127:0] $end +$var wire 128 t# in[1][0] [127:0] $end +$var wire 128 u# in[1][1] [127:0] $end +$var wire 128 v# in[1][2] [127:0] $end +$var wire 8 w# out[0][0] [7:0] $end +$var wire 8 x# out[0][1] [7:0] $end +$var wire 8 y# out[0][2] [7:0] $end +$var wire 8 z# out[1][0] [7:0] $end +$var wire 8 {# out[1][1] [7:0] $end +$var wire 8 |# out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 }# i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 ~# j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 !$ exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end +$var wire 1 "$ clk $end +$var wire 128 #$ in[0][0] [127:0] $end +$var wire 128 $$ in[0][1] [127:0] $end +$var wire 128 %$ in[0][2] [127:0] $end +$var wire 128 &$ in[1][0] [127:0] $end +$var wire 128 '$ in[1][1] [127:0] $end +$var wire 128 ($ in[1][2] [127:0] $end +$var wire 8 )$ out[0][0] [7:0] $end +$var wire 8 *$ out[0][1] [7:0] $end +$var wire 8 +$ out[0][2] [7:0] $end +$var wire 8 ,$ out[1][0] [7:0] $end +$var wire 8 -$ out[1][1] [7:0] $end +$var wire 8 .$ out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 "$ clk $end +$var wire 128 #$ in[0][0] [127:0] $end +$var wire 128 $$ in[0][1] [127:0] $end +$var wire 128 %$ in[0][2] [127:0] $end +$var wire 128 &$ in[1][0] [127:0] $end +$var wire 128 '$ in[1][1] [127:0] $end +$var wire 128 ($ in[1][2] [127:0] $end +$var wire 8 )$ out[0][0] [7:0] $end +$var wire 8 *$ out[0][1] [7:0] $end +$var wire 8 +$ out[0][2] [7:0] $end +$var wire 8 ,$ out[1][0] [7:0] $end +$var wire 8 -$ out[1][1] [7:0] $end +$var wire 8 .$ out[1][2] [7:0] $end +$var int 32 /$ count [31:0] $end +$var wire 8 0$ val0[0] [7:0] $end +$var wire 8 1$ val0[1] [7:0] $end +$var wire 8 2$ val1[0] [7:0] $end +$var wire 8 3$ val1[1] [7:0] $end +$var wire 8 4$ val2[0] [7:0] $end +$var wire 8 5$ val2[1] [7:0] $end +$var wire 8 6$ val3[0] [7:0] $end +$var wire 8 7$ val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 8$ P0 [31:0] $end +$var parameter 32 9$ P1 [31:0] $end +$var wire 8 :$ out[0] [7:0] $end +$var wire 8 ;$ out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 8$ P0 [31:0] $end +$var parameter 32 9$ P1 [31:0] $end +$var wire 8 <$ out[0] [7:0] $end +$var wire 8 =$ out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 8$ P0 [31:0] $end +$var parameter 32 9$ P1 [31:0] $end +$var wire 8 >$ out[0] [7:0] $end +$var wire 8 ?$ out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var wire 8 @$ out[0] [7:0] $end +$var wire 8 A$ out[1] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 B$ i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 C$ j [31:0] $end +$scope module unnamedblk3 $end +$var bit 128 D$ exp [127:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end +$var wire 8 E$ out[0] [7:0] $end +$var wire 8 F$ out[1] [7:0] $end +$scope module sub6_9 $end +$var parameter 32 G$ P0 [31:0] $end +$var wire 8 E$ out[0] [7:0] $end +$var wire 8 F$ out[1] [7:0] $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_1 $end +$var wire 1 H$ clk $end +$var wire 8 I$ in [7:0] $end +$var wire 8 J$ out [7:0] $end +$scope module sub4_b $end +$var wire 1 H$ clk $end +$var wire 8 I$ in [7:0] $end +$var wire 8 J$ out [7:0] $end +$var logic 8 K$ ff [7:0] $end +$var logic 128 L$ sub5_in[0][0] [127:0] $end +$var logic 128 M$ sub5_in[0][1] [127:0] $end +$var logic 128 N$ sub5_in[0][2] [127:0] $end +$var logic 128 O$ sub5_in[1][0] [127:0] $end +$var logic 128 P$ sub5_in[1][1] [127:0] $end +$var logic 128 Q$ sub5_in[1][2] [127:0] $end +$var wire 8 R$ sub5_out[0][0] [7:0] $end +$var wire 8 S$ sub5_out[0][1] [7:0] $end +$var wire 8 T$ sub5_out[0][2] [7:0] $end +$var wire 8 U$ sub5_out[1][0] [7:0] $end +$var wire 8 V$ sub5_out[1][1] [7:0] $end +$var wire 8 W$ sub5_out[1][2] [7:0] $end +$var int 32 X$ count [31:0] $end +$scope module i_sub5 $end +$var wire 1 H$ clk $end +$var wire 128 Y$ in[0][0] [127:0] $end +$var wire 128 Z$ in[0][1] [127:0] $end +$var wire 128 [$ in[0][2] [127:0] $end +$var wire 128 \$ in[1][0] [127:0] $end +$var wire 128 ]$ in[1][1] [127:0] $end +$var wire 128 ^$ in[1][2] [127:0] $end +$var wire 8 _$ out[0][0] [7:0] $end +$var wire 8 `$ out[0][1] [7:0] $end +$var wire 8 a$ out[0][2] [7:0] $end +$var wire 8 b$ out[1][0] [7:0] $end +$var wire 8 c$ out[1][1] [7:0] $end +$var wire 8 d$ out[1][2] [7:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 e$ i [31:0] $end +$scope module unnamedblk2 $end +$var int 32 f$ j [31:0] $end +$scope module unnamedblk3 $end +$var byte 8 g$ exp [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end +$var wire 1 h$ clk $end +$var wire 128 i$ in[0][0] [127:0] $end +$var wire 128 j$ in[0][1] [127:0] $end +$var wire 128 k$ in[0][2] [127:0] $end +$var wire 128 l$ in[1][0] [127:0] $end +$var wire 128 m$ in[1][1] [127:0] $end +$var wire 128 n$ in[1][2] [127:0] $end +$var wire 8 o$ out[0][0] [7:0] $end +$var wire 8 p$ out[0][1] [7:0] $end +$var wire 8 q$ out[0][2] [7:0] $end +$var wire 8 r$ out[1][0] [7:0] $end +$var wire 8 s$ out[1][1] [7:0] $end +$var wire 8 t$ out[1][2] [7:0] $end +$scope module sub5 $end +$var wire 1 h$ clk $end +$var wire 128 i$ in[0][0] [127:0] $end +$var wire 128 j$ in[0][1] [127:0] $end +$var wire 128 k$ in[0][2] [127:0] $end +$var wire 128 l$ in[1][0] [127:0] $end +$var wire 128 m$ in[1][1] [127:0] $end +$var wire 128 n$ in[1][2] [127:0] $end +$var wire 8 o$ out[0][0] [7:0] $end +$var wire 8 p$ out[0][1] [7:0] $end +$var wire 8 q$ out[0][2] [7:0] $end +$var wire 8 r$ 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W! +b00000001 H" +b00000001 0# +b00000001 !$ +b00000001 g$ +b00011101 $ +b00011101 D +b00011101 F +b00011101 G +b00011101 J +b00011101 N +b00011101 O +b00011101 R +b00011101 S +b00011101 :! +b00011101 ;! +b00011101 !" +b00011101 X# +b00010101 ( +b00010101 3 +b00010101 9 +b00011011 % +b00011011 & +b00011011 + +b00011011 ; +b00011011 "" +b00011011 '" +b00011011 (" +b00011011 +" +b00011011 ," +b00011011 q" +b00011011 r" +b00011011 Y# +b00011011 ^# +b00011011 _# +b00011011 b# +b00011011 c# +b00011011 J$ +b00011011 K$ +b00011001 C +b00011001 A +b00011001 @ +b00011001 # +b00011000 ' +b00011000 , +b00011000 0 +b00011000 2 diff --git a/test_regress/t/t_hier_block_trace_fst.pl b/test_regress/t/t_hier_block_trace_fst.pl new file mode 100755 index 000000000..29213f97b --- /dev/null +++ b/test_regress/t/t_hier_block_trace_fst.pl @@ -0,0 +1,35 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(vlt_all => 1); + +top_filename("t/t_hier_block.v"); + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performace wise, but ok. + +compile( + v_flags2 => ['t/t_hier_block.cpp'], + verilator_flags2 => [($Self->{vltmt} ? ' --threads 6' : ''), + '--hierarchical', + '--Wno-TIMESCALEMOD', + '--trace-fst', + '--no-trace-underscore', # To avoid handle mismatches + ], + ); + +execute( + check_finished => 1, + ); + +fst_identical($Self->trace_filename, $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_hier_block_trace.out b/test_regress/t/t_hier_block_trace_vcd.out similarity index 100% rename from test_regress/t/t_hier_block_trace.out rename to test_regress/t/t_hier_block_trace_vcd.out diff --git a/test_regress/t/t_hier_block_trace.pl b/test_regress/t/t_hier_block_trace_vcd.pl similarity index 100% rename from test_regress/t/t_hier_block_trace.pl rename to test_regress/t/t_hier_block_trace_vcd.pl diff --git a/test_regress/t/t_incr_void.pl b/test_regress/t/t_incr_void.pl new file mode 100755 index 000000000..5b95e5b74 --- /dev/null +++ b/test_regress/t/t_incr_void.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--Os -x-assign 0"], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_incr_void.v b/test_regress/t/t_incr_void.v new file mode 100644 index 000000000..eebf410aa --- /dev/null +++ b/test_regress/t/t_incr_void.v @@ -0,0 +1,55 @@ +module t + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + int cyc = 0; + + always @ (posedge clk) begin : main + cyc <= cyc + 1; + + if (cyc > 100) begin + $write("*-* All Finished *-*\n"); + $finish(); + end + end + + + + logic [3:0] count_d; + logic [3:0] count_q = '0; + + logic [3:0] want_count_d; + logic [3:0] want_count_q = '0; + + always_ff @(posedge clk) begin : flops + count_q <= count_d; + want_count_q <= want_count_d; + end + + always @(posedge clk) begin : simple_check + if (cyc > 0) begin + if (count_q !== want_count_q) begin + $error("%m: cyc=%0d, count_q (%0d) !== want_count_q (%0d)", + cyc, count_q, want_count_q); + $stop; // don't finish to fail the test. + end + end + end + + always_comb begin : update_golden_counts + want_count_d = want_count_q; + want_count_d += 1'b1; + end + + // make sure an implicit void cast on n++ works as expected. + always_comb begin : update_counts + count_d = count_q; + count_d++; + end + + +endmodule diff --git a/test_regress/t/t_inst_tree_inl0_pub0.pl b/test_regress/t/t_inst_tree_inl0_pub0.pl index 6037619f7..8f0584454 100755 --- a/test_regress/t/t_inst_tree_inl0_pub0.pl +++ b/test_regress/t/t_inst_tree_inl0_pub0.pl @@ -18,12 +18,12 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_inst_tree_inl1_pub0.pl b/test_regress/t/t_inst_tree_inl1_pub0.pl index 9a8a6aa92..9e8e50970 100755 --- a/test_regress/t/t_inst_tree_inl1_pub0.pl +++ b/test_regress/t/t_inst_tree_inl1_pub0.pl @@ -18,9 +18,9 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_inst_tree_inl1_pub1.pl b/test_regress/t/t_inst_tree_inl1_pub1.pl index ed87d615c..2c8ff9ac9 100755 --- a/test_regress/t/t_inst_tree_inl1_pub1.pl +++ b/test_regress/t/t_inst_tree_inl1_pub1.pl @@ -19,9 +19,9 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_interface_ref_trace_fst.out b/test_regress/t/t_interface_ref_trace_fst.out index ffe8c0410..f26bb0647 100644 --- a/test_regress/t/t_interface_ref_trace_fst.out +++ b/test_regress/t/t_interface_ref_trace_fst.out @@ -1,5 +1,5 @@ $date - Sun Apr 19 04:13:22 2020 + Tue Feb 22 23:55:07 2022 $end $version @@ -12,593 +12,587 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$scope interface intf_1 $end +$var integer 32 " cyc [31:0] $end +$scope module a $end +$scope module ac1 $end +$scope interface intf_for_check $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end $scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end -$scope module s1 $end +$upscope $end +$scope module ac2 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end +$scope struct the_struct $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module ac3 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 ) value [31:0] $end +$scope struct the_struct $end +$var logic 32 * val100 [31:0] $end +$var logic 32 + val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module as3 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 ) value [31:0] $end $scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end +$var logic 32 * val100 [31:0] $end +$var logic 32 + val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope interface intf_in_sub_all $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 ) value [31:0] $end +$scope struct the_struct $end +$var logic 32 * val100 [31:0] $end +$var logic 32 + val200 [31:0] $end +$upscope $end +$upscope $end +$scope interface intf_one $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end +$scope struct the_struct $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end +$upscope $end +$upscope $end +$scope interface intf_two $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end +$scope struct the_struct $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module abcdefghijklmnopqrstuvwxyz $end +$scope module ac1 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end +$scope struct the_struct $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module ac2 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end +$scope struct the_struct $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module ac3 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 , value [31:0] $end +$scope struct the_struct $end +$var logic 32 - val100 [31:0] $end +$var logic 32 . val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module as3 $end +$scope interface intf_for_struct $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 , value [31:0] $end +$scope struct the_struct $end +$var logic 32 - val100 [31:0] $end +$var logic 32 . val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope interface intf_in_sub_all $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 , value [31:0] $end +$scope struct the_struct $end +$var logic 32 - val100 [31:0] $end +$var logic 32 . val200 [31:0] $end +$upscope $end +$upscope $end +$scope interface intf_one $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end +$scope struct the_struct $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end +$upscope $end +$upscope $end +$scope interface intf_two $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end +$scope struct the_struct $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c1 $end $scope interface intf_for_check $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end $scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$upscope $end -$scope module a $end -$scope interface intf_one $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end -$scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$scope module ac1 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end -$scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module abcdefghijklmnopqrstuvwxyz $end -$scope interface intf_two $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end -$scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$scope module ac2 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end -$scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope interface intf_2 $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end -$scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end -$upscope $end -$upscope $end -$scope module s2 $end -$scope interface intf_for_struct $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end -$scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c2 $end $scope interface intf_for_check $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end $scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end $upscope $end $upscope $end $upscope $end -$scope module a $end -$scope interface intf_two $end +$scope interface intf_1 $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end $scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end -$scope module ac2 $end -$scope interface intf_for_check $end +$scope interface intf_2 $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end $scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end $upscope $end $upscope $end -$upscope $end -$upscope $end -$scope module abcdefghijklmnopqrstuvwxyz $end -$scope interface intf_one $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end -$scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end -$upscope $end -$upscope $end -$scope module ac1 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end -$scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module a $end -$scope interface intf_in_sub_all $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 ) value $end -$scope struct the_struct $end -$var logic 32 * val100 $end -$var logic 32 + val200 $end -$upscope $end -$upscope $end -$scope module as3 $end +$scope module s1 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 ) value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end $scope struct the_struct $end -$var logic 32 * val100 $end -$var logic 32 + val200 $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end $upscope $end -$scope module ac3 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 ) value $end -$scope struct the_struct $end -$var logic 32 * val100 $end -$var logic 32 + val200 $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module abcdefghijklmnopqrstuvwxyz $end -$scope interface intf_in_sub_all $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 , value $end -$scope struct the_struct $end -$var logic 32 - val100 $end -$var logic 32 . val200 $end -$upscope $end -$upscope $end -$scope module as3 $end +$scope module s2 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 , value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end $scope struct the_struct $end -$var logic 32 - val100 $end -$var logic 32 . val200 $end -$upscope $end -$upscope $end -$upscope $end -$scope module ac3 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 , value $end -$scope struct the_struct $end -$var logic 32 - val100 $end -$var logic 32 . val200 $end -$upscope $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end +#0 $dumpvars -0! -b00000000000000000000000000000000 " -b00000000000000000000000000000001 # -b00000000000000000000000001100101 $ -b00000000000000000000000011001001 % -b00000000000000000000000000000010 & -b00000000000000000000000001100110 ' -b00000000000000000000000011001010 ( -b00000000000000000000001111101001 ) -b00000000000000000000010001001101 * -b00000000000000000000010010110001 + -b00000000000000000000001111101010 , -b00000000000000000000010001001110 - b00000000000000000000010010110010 . +b00000000000000000000010001001110 - +b00000000000000000000001111101010 , +b00000000000000000000010010110001 + +b00000000000000000000010001001101 * +b00000000000000000000001111101001 ) +b00000000000000000000000011001010 ( +b00000000000000000000000001100110 ' +b00000000000000000000000000000010 & +b00000000000000000000000011001001 % +b00000000000000000000000001100101 $ +b00000000000000000000000000000001 # +b00000000000000000000000000000000 " +0! +$end #10 -b00000000000000000000010010110011 . -b00000000000000000000010001001111 - -b00000000000000000000001111101011 , -b00000000000000000000010010110010 + -b00000000000000000000010001001110 * -b00000000000000000000001111101010 ) -b00000000000000000000000011001011 ( -b00000000000000000000000001100111 ' -b00000000000000000000000000000011 & -b00000000000000000000000011001010 % -b00000000000000000000000001100110 $ -b00000000000000000000000000000010 # -b00000000000000000000000000000001 " 1! +b00000000000000000000000000000001 " +b00000000000000000000000000000010 # +b00000000000000000000000001100110 $ +b00000000000000000000000011001010 % +b00000000000000000000000000000011 & +b00000000000000000000000001100111 ' +b00000000000000000000000011001011 ( +b00000000000000000000001111101010 ) +b00000000000000000000010001001110 * +b00000000000000000000010010110010 + +b00000000000000000000001111101011 , +b00000000000000000000010001001111 - +b00000000000000000000010010110011 . #15 0! #20 1! -b00000000000000000000000000000010 " -b00000000000000000000000000000011 # -b00000000000000000000000001100111 $ -b00000000000000000000000011001011 % -b00000000000000000000000000000100 & -b00000000000000000000000001101000 ' -b00000000000000000000000011001100 ( -b00000000000000000000001111101011 ) -b00000000000000000000010001001111 * -b00000000000000000000010010110011 + -b00000000000000000000001111101100 , -b00000000000000000000010001010000 - b00000000000000000000010010110100 . +b00000000000000000000010001010000 - +b00000000000000000000001111101100 , +b00000000000000000000010010110011 + +b00000000000000000000010001001111 * +b00000000000000000000001111101011 ) +b00000000000000000000000011001100 ( +b00000000000000000000000001101000 ' +b00000000000000000000000000000100 & +b00000000000000000000000011001011 % +b00000000000000000000000001100111 $ +b00000000000000000000000000000011 # +b00000000000000000000000000000010 " #25 0! #30 1! -b00000000000000000000010010110101 . -b00000000000000000000010001010001 - -b00000000000000000000001111101101 , -b00000000000000000000010010110100 + -b00000000000000000000010001010000 * -b00000000000000000000001111101100 ) -b00000000000000000000000011001101 ( -b00000000000000000000000001101001 ' -b00000000000000000000000000000101 & -b00000000000000000000000011001100 % -b00000000000000000000000001101000 $ -b00000000000000000000000000000100 # b00000000000000000000000000000011 " +b00000000000000000000000000000100 # +b00000000000000000000000001101000 $ +b00000000000000000000000011001100 % +b00000000000000000000000000000101 & +b00000000000000000000000001101001 ' +b00000000000000000000000011001101 ( +b00000000000000000000001111101100 ) +b00000000000000000000010001010000 * +b00000000000000000000010010110100 + +b00000000000000000000001111101101 , +b00000000000000000000010001010001 - +b00000000000000000000010010110101 . #35 0! #40 1! -b00000000000000000000000000000100 " -b00000000000000000000000000000101 # -b00000000000000000000000001101001 $ -b00000000000000000000000011001101 % -b00000000000000000000000000000110 & -b00000000000000000000000001101010 ' -b00000000000000000000000011001110 ( -b00000000000000000000001111101101 ) -b00000000000000000000010001010001 * -b00000000000000000000010010110101 + -b00000000000000000000001111101110 , -b00000000000000000000010001010010 - b00000000000000000000010010110110 . +b00000000000000000000010001010010 - +b00000000000000000000001111101110 , +b00000000000000000000010010110101 + +b00000000000000000000010001010001 * +b00000000000000000000001111101101 ) +b00000000000000000000000011001110 ( +b00000000000000000000000001101010 ' +b00000000000000000000000000000110 & +b00000000000000000000000011001101 % +b00000000000000000000000001101001 $ +b00000000000000000000000000000101 # +b00000000000000000000000000000100 " #45 0! #50 1! -b00000000000000000000010010110111 . -b00000000000000000000010001010011 - -b00000000000000000000001111101111 , -b00000000000000000000010010110110 + -b00000000000000000000010001010010 * -b00000000000000000000001111101110 ) -b00000000000000000000000011001111 ( -b00000000000000000000000001101011 ' -b00000000000000000000000000000111 & -b00000000000000000000000011001110 % -b00000000000000000000000001101010 $ -b00000000000000000000000000000110 # b00000000000000000000000000000101 " +b00000000000000000000000000000110 # +b00000000000000000000000001101010 $ +b00000000000000000000000011001110 % +b00000000000000000000000000000111 & +b00000000000000000000000001101011 ' +b00000000000000000000000011001111 ( +b00000000000000000000001111101110 ) +b00000000000000000000010001010010 * +b00000000000000000000010010110110 + +b00000000000000000000001111101111 , +b00000000000000000000010001010011 - +b00000000000000000000010010110111 . #55 0! #60 1! -b00000000000000000000000000000110 " -b00000000000000000000000000000111 # -b00000000000000000000000001101011 $ -b00000000000000000000000011001111 % -b00000000000000000000000000001000 & -b00000000000000000000000001101100 ' -b00000000000000000000000011010000 ( -b00000000000000000000001111101111 ) -b00000000000000000000010001010011 * -b00000000000000000000010010110111 + -b00000000000000000000001111110000 , -b00000000000000000000010001010100 - b00000000000000000000010010111000 . +b00000000000000000000010001010100 - +b00000000000000000000001111110000 , +b00000000000000000000010010110111 + +b00000000000000000000010001010011 * +b00000000000000000000001111101111 ) +b00000000000000000000000011010000 ( +b00000000000000000000000001101100 ' +b00000000000000000000000000001000 & +b00000000000000000000000011001111 % +b00000000000000000000000001101011 $ +b00000000000000000000000000000111 # +b00000000000000000000000000000110 " #65 0! #70 1! -b00000000000000000000010010111001 . -b00000000000000000000010001010101 - -b00000000000000000000001111110001 , -b00000000000000000000010010111000 + -b00000000000000000000010001010100 * -b00000000000000000000001111110000 ) -b00000000000000000000000011010001 ( -b00000000000000000000000001101101 ' -b00000000000000000000000000001001 & -b00000000000000000000000011010000 % -b00000000000000000000000001101100 $ -b00000000000000000000000000001000 # b00000000000000000000000000000111 " +b00000000000000000000000000001000 # +b00000000000000000000000001101100 $ +b00000000000000000000000011010000 % +b00000000000000000000000000001001 & +b00000000000000000000000001101101 ' +b00000000000000000000000011010001 ( +b00000000000000000000001111110000 ) +b00000000000000000000010001010100 * +b00000000000000000000010010111000 + +b00000000000000000000001111110001 , +b00000000000000000000010001010101 - +b00000000000000000000010010111001 . #75 0! #80 1! -b00000000000000000000000000001000 " -b00000000000000000000000000001001 # -b00000000000000000000000001101101 $ -b00000000000000000000000011010001 % -b00000000000000000000000000001010 & -b00000000000000000000000001101110 ' -b00000000000000000000000011010010 ( -b00000000000000000000001111110001 ) -b00000000000000000000010001010101 * -b00000000000000000000010010111001 + -b00000000000000000000001111110010 , -b00000000000000000000010001010110 - b00000000000000000000010010111010 . +b00000000000000000000010001010110 - +b00000000000000000000001111110010 , +b00000000000000000000010010111001 + +b00000000000000000000010001010101 * +b00000000000000000000001111110001 ) +b00000000000000000000000011010010 ( +b00000000000000000000000001101110 ' +b00000000000000000000000000001010 & +b00000000000000000000000011010001 % +b00000000000000000000000001101101 $ +b00000000000000000000000000001001 # +b00000000000000000000000000001000 " #85 0! #90 1! -b00000000000000000000010010111011 . -b00000000000000000000010001010111 - -b00000000000000000000001111110011 , -b00000000000000000000010010111010 + -b00000000000000000000010001010110 * -b00000000000000000000001111110010 ) -b00000000000000000000000011010011 ( -b00000000000000000000000001101111 ' -b00000000000000000000000000001011 & -b00000000000000000000000011010010 % -b00000000000000000000000001101110 $ -b00000000000000000000000000001010 # b00000000000000000000000000001001 " +b00000000000000000000000000001010 # +b00000000000000000000000001101110 $ +b00000000000000000000000011010010 % +b00000000000000000000000000001011 & +b00000000000000000000000001101111 ' +b00000000000000000000000011010011 ( +b00000000000000000000001111110010 ) +b00000000000000000000010001010110 * +b00000000000000000000010010111010 + +b00000000000000000000001111110011 , +b00000000000000000000010001010111 - +b00000000000000000000010010111011 . #95 0! #100 1! -b00000000000000000000000000001010 " -b00000000000000000000000000001011 # -b00000000000000000000000001101111 $ -b00000000000000000000000011010011 % -b00000000000000000000000000001100 & -b00000000000000000000000001110000 ' -b00000000000000000000000011010100 ( -b00000000000000000000001111110011 ) -b00000000000000000000010001010111 * -b00000000000000000000010010111011 + -b00000000000000000000001111110100 , -b00000000000000000000010001011000 - b00000000000000000000010010111100 . +b00000000000000000000010001011000 - +b00000000000000000000001111110100 , +b00000000000000000000010010111011 + +b00000000000000000000010001010111 * +b00000000000000000000001111110011 ) +b00000000000000000000000011010100 ( +b00000000000000000000000001110000 ' +b00000000000000000000000000001100 & +b00000000000000000000000011010011 % +b00000000000000000000000001101111 $ +b00000000000000000000000000001011 # +b00000000000000000000000000001010 " #105 0! #110 1! -b00000000000000000000010010111101 . -b00000000000000000000010001011001 - -b00000000000000000000001111110101 , -b00000000000000000000010010111100 + -b00000000000000000000010001011000 * -b00000000000000000000001111110100 ) -b00000000000000000000000011010101 ( -b00000000000000000000000001110001 ' -b00000000000000000000000000001101 & -b00000000000000000000000011010100 % -b00000000000000000000000001110000 $ -b00000000000000000000000000001100 # b00000000000000000000000000001011 " +b00000000000000000000000000001100 # +b00000000000000000000000001110000 $ +b00000000000000000000000011010100 % +b00000000000000000000000000001101 & +b00000000000000000000000001110001 ' +b00000000000000000000000011010101 ( +b00000000000000000000001111110100 ) +b00000000000000000000010001011000 * +b00000000000000000000010010111100 + +b00000000000000000000001111110101 , +b00000000000000000000010001011001 - +b00000000000000000000010010111101 . #115 0! #120 1! -b00000000000000000000000000001100 " -b00000000000000000000000000001101 # -b00000000000000000000000001110001 $ -b00000000000000000000000011010101 % -b00000000000000000000000000001110 & -b00000000000000000000000001110010 ' -b00000000000000000000000011010110 ( -b00000000000000000000001111110101 ) -b00000000000000000000010001011001 * -b00000000000000000000010010111101 + -b00000000000000000000001111110110 , -b00000000000000000000010001011010 - b00000000000000000000010010111110 . +b00000000000000000000010001011010 - +b00000000000000000000001111110110 , +b00000000000000000000010010111101 + +b00000000000000000000010001011001 * +b00000000000000000000001111110101 ) +b00000000000000000000000011010110 ( +b00000000000000000000000001110010 ' +b00000000000000000000000000001110 & +b00000000000000000000000011010101 % +b00000000000000000000000001110001 $ +b00000000000000000000000000001101 # +b00000000000000000000000000001100 " #125 0! #130 1! -b00000000000000000000010010111111 . -b00000000000000000000010001011011 - -b00000000000000000000001111110111 , -b00000000000000000000010010111110 + -b00000000000000000000010001011010 * -b00000000000000000000001111110110 ) -b00000000000000000000000011010111 ( -b00000000000000000000000001110011 ' -b00000000000000000000000000001111 & -b00000000000000000000000011010110 % -b00000000000000000000000001110010 $ -b00000000000000000000000000001110 # b00000000000000000000000000001101 " +b00000000000000000000000000001110 # +b00000000000000000000000001110010 $ +b00000000000000000000000011010110 % +b00000000000000000000000000001111 & +b00000000000000000000000001110011 ' +b00000000000000000000000011010111 ( +b00000000000000000000001111110110 ) +b00000000000000000000010001011010 * +b00000000000000000000010010111110 + +b00000000000000000000001111110111 , +b00000000000000000000010001011011 - +b00000000000000000000010010111111 . #135 0! #140 1! -b00000000000000000000000000001110 " -b00000000000000000000000000001111 # -b00000000000000000000000001110011 $ -b00000000000000000000000011010111 % -b00000000000000000000000000010000 & -b00000000000000000000000001110100 ' -b00000000000000000000000011011000 ( -b00000000000000000000001111110111 ) -b00000000000000000000010001011011 * -b00000000000000000000010010111111 + -b00000000000000000000001111111000 , -b00000000000000000000010001011100 - b00000000000000000000010011000000 . +b00000000000000000000010001011100 - +b00000000000000000000001111111000 , +b00000000000000000000010010111111 + +b00000000000000000000010001011011 * +b00000000000000000000001111110111 ) +b00000000000000000000000011011000 ( +b00000000000000000000000001110100 ' +b00000000000000000000000000010000 & +b00000000000000000000000011010111 % +b00000000000000000000000001110011 $ +b00000000000000000000000000001111 # +b00000000000000000000000000001110 " #145 0! #150 1! -b00000000000000000000010011000001 . -b00000000000000000000010001011101 - -b00000000000000000000001111111001 , -b00000000000000000000010011000000 + -b00000000000000000000010001011100 * -b00000000000000000000001111111000 ) -b00000000000000000000000011011001 ( -b00000000000000000000000001110101 ' -b00000000000000000000000000010001 & -b00000000000000000000000011011000 % -b00000000000000000000000001110100 $ -b00000000000000000000000000010000 # b00000000000000000000000000001111 " +b00000000000000000000000000010000 # +b00000000000000000000000001110100 $ +b00000000000000000000000011011000 % +b00000000000000000000000000010001 & +b00000000000000000000000001110101 ' +b00000000000000000000000011011001 ( +b00000000000000000000001111111000 ) +b00000000000000000000010001011100 * +b00000000000000000000010011000000 + +b00000000000000000000001111111001 , +b00000000000000000000010001011101 - +b00000000000000000000010011000001 . #155 0! #160 1! -b00000000000000000000000000010000 " -b00000000000000000000000000010001 # -b00000000000000000000000001110101 $ -b00000000000000000000000011011001 % -b00000000000000000000000000010010 & -b00000000000000000000000001110110 ' -b00000000000000000000000011011010 ( -b00000000000000000000001111111001 ) -b00000000000000000000010001011101 * -b00000000000000000000010011000001 + -b00000000000000000000001111111010 , -b00000000000000000000010001011110 - b00000000000000000000010011000010 . +b00000000000000000000010001011110 - +b00000000000000000000001111111010 , +b00000000000000000000010011000001 + +b00000000000000000000010001011101 * +b00000000000000000000001111111001 ) +b00000000000000000000000011011010 ( +b00000000000000000000000001110110 ' +b00000000000000000000000000010010 & +b00000000000000000000000011011001 % +b00000000000000000000000001110101 $ +b00000000000000000000000000010001 # +b00000000000000000000000000010000 " #165 0! #170 1! -b00000000000000000000010011000011 . -b00000000000000000000010001011111 - -b00000000000000000000001111111011 , -b00000000000000000000010011000010 + -b00000000000000000000010001011110 * -b00000000000000000000001111111010 ) -b00000000000000000000000011011011 ( -b00000000000000000000000001110111 ' -b00000000000000000000000000010011 & -b00000000000000000000000011011010 % -b00000000000000000000000001110110 $ -b00000000000000000000000000010010 # b00000000000000000000000000010001 " +b00000000000000000000000000010010 # +b00000000000000000000000001110110 $ +b00000000000000000000000011011010 % +b00000000000000000000000000010011 & +b00000000000000000000000001110111 ' +b00000000000000000000000011011011 ( +b00000000000000000000001111111010 ) +b00000000000000000000010001011110 * +b00000000000000000000010011000010 + +b00000000000000000000001111111011 , +b00000000000000000000010001011111 - +b00000000000000000000010011000011 . #175 0! #180 1! -b00000000000000000000000000010010 " -b00000000000000000000000000010011 # -b00000000000000000000000001110111 $ -b00000000000000000000000011011011 % -b00000000000000000000000000010100 & -b00000000000000000000000001111000 ' -b00000000000000000000000011011100 ( -b00000000000000000000001111111011 ) -b00000000000000000000010001011111 * -b00000000000000000000010011000011 + -b00000000000000000000001111111100 , -b00000000000000000000010001100000 - b00000000000000000000010011000100 . +b00000000000000000000010001100000 - +b00000000000000000000001111111100 , +b00000000000000000000010011000011 + +b00000000000000000000010001011111 * +b00000000000000000000001111111011 ) +b00000000000000000000000011011100 ( +b00000000000000000000000001111000 ' +b00000000000000000000000000010100 & +b00000000000000000000000011011011 % +b00000000000000000000000001110111 $ +b00000000000000000000000000010011 # +b00000000000000000000000000010010 " #185 0! #190 1! -b00000000000000000000010011000101 . -b00000000000000000000010001100001 - -b00000000000000000000001111111101 , -b00000000000000000000010011000100 + -b00000000000000000000010001100000 * -b00000000000000000000001111111100 ) -b00000000000000000000000011011101 ( -b00000000000000000000000001111001 ' -b00000000000000000000000000010101 & -b00000000000000000000000011011100 % -b00000000000000000000000001111000 $ -b00000000000000000000000000010100 # b00000000000000000000000000010011 " +b00000000000000000000000000010100 # +b00000000000000000000000001111000 $ +b00000000000000000000000011011100 % +b00000000000000000000000000010101 & +b00000000000000000000000001111001 ' +b00000000000000000000000011011101 ( +b00000000000000000000001111111100 ) +b00000000000000000000010001100000 * +b00000000000000000000010011000100 + +b00000000000000000000001111111101 , +b00000000000000000000010001100001 - +b00000000000000000000010011000101 . #195 0! #200 1! -b00000000000000000000000000010100 " -b00000000000000000000000000010101 # -b00000000000000000000000001111001 $ -b00000000000000000000000011011101 % -b00000000000000000000000000010110 & -b00000000000000000000000001111010 ' -b00000000000000000000000011011110 ( -b00000000000000000000001111111101 ) -b00000000000000000000010001100001 * -b00000000000000000000010011000101 + -b00000000000000000000001111111110 , -b00000000000000000000010001100010 - b00000000000000000000010011000110 . +b00000000000000000000010001100010 - +b00000000000000000000001111111110 , +b00000000000000000000010011000101 + +b00000000000000000000010001100001 * +b00000000000000000000001111111101 ) +b00000000000000000000000011011110 ( +b00000000000000000000000001111010 ' +b00000000000000000000000000010110 & +b00000000000000000000000011011101 % +b00000000000000000000000001111001 $ +b00000000000000000000000000010101 # +b00000000000000000000000000010100 " #205 0! #210 1! -b00000000000000000000010011000111 . -b00000000000000000000010001100011 - -b00000000000000000000001111111111 , -b00000000000000000000010011000110 + -b00000000000000000000010001100010 * -b00000000000000000000001111111110 ) -b00000000000000000000000011011111 ( -b00000000000000000000000001111011 ' -b00000000000000000000000000010111 & -b00000000000000000000000011011110 % -b00000000000000000000000001111010 $ -b00000000000000000000000000010110 # b00000000000000000000000000010101 " +b00000000000000000000000000010110 # +b00000000000000000000000001111010 $ +b00000000000000000000000011011110 % +b00000000000000000000000000010111 & +b00000000000000000000000001111011 ' +b00000000000000000000000011011111 ( +b00000000000000000000001111111110 ) +b00000000000000000000010001100010 * +b00000000000000000000010011000110 + +b00000000000000000000001111111111 , +b00000000000000000000010001100011 - +b00000000000000000000010011000111 . diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.out b/test_regress/t/t_interface_ref_trace_fst_sc.out index 753dc7847..dbbfe4f3b 100644 --- a/test_regress/t/t_interface_ref_trace_fst_sc.out +++ b/test_regress/t/t_interface_ref_trace_fst_sc.out @@ -1,5 +1,5 @@ $date - Thu Apr 1 14:51:24 2021 + Tue Feb 22 23:55:19 2022 $end $version @@ -11,220 +11,212 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$scope interface intf_1 $end +$var integer 32 " cyc [31:0] $end +$scope module a $end +$scope module ac1 $end +$scope interface intf_for_check $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end $scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end -$scope module s1 $end +$upscope $end +$scope module ac2 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end +$scope struct the_struct $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module ac3 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 ) value [31:0] $end +$scope struct the_struct $end +$var logic 32 * val100 [31:0] $end +$var logic 32 + val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module as3 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 ) value [31:0] $end $scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end +$var logic 32 * val100 [31:0] $end +$var logic 32 + val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope interface intf_in_sub_all $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 ) value [31:0] $end +$scope struct the_struct $end +$var logic 32 * val100 [31:0] $end +$var logic 32 + val200 [31:0] $end +$upscope $end +$upscope $end +$scope interface intf_one $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end +$scope struct the_struct $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end +$upscope $end +$upscope $end +$scope interface intf_two $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end +$scope struct the_struct $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module abcdefghijklmnopqrstuvwxyz $end +$scope module ac1 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end +$scope struct the_struct $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module ac2 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end +$scope struct the_struct $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module ac3 $end +$scope interface intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 , value [31:0] $end +$scope struct the_struct $end +$var logic 32 - val100 [31:0] $end +$var logic 32 . val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module as3 $end +$scope interface intf_for_struct $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 , value [31:0] $end +$scope struct the_struct $end +$var logic 32 - val100 [31:0] $end +$var logic 32 . val200 [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope interface intf_in_sub_all $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 , value [31:0] $end +$scope struct the_struct $end +$var logic 32 - val100 [31:0] $end +$var logic 32 . val200 [31:0] $end +$upscope $end +$upscope $end +$scope interface intf_one $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end +$scope struct the_struct $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end +$upscope $end +$upscope $end +$scope interface intf_two $end +$var wire 1 ! clk $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end +$scope struct the_struct $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c1 $end $scope interface intf_for_check $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end $scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$upscope $end -$scope module a $end -$scope interface intf_one $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end -$scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$scope module ac1 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end -$scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module abcdefghijklmnopqrstuvwxyz $end -$scope interface intf_two $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end -$scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$scope module ac2 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 # value $end -$scope struct the_struct $end -$var logic 32 $ val100 $end -$var logic 32 % val200 $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope interface intf_2 $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end -$scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end -$upscope $end -$upscope $end -$scope module s2 $end -$scope interface intf_for_struct $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end -$scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c2 $end $scope interface intf_for_check $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end $scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end $upscope $end $upscope $end $upscope $end -$scope module a $end -$scope interface intf_two $end +$scope interface intf_1 $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end $scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end -$scope module ac2 $end -$scope interface intf_for_check $end +$scope interface intf_2 $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end $scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end $upscope $end $upscope $end -$upscope $end -$upscope $end -$scope module abcdefghijklmnopqrstuvwxyz $end -$scope interface intf_one $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end -$scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end -$upscope $end -$upscope $end -$scope module ac1 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 & value $end -$scope struct the_struct $end -$var logic 32 ' val100 $end -$var logic 32 ( val200 $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module a $end -$scope interface intf_in_sub_all $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 ) value $end -$scope struct the_struct $end -$var logic 32 * val100 $end -$var logic 32 + val200 $end -$upscope $end -$upscope $end -$scope module as3 $end +$scope module s1 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 ) value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 # value [31:0] $end $scope struct the_struct $end -$var logic 32 * val100 $end -$var logic 32 + val200 $end +$var logic 32 $ val100 [31:0] $end +$var logic 32 % val200 [31:0] $end $upscope $end $upscope $end $upscope $end -$scope module ac3 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 ) value $end -$scope struct the_struct $end -$var logic 32 * val100 $end -$var logic 32 + val200 $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module abcdefghijklmnopqrstuvwxyz $end -$scope interface intf_in_sub_all $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 , value $end -$scope struct the_struct $end -$var logic 32 - val100 $end -$var logic 32 . val200 $end -$upscope $end -$upscope $end -$scope module as3 $end +$scope module s2 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 , value $end +$var wire 32 " cyc [31:0] $end +$var integer 32 & value [31:0] $end $scope struct the_struct $end -$var logic 32 - val100 $end -$var logic 32 . val200 $end -$upscope $end -$upscope $end -$upscope $end -$scope module ac3 $end -$scope interface intf_for_check $end -$var wire 1 ! clk $end -$var wire 32 " cyc $end -$var integer 32 , value $end -$scope struct the_struct $end -$var logic 32 - val100 $end -$var logic 32 . val200 $end -$upscope $end +$var logic 32 ' val100 [31:0] $end +$var logic 32 ( val200 [31:0] $end $upscope $end $upscope $end $upscope $end diff --git a/test_regress/t/t_leak.cpp b/test_regress/t/t_leak.cpp index f9bdf3bda..a70ecda6d 100644 --- a/test_regress/t/t_leak.cpp +++ b/test_regress/t/t_leak.cpp @@ -33,7 +33,7 @@ long long get_memory_usage() { int items = fscanf(fp, ("%d (%*[^) ]) %*1s %d %*d %*d %*d %*d %u" " %u %u %u %u %d %d %d %d" - " %*d %*d %*u %*u %d %" VL_PRI64 "u %" VL_PRI64 "u "), + " %*d %*d %*u %*u %d %" PRIu64 " %" PRIu64 " "), &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_vsize, &ps_rss); fclose(fp); @@ -85,7 +85,7 @@ int main(int argc, char* argv[]) { make_and_destroy(); } firstUsage = get_memory_usage(); - printf("Memory size %" VL_PRI64 "d bytes\n", firstUsage); + printf("Memory size %" PRId64 " bytes\n", firstUsage); int loops = 10; for (int left = loops; left > 0;) { @@ -96,7 +96,7 @@ int main(int argc, char* argv[]) { vluint64_t leaked = get_memory_usage() - firstUsage; if (leaked > 64 * 1024) { // Have to allow some slop for this code. - printf("Leaked %" VL_PRI64 "d bytes, or ~ %" VL_PRI64 "d bytes/construt\n", // + printf("Leaked %" PRId64 " bytes, or ~ %" PRId64 " bytes/construt\n", // leaked, leaked / loops); vl_fatal(__FILE__, __LINE__, "top", "Leaked memory\n"); } diff --git a/test_regress/t/t_lint_once_bad.out b/test_regress/t/t_lint_once_bad.out index 4a8917764..04dca3c21 100644 --- a/test_regress/t/t_lint_once_bad.out +++ b/test_regress/t/t_lint_once_bad.out @@ -1,11 +1,11 @@ %Warning-UNUSED: t/t_lint_once_bad.v:19:14: Signal is not driven, nor used: 'unus1' - : ... In instance t.sub3 + : ... In instance t.sub1 19 | reg [A:0] unus1; reg [A:0] unus2; | ^~~~~ ... For warning description see https://verilator.org/warn/UNUSED?v=latest ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_once_bad.v:19:34: Signal is not driven, nor used: 'unus2' - : ... In instance t.sub3 + : ... In instance t.sub1 19 | reg [A:0] unus1; reg [A:0] unus2; | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_repeat_bad.out b/test_regress/t/t_lint_repeat_bad.out index 2d8287e78..35067222b 100644 --- a/test_regress/t/t_lint_repeat_bad.out +++ b/test_regress/t/t_lint_repeat_bad.out @@ -1,5 +1,5 @@ %Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits. - : ... In instance t.sub2 + : ... In instance t.sub3 18 | wire [0:0] b = a; | ^ ... For warning description see https://verilator.org/warn/WIDTH?v=latest diff --git a/test_regress/t/t_lint_unused_tri.pl b/test_regress/t/t_lint_unused_tri.pl new file mode 100755 index 000000000..3679f5264 --- /dev/null +++ b/test_regress/t/t_lint_unused_tri.pl @@ -0,0 +1,18 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_unused_tri.v b/test_regress/t/t_lint_unused_tri.v new file mode 100644 index 000000000..4d2646a00 --- /dev/null +++ b/test_regress/t/t_lint_unused_tri.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module Receiver(in); + inout [31:0] in; + always @(in) $display(in); +endmodule + +module Sender(out); + inout [31:0] out; + assign out = 12; +endmodule + +module t; + // ports of submodule recv + tri [31 : 0] recvIn; + + // submodule recv + Receiver recv(.in(recvIn)); + + // submodule send + Sender send(.out(recvIn)); +endmodule diff --git a/test_regress/t/t_lint_width.v b/test_regress/t/t_lint_width.v index 18db807d8..0931dd1b2 100644 --- a/test_regress/t/t_lint_width.v +++ b/test_regress/t/t_lint_width.v @@ -13,6 +13,9 @@ module t (); wire [4:0] sumb = 1'b1 + five; wire [4:0] sumc = five - 1'b1; + wire [4:0] neg5 = - five; + wire [5:0] neg6 = - five; + // Relatively harmless < or <= compared with something less wide localparam [1:0] THREE = 3; int a; diff --git a/test_regress/t/t_math_imm2.cpp b/test_regress/t/t_math_imm2.cpp index 1238fff1f..2736601e0 100644 --- a/test_regress/t/t_math_imm2.cpp +++ b/test_regress/t/t_math_imm2.cpp @@ -36,8 +36,8 @@ int main(int argc, char* argv[]) { | MaskVal(sim->LowMaskSel_Bot, sim->HighMaskSel_Bot)); if (sim->LogicImm != expected) { - printf("%%Error: %d.%d,%d.%d -> %016" VL_PRI64 "x/%016" VL_PRI64 - "x -> %016" VL_PRI64 "x (expected %016" VL_PRI64 "x)\n", + printf("%%Error: %d.%d,%d.%d -> %016" PRIx64 "/%016" PRIx64 " -> %016" PRIx64 + " (expected %016" PRIx64 ")\n", sim->LowMaskSel_Top, sim->HighMaskSel_Top, sim->LowMaskSel_Bot, sim->HighMaskSel_Bot, sim->LowLogicImm, sim->HighLogicImm, sim->LogicImm, expected); diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_precedence.pl index 7cb68e14d..b46d46042 100755 --- a/test_regress/t/t_math_precedence.pl +++ b/test_regress/t/t_math_precedence.pl @@ -10,8 +10,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); -#!$Self->{vcs} or unsupported("VCS does ** wrong, fixed in 2014"); - compile( ); diff --git a/test_regress/t/t_math_signed_calc.pl b/test_regress/t/t_math_signed_calc.pl new file mode 100755 index 000000000..700b77233 --- /dev/null +++ b/test_regress/t/t_math_signed_calc.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Raynard Qiao. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_signed_calc.v b/test_regress/t/t_math_signed_calc.v new file mode 100644 index 000000000..90ce5de34 --- /dev/null +++ b/test_regress/t/t_math_signed_calc.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This mode performs signed number computations in the case of a particular +// interface definition. +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Raynard Qiao. +// SPDX-License-Identifier: CC0-1.0 + +// issure 3294 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [7:0] in0; + reg [7:0] in1; + reg [15:0] out; + initial begin + in0 = 'h2; + in1 = 'hff; + end + Test test(.in0, .in1, .out); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $display("[%0t] clk @ out 'h%0x, expect value='hfffe", $time, out); +`endif + if (out !== 'hfffe) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + + +module Test(in0, in1, out); + input [7:0] in0; + input [7:0] in1; + output [15:0] out; + wire signed [7:0] in1; + wire signed [7:0] in0; + wire signed [15:0] out; + + assign out = $signed({1'b0, in0}) * in1; // this operator should be signed multiplication +endmodule + + diff --git a/test_regress/t/t_order_quad.cpp b/test_regress/t/t_order_quad.cpp index 9f6bd98d8..dab33bd3d 100644 --- a/test_regress/t/t_order_quad.cpp +++ b/test_regress/t/t_order_quad.cpp @@ -20,7 +20,7 @@ bool fail = false; void check(QData got, QData exp) { if (got != exp) { - VL_PRINTF("%%Error: got=0x%" VL_PRI64 "x exp=0x%" VL_PRI64 "x\n", got, exp); + VL_PRINTF("%%Error: got=0x%" PRIx64 " exp=0x%" PRIx64 "\n", got, exp); fail = true; } } diff --git a/test_regress/t/t_protect_ids_key.out b/test_regress/t/t_protect_ids_key.out index 4575b30b0..45059c7d7 100644 --- a/test_regress/t/t_protect_ids_key.out +++ b/test_regress/t/t_protect_ids_key.out @@ -29,8 +29,8 @@ - - + + diff --git a/test_regress/t/t_recursive_module_bug.pl b/test_regress/t/t_recursive_module_bug.pl new file mode 100755 index 000000000..2ef6db6a2 --- /dev/null +++ b/test_regress/t/t_recursive_module_bug.pl @@ -0,0 +1,16 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Geza Lore. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile(); + +ok(1); +1; diff --git a/test_regress/t/t_recursive_module_bug.v b/test_regress/t/t_recursive_module_bug.v new file mode 100644 index 000000000..00d362073 --- /dev/null +++ b/test_regress/t/t_recursive_module_bug.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2022 by Geza Lore. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// This hits a case where parameter specialization of recursive modules +// used to yield a module list that was not topologically sorted, which +// then caused V3Inline to blow up as it assumes that. + +module top #( + parameter N=8 +) ( + input wire [N-1:0] i, + output wire [N-1:0] o, + output wire [N-1:0] a +); + +sub #(.N(N)) inst(.i(i), .o(a)); + +generate if (N > 1) begin: recursive + top #(.N(N/2)) hi(.i(i[N - 1:N/2]), .o(o[N - 1:N/2]), .a()); + top #(.N(N/2)) lo(.i(i[N/2 - 1: 0]), .o(o[N/2 - 1: 0]), .a()); +end else begin: base + assign o = i; +end endgenerate + +endmodule + +module sub #( + parameter N = 8 +) ( + input wire [N-1:0] i, + output wire [N-1:0] o +); + +generate if (N > 1) begin: recursive + sub #(.N(N/2)) hi(.i(i[N - 1:N/2]), .o(o[N - 1:N/2])); + sub #(.N(N/2)) lo(.i(i[N/2 - 1: 0]), .o(o[N/2 - 1: 0])); +end else begin: base + assign o = i; +end endgenerate + +endmodule diff --git a/test_regress/t/t_stream4.pl b/test_regress/t/t_stream4.pl new file mode 100755 index 000000000..b46d46042 --- /dev/null +++ b/test_regress/t/t_stream4.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_stream4.v b/test_regress/t/t_stream4.v new file mode 100644 index 000000000..6bb61425c --- /dev/null +++ b/test_regress/t/t_stream4.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2021 by Adrien Le Masle. +// SPDX-License-Identifier: CC0-1.0 + +//module t; +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + logic [63:0] din; + logic [63:0] dout; + + always_comb begin + dout = {<<8{din}}; + end + + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + + if (cyc == 1) begin + din <= 64'h1122334455667788; + end + + if (cyc == 2) begin + if (dout != 64'h8877665544332211) $stop; + end + + if (cyc == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test_regress/t/t_sys_file_basic.pl b/test_regress/t/t_sys_file_basic.pl index 7b4870947..fe1cedbce 100755 --- a/test_regress/t/t_sys_file_basic.pl +++ b/test_regress/t/t_sys_file_basic.pl @@ -13,7 +13,6 @@ scenarios(simulator => 1); unlink("$Self->{obj_dir}/t_sys_file_basic_test.log"); compile( - v_flags2 => ['+incdir+../include'], # Build without cached objects, see bug363 make_flags => 'VM_PARALLEL_BUILDS=0', ); diff --git a/test_regress/t/t_sys_file_eof.pl b/test_regress/t/t_sys_file_eof.pl new file mode 100755 index 000000000..b46d46042 --- /dev/null +++ b/test_regress/t/t_sys_file_eof.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_sys_file_eof.v b/test_regress/t/t_sys_file_eof.v new file mode 100644 index 000000000..8b8069a4f --- /dev/null +++ b/test_regress/t/t_sys_file_eof.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`include "verilated.v" + +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t; + + integer f; + integer i; + integer j; + + initial begin + f = $fopen("/does-not-exist", "r"); + `checkd(f, 0); + i = $fscanf(f, "check %d", j); + `checkd(i, -1); + i = $fgetc(f); + `checkd(i, -1); + i = $ftell(f); + `checkd(i, -1); + i = $rewind(f); + `checkd(i, -1); + i = $fseek(f, 0, 0); + `checkd(i, -1); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_sys_rand_seed.v b/test_regress/t/t_sys_rand_seed.v index 53dc8eee5..c26867a61 100644 --- a/test_regress/t/t_sys_rand_seed.v +++ b/test_regress/t/t_sys_rand_seed.v @@ -6,16 +6,39 @@ module t; + integer seeda; + integer seedb; + integer seedc; int valuea; int valueb; + int valuec; initial begin - valuea = $random(10); - valueb = $random(10); + // $random unlike $urandom updates the value if given + seeda = 10; + valuea = $random(seeda); + seedb = 10; + valueb = $random(seedb); if (valuea !== valueb) $stop; + + seeda = 10; + valuea = $random(seeda); + seedb = seeda; + valueb = $random(seedb); + seedc = seedb; + valuec = $random(seedc); + if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 + if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64 + valuea = $urandom(10); valueb = $urandom(10); if (valuea !== valueb) $stop; + + valuea = $urandom(10); + valueb = $urandom(); + valuec = $urandom(); + if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_sys_readmem_bad_end.out b/test_regress/t/t_sys_readmem_bad_end.out index 752129a5b..4c6aaf01f 100644 --- a/test_regress/t/t_sys_readmem_bad_end.out +++ b/test_regress/t/t_sys_readmem_bad_end.out @@ -1,2 +1,2 @@ -%Error: t/t_sys_readmem_bad_end.mem:12: $readmem file ended before specified final address (IEEE 2017 21.4) -Aborting... +%Warning: t/t_sys_readmem_bad_end.mem:12: $readmem file ended before specified final address (IEEE 2017 21.4) +*-* All Finished *-* diff --git a/test_regress/t/t_sys_readmem_bad_end.pl b/test_regress/t/t_sys_readmem_bad_end.pl index d89f1290d..56cc415df 100755 --- a/test_regress/t/t_sys_readmem_bad_end.pl +++ b/test_regress/t/t_sys_readmem_bad_end.pl @@ -14,7 +14,6 @@ compile( ); execute( - fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_sys_readmem_bad_end.v b/test_regress/t/t_sys_readmem_bad_end.v index 7aee6a967..772e74f55 100644 --- a/test_regress/t/t_sys_readmem_bad_end.v +++ b/test_regress/t/t_sys_readmem_bad_end.v @@ -11,6 +11,9 @@ module t; integer i; initial begin + // No warning as has addresses + $readmemh("t/t_sys_readmem_bad_end2.mem", hex, 0, 15); + // Warning as wrong end address $readmemh("t/t_sys_readmem_bad_end.mem", hex, 0, 15); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_sys_readmem_bad_end2.mem b/test_regress/t/t_sys_readmem_bad_end2.mem new file mode 100644 index 000000000..d4d4bc48a --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_end2.mem @@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test data file +// +// Copyright 2006 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +10 +11 +@2 +01 +// Missing additional data diff --git a/test_regress/t/t_sys_readmem_bad_notfound.out b/test_regress/t/t_sys_readmem_bad_notfound.out index 317be5d9a..bb1d719c9 100644 --- a/test_regress/t/t_sys_readmem_bad_notfound.out +++ b/test_regress/t/t_sys_readmem_bad_notfound.out @@ -1,2 +1,2 @@ -%Error: t/t_sys_readmem_bad_NOTFOUND.mem:0: $readmem file not found -Aborting... +%Warning: t/t_sys_readmem_bad_NOTFOUND.mem:0: $readmem file not found +*-* All Finished *-* diff --git a/test_regress/t/t_sys_readmem_bad_notfound.pl b/test_regress/t/t_sys_readmem_bad_notfound.pl index d89f1290d..56cc415df 100755 --- a/test_regress/t/t_sys_readmem_bad_notfound.pl +++ b/test_regress/t/t_sys_readmem_bad_notfound.pl @@ -14,7 +14,6 @@ compile( ); execute( - fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_timescale_parse_bad.pl b/test_regress/t/t_timescale_parse_bad.pl index 59ba0d6c6..a60503a1f 100755 --- a/test_regress/t/t_timescale_parse_bad.pl +++ b/test_regress/t/t_timescale_parse_bad.pl @@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(linter => 1); lint( - fails => $Self->{vlt_all}, + fails => 1, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_trace_abort_fst.out b/test_regress/t/t_trace_abort_fst.out index af9505556..2419f3b4e 100644 --- a/test_regress/t/t_trace_abort_fst.out +++ b/test_regress/t/t_trace_abort_fst.out @@ -1,5 +1,5 @@ $date - Wed Jun 10 20:47:01 2020 + Wed Feb 23 00:00:18 2022 $end $version @@ -12,7 +12,7 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var logic 3 " cyc $end +$var logic 3 " cyc [2:0] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_abort_fst_sc.out b/test_regress/t/t_trace_abort_fst_sc.out index a2de34150..c8a48100d 100644 --- a/test_regress/t/t_trace_abort_fst_sc.out +++ b/test_regress/t/t_trace_abort_fst_sc.out @@ -1,5 +1,5 @@ $date - Thu Apr 1 14:55:09 2021 + Wed Feb 23 00:00:24 2022 $end $version @@ -11,7 +11,7 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var logic 3 " cyc $end +$var logic 3 " cyc [2:0] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_array_fst.out b/test_regress/t/t_trace_array_fst.out index 030701a44..134e37aab 100644 --- a/test_regress/t/t_trace_array_fst.out +++ b/test_regress/t/t_trace_array_fst.out @@ -1,5 +1,5 @@ $date - Thu Jul 1 22:53:18 2021 + Wed Feb 23 00:00:41 2022 $end $version @@ -12,9 +12,9 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end +$var integer 32 " cyc [31:0] $end $scope struct biggie $end -$var logic 1048577 # d $end +$var logic 1048577 # d [1048576:0] $end $upscope $end $upscope $end $upscope $end diff --git a/test_regress/t/t_trace_array_fst_sc.out b/test_regress/t/t_trace_array_fst_sc.out index 51dbb33a9..f304e1cff 100644 --- a/test_regress/t/t_trace_array_fst_sc.out +++ b/test_regress/t/t_trace_array_fst_sc.out @@ -1,5 +1,5 @@ $date - Thu Apr 1 15:02:16 2021 + Wed Feb 23 00:00:45 2022 $end $version @@ -11,9 +11,9 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end +$var integer 32 " cyc [31:0] $end $scope struct biggie $end -$var logic 1048577 # d $end +$var logic 1048577 # d [1048576:0] $end $upscope $end $upscope $end $upscope $end diff --git a/test_regress/t/t_trace_cat_fst_0000.out b/test_regress/t/t_trace_cat_fst_0000.out index 9797307a3..bff2d2b8b 100644 --- a/test_regress/t/t_trace_cat_fst_0000.out +++ b/test_regress/t/t_trace_cat_fst_0000.out @@ -1,5 +1,5 @@ $date - Wed Apr 14 17:11:07 2021 + Wed Feb 23 00:00:47 2022 $end $version @@ -12,8 +12,8 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var integer 32 # unchanged $end +$var integer 32 " cyc [31:0] $end +$var integer 32 # unchanged [31:0] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_cat_fst_0100.out b/test_regress/t/t_trace_cat_fst_0100.out index fb24bf654..911261625 100644 --- a/test_regress/t/t_trace_cat_fst_0100.out +++ b/test_regress/t/t_trace_cat_fst_0100.out @@ -1,5 +1,5 @@ $date - Wed Apr 14 17:04:26 2021 + Wed Feb 23 00:26:16 2022 $end $version @@ -12,8 +12,8 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var integer 32 # unchanged $end +$var integer 32 " cyc [31:0] $end +$var integer 32 # unchanged [31:0] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index 9572e92dc..313440c33 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -92,9 +92,9 @@ module t (clk); v_string <= cyc[0] ? "foo" : "bar"; v_arr_real[0] <= v_arr_real[0] + 0.2; v_arr_real[1] <= v_arr_real[1] + 0.3; - v_enumed <= v_enumed + 1; - v_enumed2 <= v_enumed2 + 2; - v_enumb <= v_enumb - 1; + v_enumed <= enumed_t'(v_enumed + 1); + v_enumed2 <= enumed_t'(v_enumed2 + 2); + v_enumb <= enumb_t'(v_enumb - 3'd1); v_enumb2_str <= {v_enumb, v_enumb}; for (integer b=3; b<=4; b++) begin v_arru[b] <= ~v_arru[b]; diff --git a/test_regress/t/t_trace_complex_fst.out b/test_regress/t/t_trace_complex_fst.out index 3fbfab803..b5109253a 100644 --- a/test_regress/t/t_trace_complex_fst.out +++ b/test_regress/t/t_trace_complex_fst.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 12:40:48 2021 + Wed Feb 23 00:01:04 2022 $end $version @@ -12,54 +12,54 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var logic 2 # v_strp $end -$var logic 4 $ v_strp_strp $end -$var logic 2 % v_unip_strp $end -$var logic 2 & v_arrp $end -$var logic 4 ' v_arrp_arrp $end -$var logic 4 ( v_arrp_strp $end +$var integer 32 " cyc [31:0] $end +$var logic 2 # v_strp [1:0] $end +$var logic 4 $ v_strp_strp [3:0] $end +$var logic 2 % v_unip_strp [1:0] $end +$var logic 2 & v_arrp [2:1] $end +$var logic 4 ' v_arrp_arrp [3:0] $end +$var logic 4 ( v_arrp_strp [3:0] $end $var logic 1 ) v_arru[1] $end $var logic 1 * v_arru[2] $end $var logic 1 + v_arru_arru[3][1] $end $var logic 1 , v_arru_arru[3][2] $end $var logic 1 - v_arru_arru[4][1] $end $var logic 1 . v_arru_arru[4][2] $end -$var logic 2 / v_arru_arrp[3] $end -$var logic 2 0 v_arru_arrp[4] $end -$var logic 2 1 v_arru_strp[3] $end -$var logic 2 2 v_arru_strp[4] $end +$var logic 2 / v_arru_arrp[3] [2:1] $end +$var logic 2 0 v_arru_arrp[4] [2:1] $end +$var logic 2 1 v_arru_strp[3] [1:0] $end +$var logic 2 2 v_arru_strp[4] [1:0] $end $var real 64 3 v_real $end $var real 64 4 v_arr_real[0] $end $var real 64 5 v_arr_real[1] $end -$var logic 64 6 v_str32x2 $end +$var logic 64 6 v_str32x2 [63:0] $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end -$var logic 32 7 v_enumed $end +$var logic 32 7 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end -$var logic 32 8 v_enumed2 $end +$var logic 32 8 v_enumed2 [31:0] $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end -$var logic 3 9 v_enumb $end -$var logic 6 : v_enumb2_str $end -$var logic 8 ; unpacked_array[-2] $end -$var logic 8 < unpacked_array[-1] $end -$var logic 8 = unpacked_array[0] $end +$var logic 3 9 v_enumb [2:0] $end +$var logic 6 : v_enumb2_str [5:0] $end +$var logic 8 ; unpacked_array[-2] [7:0] $end +$var logic 8 < unpacked_array[-1] [7:0] $end +$var logic 8 = unpacked_array[0] [7:0] $end $var bit 1 > LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end -$scope module unnamedblk1 $end -$var integer 32 ? b $end -$scope module unnamedblk2 $end -$var integer 32 @ a $end -$upscope $end +$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end +$var parameter 32 ? PARAM [31:0] $end $upscope $end $scope module p2 $end -$var parameter 32 A PARAM $end +$var parameter 32 @ PARAM [31:0] $end $upscope $end $scope module p3 $end -$var parameter 32 B PARAM $end +$var parameter 32 A PARAM [31:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var integer 32 B b [31:0] $end +$scope module unnamedblk2 $end +$var integer 32 C a [31:0] $end $upscope $end -$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end -$var parameter 32 C PARAM $end $upscope $end $upscope $end $scope module $unit $end @@ -70,11 +70,11 @@ $enddefinitions $end #0 $dumpvars 1D -b00000000000000000000000000000100 C -b00000000000000000000000000000011 B -b00000000000000000000000000000010 A -b00000000000000000000000000000000 @ -b00000000000000000000000000000000 ? +b00000000000000000000000000000000 C +b00000000000000000000000000000000 B +b00000000000000000000000000000011 A +b00000000000000000000000000000010 @ +b00000000000000000000000000000100 ? 0> b00000000 = b00000000 < @@ -126,8 +126,8 @@ b0000000000000000000000000000000100000000000000000000000011111110 6 b00000000000000000000000000000001 7 b00000000000000000000000000000010 8 b111 9 -b00000000000000000000000000000101 ? -b00000000000000000000000000000101 @ +b00000000000000000000000000000101 B +b00000000000000000000000000000101 C #15 0! #20 diff --git a/test_regress/t/t_trace_complex_fst_sc.out b/test_regress/t/t_trace_complex_fst_sc.out index f56182246..c77a06772 100644 --- a/test_regress/t/t_trace_complex_fst_sc.out +++ b/test_regress/t/t_trace_complex_fst_sc.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 12:40:52 2021 + Wed Feb 23 00:01:09 2022 $end $version @@ -11,54 +11,54 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var logic 2 # v_strp $end -$var logic 4 $ v_strp_strp $end -$var logic 2 % v_unip_strp $end -$var logic 2 & v_arrp $end -$var logic 4 ' v_arrp_arrp $end -$var logic 4 ( v_arrp_strp $end +$var integer 32 " cyc [31:0] $end +$var logic 2 # v_strp [1:0] $end +$var logic 4 $ v_strp_strp [3:0] $end +$var logic 2 % v_unip_strp [1:0] $end +$var logic 2 & v_arrp [2:1] $end +$var logic 4 ' v_arrp_arrp [3:0] $end +$var logic 4 ( v_arrp_strp [3:0] $end $var logic 1 ) v_arru[1] $end $var logic 1 * v_arru[2] $end $var logic 1 + v_arru_arru[3][1] $end $var logic 1 , v_arru_arru[3][2] $end $var logic 1 - v_arru_arru[4][1] $end $var logic 1 . v_arru_arru[4][2] $end -$var logic 2 / v_arru_arrp[3] $end -$var logic 2 0 v_arru_arrp[4] $end -$var logic 2 1 v_arru_strp[3] $end -$var logic 2 2 v_arru_strp[4] $end +$var logic 2 / v_arru_arrp[3] [2:1] $end +$var logic 2 0 v_arru_arrp[4] [2:1] $end +$var logic 2 1 v_arru_strp[3] [1:0] $end +$var logic 2 2 v_arru_strp[4] [1:0] $end $var real 64 3 v_real $end $var real 64 4 v_arr_real[0] $end $var real 64 5 v_arr_real[1] $end -$var logic 64 6 v_str32x2 $end +$var logic 64 6 v_str32x2 [63:0] $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end -$var logic 32 7 v_enumed $end +$var logic 32 7 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end -$var logic 32 8 v_enumed2 $end +$var logic 32 8 v_enumed2 [31:0] $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end -$var logic 3 9 v_enumb $end -$var logic 6 : v_enumb2_str $end -$var logic 8 ; unpacked_array[-2] $end -$var logic 8 < unpacked_array[-1] $end -$var logic 8 = unpacked_array[0] $end +$var logic 3 9 v_enumb [2:0] $end +$var logic 6 : v_enumb2_str [5:0] $end +$var logic 8 ; unpacked_array[-2] [7:0] $end +$var logic 8 < unpacked_array[-1] [7:0] $end +$var logic 8 = unpacked_array[0] [7:0] $end $var bit 1 > LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end -$scope module unnamedblk1 $end -$var integer 32 ? b $end -$scope module unnamedblk2 $end -$var integer 32 @ a $end -$upscope $end +$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end +$var parameter 32 ? PARAM [31:0] $end $upscope $end $scope module p2 $end -$var parameter 32 A PARAM $end +$var parameter 32 @ PARAM [31:0] $end $upscope $end $scope module p3 $end -$var parameter 32 B PARAM $end +$var parameter 32 A PARAM [31:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var integer 32 B b [31:0] $end +$scope module unnamedblk2 $end +$var integer 32 C a [31:0] $end $upscope $end -$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end -$var parameter 32 C PARAM $end $upscope $end $upscope $end $scope module $unit $end @@ -69,11 +69,11 @@ $enddefinitions $end #0 $dumpvars 1D -b00000000000000000000000000000100 C -b00000000000000000000000000000011 B -b00000000000000000000000000000010 A -b00000000000000000000000000000000 @ -b00000000000000000000000000000000 ? +b00000000000000000000000000000000 C +b00000000000000000000000000000000 B +b00000000000000000000000000000011 A +b00000000000000000000000000000010 @ +b00000000000000000000000000000100 ? 0> b00000000 = b00000000 < @@ -125,8 +125,8 @@ b0000000000000000000000000000000100000000000000000000000011111110 6 b00000000000000000000000000000001 7 b00000000000000000000000000000010 8 b111 9 -b00000000000000000000000000000101 ? -b00000000000000000000000000000101 @ +b00000000000000000000000000000101 B +b00000000000000000000000000000101 C #11 #12 #13 diff --git a/test_regress/t/t_trace_complex_params_fst.out b/test_regress/t/t_trace_complex_params_fst.out index 1825f3bd9..24ad40d1b 100644 --- a/test_regress/t/t_trace_complex_params_fst.out +++ b/test_regress/t/t_trace_complex_params_fst.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 12:41:14 2021 + Wed Feb 23 00:01:11 2022 $end $version @@ -12,54 +12,54 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var logic 2 # v_strp $end -$var logic 4 $ v_strp_strp $end -$var logic 2 % v_unip_strp $end -$var logic 2 & v_arrp $end -$var logic 4 ' v_arrp_arrp $end -$var logic 4 ( v_arrp_strp $end +$var integer 32 " cyc [31:0] $end +$var logic 2 # v_strp [1:0] $end +$var logic 4 $ v_strp_strp [3:0] $end +$var logic 2 % v_unip_strp [1:0] $end +$var logic 2 & v_arrp [2:1] $end +$var logic 4 ' v_arrp_arrp [3:0] $end +$var logic 4 ( v_arrp_strp [3:0] $end $var logic 1 ) v_arru[1] $end $var logic 1 * v_arru[2] $end $var logic 1 + v_arru_arru[3][1] $end $var logic 1 , v_arru_arru[3][2] $end $var logic 1 - v_arru_arru[4][1] $end $var logic 1 . v_arru_arru[4][2] $end -$var logic 2 / v_arru_arrp[3] $end -$var logic 2 0 v_arru_arrp[4] $end -$var logic 2 1 v_arru_strp[3] $end -$var logic 2 2 v_arru_strp[4] $end +$var logic 2 / v_arru_arrp[3] [2:1] $end +$var logic 2 0 v_arru_arrp[4] [2:1] $end +$var logic 2 1 v_arru_strp[3] [1:0] $end +$var logic 2 2 v_arru_strp[4] [1:0] $end $var real 64 3 v_real $end $var real 64 4 v_arr_real[0] $end $var real 64 5 v_arr_real[1] $end -$var logic 64 6 v_str32x2 $end +$var logic 64 6 v_str32x2 [63:0] $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end -$var logic 32 7 v_enumed $end +$var logic 32 7 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end -$var logic 32 8 v_enumed2 $end +$var logic 32 8 v_enumed2 [31:0] $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end -$var logic 3 9 v_enumb $end -$var logic 6 : v_enumb2_str $end -$var logic 8 ; unpacked_array[-2] $end -$var logic 8 < unpacked_array[-1] $end -$var logic 8 = unpacked_array[0] $end +$var logic 3 9 v_enumb [2:0] $end +$var logic 6 : v_enumb2_str [5:0] $end +$var logic 8 ; unpacked_array[-2] [7:0] $end +$var logic 8 < unpacked_array[-1] [7:0] $end +$var logic 8 = unpacked_array[0] [7:0] $end $var bit 1 > LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end -$scope module unnamedblk1 $end -$var integer 32 ? b $end -$scope module unnamedblk2 $end -$var integer 32 @ a $end -$upscope $end +$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end +$var parameter 32 ? PARAM [31:0] $end $upscope $end $scope module p2 $end -$var parameter 32 A PARAM $end +$var parameter 32 @ PARAM [31:0] $end $upscope $end $scope module p3 $end -$var parameter 32 B PARAM $end +$var parameter 32 A PARAM [31:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var integer 32 B b [31:0] $end +$scope module unnamedblk2 $end +$var integer 32 C a [31:0] $end $upscope $end -$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end -$var parameter 32 C PARAM $end $upscope $end $upscope $end $scope module $unit $end @@ -70,11 +70,11 @@ $enddefinitions $end #0 $dumpvars 1D -b00000000000000000000000000000100 C -b00000000000000000000000000000011 B -b00000000000000000000000000000010 A -b00000000000000000000000000000000 @ -b00000000000000000000000000000000 ? +b00000000000000000000000000000000 C +b00000000000000000000000000000000 B +b00000000000000000000000000000011 A +b00000000000000000000000000000010 @ +b00000000000000000000000000000100 ? 0> b00000000 = b00000000 < @@ -126,8 +126,8 @@ b0000000000000000000000000000000100000000000000000000000011111110 6 b00000000000000000000000000000001 7 b00000000000000000000000000000010 8 b111 9 -b00000000000000000000000000000101 ? -b00000000000000000000000000000101 @ +b00000000000000000000000000000101 B +b00000000000000000000000000000101 C #15 0! #20 diff --git a/test_regress/t/t_trace_complex_params_fst_sc.out b/test_regress/t/t_trace_complex_params_fst_sc.out index fd56fca23..43f3c9ed6 100644 --- a/test_regress/t/t_trace_complex_params_fst_sc.out +++ b/test_regress/t/t_trace_complex_params_fst_sc.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 12:41:17 2021 + Wed Feb 23 00:01:18 2022 $end $version @@ -11,54 +11,54 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var logic 2 # v_strp $end -$var logic 4 $ v_strp_strp $end -$var logic 2 % v_unip_strp $end -$var logic 2 & v_arrp $end -$var logic 4 ' v_arrp_arrp $end -$var logic 4 ( v_arrp_strp $end +$var integer 32 " cyc [31:0] $end +$var logic 2 # v_strp [1:0] $end +$var logic 4 $ v_strp_strp [3:0] $end +$var logic 2 % v_unip_strp [1:0] $end +$var logic 2 & v_arrp [2:1] $end +$var logic 4 ' v_arrp_arrp [3:0] $end +$var logic 4 ( v_arrp_strp [3:0] $end $var logic 1 ) v_arru[1] $end $var logic 1 * v_arru[2] $end $var logic 1 + v_arru_arru[3][1] $end $var logic 1 , v_arru_arru[3][2] $end $var logic 1 - v_arru_arru[4][1] $end $var logic 1 . v_arru_arru[4][2] $end -$var logic 2 / v_arru_arrp[3] $end -$var logic 2 0 v_arru_arrp[4] $end -$var logic 2 1 v_arru_strp[3] $end -$var logic 2 2 v_arru_strp[4] $end +$var logic 2 / v_arru_arrp[3] [2:1] $end +$var logic 2 0 v_arru_arrp[4] [2:1] $end +$var logic 2 1 v_arru_strp[3] [1:0] $end +$var logic 2 2 v_arru_strp[4] [1:0] $end $var real 64 3 v_real $end $var real 64 4 v_arr_real[0] $end $var real 64 5 v_arr_real[1] $end -$var logic 64 6 v_str32x2 $end +$var logic 64 6 v_str32x2 [63:0] $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end -$var logic 32 7 v_enumed $end +$var logic 32 7 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end -$var logic 32 8 v_enumed2 $end +$var logic 32 8 v_enumed2 [31:0] $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end -$var logic 3 9 v_enumb $end -$var logic 6 : v_enumb2_str $end -$var logic 8 ; unpacked_array[-2] $end -$var logic 8 < unpacked_array[-1] $end -$var logic 8 = unpacked_array[0] $end +$var logic 3 9 v_enumb [2:0] $end +$var logic 6 : v_enumb2_str [5:0] $end +$var logic 8 ; unpacked_array[-2] [7:0] $end +$var logic 8 < unpacked_array[-1] [7:0] $end +$var logic 8 = unpacked_array[0] [7:0] $end $var bit 1 > LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end -$scope module unnamedblk1 $end -$var integer 32 ? b $end -$scope module unnamedblk2 $end -$var integer 32 @ a $end -$upscope $end +$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end +$var parameter 32 ? PARAM [31:0] $end $upscope $end $scope module p2 $end -$var parameter 32 A PARAM $end +$var parameter 32 @ PARAM [31:0] $end $upscope $end $scope module p3 $end -$var parameter 32 B PARAM $end +$var parameter 32 A PARAM [31:0] $end +$upscope $end +$scope module unnamedblk1 $end +$var integer 32 B b [31:0] $end +$scope module unnamedblk2 $end +$var integer 32 C a [31:0] $end $upscope $end -$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end -$var parameter 32 C PARAM $end $upscope $end $upscope $end $scope module $unit $end @@ -69,11 +69,11 @@ $enddefinitions $end #0 $dumpvars 1D -b00000000000000000000000000000100 C -b00000000000000000000000000000011 B -b00000000000000000000000000000010 A -b00000000000000000000000000000000 @ -b00000000000000000000000000000000 ? +b00000000000000000000000000000000 C +b00000000000000000000000000000000 B +b00000000000000000000000000000011 A +b00000000000000000000000000000010 @ +b00000000000000000000000000000100 ? 0> b00000000 = b00000000 < @@ -125,8 +125,8 @@ b0000000000000000000000000000000100000000000000000000000011111110 6 b00000000000000000000000000000001 7 b00000000000000000000000000000010 8 b111 9 -b00000000000000000000000000000101 ? -b00000000000000000000000000000101 @ +b00000000000000000000000000000101 B +b00000000000000000000000000000101 C #11 #12 #13 diff --git a/test_regress/t/t_trace_complex_structs_fst.out b/test_regress/t/t_trace_complex_structs_fst.out index 8ba8df6f3..c827fdd9b 100644 --- a/test_regress/t/t_trace_complex_structs_fst.out +++ b/test_regress/t/t_trace_complex_structs_fst.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 12:41:25 2021 + Wed Feb 23 00:01:19 2022 $end $version @@ -12,7 +12,7 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end +$var integer 32 " cyc [31:0] $end $scope struct v_strp $end $var logic 1 # b1 $end $var logic 1 $ b0 $end @@ -37,9 +37,9 @@ $var logic 1 ) b1 $end $var logic 1 * b0 $end $upscope $end $upscope $end -$var logic 2 + v_arrp $end -$var logic 2 , v_arrp_arrp[3] $end -$var logic 2 - v_arrp_arrp[4] $end +$var logic 2 + v_arrp [2:1] $end +$var logic 2 , v_arrp_arrp[3] [2:1] $end +$var logic 2 - v_arrp_arrp[4] [2:1] $end $scope struct v_arrp_strp[3] $end $var logic 1 . b1 $end $var logic 1 / b0 $end @@ -54,8 +54,8 @@ $var logic 1 4 v_arru_arru[3][1] $end $var logic 1 5 v_arru_arru[3][2] $end $var logic 1 6 v_arru_arru[4][1] $end $var logic 1 7 v_arru_arru[4][2] $end -$var logic 2 8 v_arru_arrp[3] $end -$var logic 2 9 v_arru_arrp[4] $end +$var logic 2 8 v_arru_arrp[3] [2:1] $end +$var logic 2 9 v_arru_arrp[4] [2:1] $end $scope struct v_arru_strp[3] $end $var logic 1 : b1 $end $var logic 1 ; b0 $end @@ -68,33 +68,33 @@ $var real 64 > v_real $end $var real 64 ? v_arr_real[0] $end $var real 64 @ v_arr_real[1] $end $scope struct v_str32x2[0] $end -$var logic 32 A data $end +$var logic 32 A data [31:0] $end $upscope $end $scope struct v_str32x2[1] $end -$var logic 32 B data $end +$var logic 32 B data [31:0] $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $upscope $end $attrbegin misc 07 "" 1 $end -$var logic 32 C v_enumed $end +$var logic 32 C v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end -$var logic 32 D v_enumed2 $end +$var logic 32 D v_enumed2 [31:0] $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end -$var logic 3 E v_enumb $end +$var logic 3 E v_enumb [2:0] $end $scope struct v_enumb2_str $end $attrbegin misc 07 "" 2 $end -$var logic 3 F a $end +$var logic 3 F a [2:0] $end $attrbegin misc 07 "" 2 $end -$var logic 3 G b $end +$var logic 3 G b [2:0] $end $upscope $end -$var logic 8 H unpacked_array[-2] $end -$var logic 8 I unpacked_array[-1] $end -$var logic 8 J unpacked_array[0] $end +$var logic 8 H unpacked_array[-2] [7:0] $end +$var logic 8 I unpacked_array[-1] [7:0] $end +$var logic 8 J unpacked_array[0] [7:0] $end $var bit 1 K LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module unnamedblk1 $end -$var integer 32 L b $end +$var integer 32 L b [31:0] $end $scope module unnamedblk2 $end -$var integer 32 M a $end +$var integer 32 M a [31:0] $end $upscope $end $upscope $end $upscope $end diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.out b/test_regress/t/t_trace_complex_structs_fst_sc.out index 515dd4625..81696e302 100644 --- a/test_regress/t/t_trace_complex_structs_fst_sc.out +++ b/test_regress/t/t_trace_complex_structs_fst_sc.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 12:41:29 2021 + Wed Feb 23 00:01:26 2022 $end $version @@ -11,7 +11,7 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end +$var integer 32 " cyc [31:0] $end $scope struct v_strp $end $var logic 1 # b1 $end $var logic 1 $ b0 $end @@ -36,9 +36,9 @@ $var logic 1 ) b1 $end $var logic 1 * b0 $end $upscope $end $upscope $end -$var logic 2 + v_arrp $end -$var logic 2 , v_arrp_arrp[3] $end -$var logic 2 - v_arrp_arrp[4] $end +$var logic 2 + v_arrp [2:1] $end +$var logic 2 , v_arrp_arrp[3] [2:1] $end +$var logic 2 - v_arrp_arrp[4] [2:1] $end $scope struct v_arrp_strp[3] $end $var logic 1 . b1 $end $var logic 1 / b0 $end @@ -53,8 +53,8 @@ $var logic 1 4 v_arru_arru[3][1] $end $var logic 1 5 v_arru_arru[3][2] $end $var logic 1 6 v_arru_arru[4][1] $end $var logic 1 7 v_arru_arru[4][2] $end -$var logic 2 8 v_arru_arrp[3] $end -$var logic 2 9 v_arru_arrp[4] $end +$var logic 2 8 v_arru_arrp[3] [2:1] $end +$var logic 2 9 v_arru_arrp[4] [2:1] $end $scope struct v_arru_strp[3] $end $var logic 1 : b1 $end $var logic 1 ; b0 $end @@ -67,33 +67,33 @@ $var real 64 > v_real $end $var real 64 ? v_arr_real[0] $end $var real 64 @ v_arr_real[1] $end $scope struct v_str32x2[0] $end -$var logic 32 A data $end +$var logic 32 A data [31:0] $end $upscope $end $scope struct v_str32x2[1] $end -$var logic 32 B data $end +$var logic 32 B data [31:0] $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $upscope $end $attrbegin misc 07 "" 1 $end -$var logic 32 C v_enumed $end +$var logic 32 C v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end -$var logic 32 D v_enumed2 $end +$var logic 32 D v_enumed2 [31:0] $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end -$var logic 3 E v_enumb $end +$var logic 3 E v_enumb [2:0] $end $scope struct v_enumb2_str $end $attrbegin misc 07 "" 2 $end -$var logic 3 F a $end +$var logic 3 F a [2:0] $end $attrbegin misc 07 "" 2 $end -$var logic 3 G b $end +$var logic 3 G b [2:0] $end $upscope $end -$var logic 8 H unpacked_array[-2] $end -$var logic 8 I unpacked_array[-1] $end -$var logic 8 J unpacked_array[0] $end +$var logic 8 H unpacked_array[-2] [7:0] $end +$var logic 8 I unpacked_array[-1] [7:0] $end +$var logic 8 J unpacked_array[0] [7:0] $end $var bit 1 K LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module unnamedblk1 $end -$var integer 32 L b $end +$var integer 32 L b [31:0] $end $scope module unnamedblk2 $end -$var integer 32 M a $end +$var integer 32 M a [31:0] $end $upscope $end $upscope $end $upscope $end diff --git a/test_regress/t/t_trace_dumpvars_dyn.cpp b/test_regress/t/t_trace_dumpvars_dyn.cpp new file mode 100644 index 000000000..f5d5f986e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn.cpp @@ -0,0 +1,62 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include +#include +#include +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +const unsigned long long dt_2 = 3; + +int main(int argc, char** argv, char** env) { + std::unique_ptr top{new VM_PREFIX("top")}; + + Verilated::debug(0); + Verilated::traceEverOn(true); + +#if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_VCD_1) + std::unique_ptr tfp{new VerilatedVcdC}; +#elif defined(T_TRACE_DUMPVARS_DYN_FST_0) || defined(T_TRACE_DUMPVARS_DYN_FST_1) + std::unique_ptr tfp{new VerilatedFstC}; +#else +#error "Bad test" +#endif + +#if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0) + tfp->dumpvars(0, ""); +#elif defined(T_TRACE_DUMPVARS_DYN_VCD_1) || defined(T_TRACE_DUMPVARS_DYN_FST_1) + tfp->dumpvars(99, "t"); // This should not match "top." + tfp->dumpvars(1, "top.t.cyc"); // A signal + tfp->dumpvars(1, "top.t.sub1a"); // Scope + tfp->dumpvars(2, "top.t.sub1b"); // Scope +#else +#error "Bad test" +#endif + + top->trace(tfp.get(), 99); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); + top->clk = 0; + + while (main_time <= 20) { + top->eval(); + tfp->dump((unsigned int)(main_time)); + ++main_time; + top->clk = !top->clk; + } + tfp->close(); + top->final(); + tfp.reset(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_dyn.v b/test_regress/t/t_trace_dumpvars_dyn.v new file mode 100644 index 000000000..dfeaa16dd --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + int cyc; + + sub1 #(10) sub1a (.*); + sub1 #(20) sub1b (.*); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub1 #(parameter int ADD) + (input int cyc); + + wire int value = cyc + ADD; + + sub2 #(ADD + 1) sub2a(.*); + sub2 #(ADD + 2) sub2b(.*); + sub2 #(ADD + 3) sub2c(.*); +endmodule + +module sub2 #(parameter int ADD) + (input int cyc); + + wire int value = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.out b/test_regress/t/t_trace_dumpvars_dyn_fst_0.out new file mode 100644 index 000000000..e3d5eaaf3 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_0.out @@ -0,0 +1,209 @@ +$date + Sat Mar 5 14:06:13 2022 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$var int 32 " cyc [31:0] $end +$scope module sub1a $end +$var parameter 32 # ADD [31:0] $end +$var wire 32 " cyc [31:0] $end +$var wire 32 $ value [31:0] $end +$scope module sub2a $end +$var parameter 32 % ADD [31:0] $end +$var wire 32 " cyc [31:0] $end +$var wire 32 & value [31:0] $end +$upscope $end +$scope module sub2b $end +$var parameter 32 ' ADD [31:0] $end +$var wire 32 " cyc [31:0] $end +$var wire 32 ( value [31:0] $end +$upscope $end +$scope module sub2c $end +$var parameter 32 ) ADD [31:0] $end +$var wire 32 " cyc [31:0] $end +$var wire 32 * value [31:0] $end +$upscope $end +$upscope $end +$scope module sub1b $end +$var parameter 32 + ADD [31:0] $end +$var wire 32 " cyc [31:0] $end +$var wire 32 , value [31:0] $end +$scope module sub2a $end +$var parameter 32 - ADD [31:0] $end +$var wire 32 " cyc [31:0] $end +$var wire 32 . value [31:0] $end +$upscope $end +$scope module sub2b $end +$var parameter 32 / ADD [31:0] $end +$var wire 32 " cyc [31:0] $end +$var wire 32 0 value [31:0] $end +$upscope $end +$scope module sub2c $end +$var parameter 32 1 ADD [31:0] $end +$var wire 32 " cyc [31:0] $end +$var wire 32 2 value [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000000000010111 2 +b00000000000000000000000000010111 1 +b00000000000000000000000000010110 0 +b00000000000000000000000000010110 / +b00000000000000000000000000010101 . +b00000000000000000000000000010101 - +b00000000000000000000000000010100 , +b00000000000000000000000000010100 + +b00000000000000000000000000001101 * +b00000000000000000000000000001101 ) +b00000000000000000000000000001100 ( +b00000000000000000000000000001100 ' +b00000000000000000000000000001011 & +b00000000000000000000000000001011 % +b00000000000000000000000000001010 $ +b00000000000000000000000000001010 # +b00000000000000000000000000000000 " +0! +$end +#1 +1! +b00000000000000000000000000000001 " +b00000000000000000000000000001011 $ +b00000000000000000000000000001100 & +b00000000000000000000000000001101 ( +b00000000000000000000000000001110 * +b00000000000000000000000000010101 , +b00000000000000000000000000010110 . +b00000000000000000000000000010111 0 +b00000000000000000000000000011000 2 +#2 +0! +#3 +1! +b00000000000000000000000000011001 2 +b00000000000000000000000000011000 0 +b00000000000000000000000000010111 . +b00000000000000000000000000010110 , +b00000000000000000000000000001111 * +b00000000000000000000000000001110 ( +b00000000000000000000000000001101 & +b00000000000000000000000000001100 $ +b00000000000000000000000000000010 " +#4 +0! +#5 +1! +b00000000000000000000000000000011 " +b00000000000000000000000000001101 $ +b00000000000000000000000000001110 & +b00000000000000000000000000001111 ( +b00000000000000000000000000010000 * +b00000000000000000000000000010111 , +b00000000000000000000000000011000 . +b00000000000000000000000000011001 0 +b00000000000000000000000000011010 2 +#6 +0! +#7 +1! +b00000000000000000000000000011011 2 +b00000000000000000000000000011010 0 +b00000000000000000000000000011001 . +b00000000000000000000000000011000 , +b00000000000000000000000000010001 * +b00000000000000000000000000010000 ( +b00000000000000000000000000001111 & +b00000000000000000000000000001110 $ +b00000000000000000000000000000100 " +#8 +0! +#9 +1! +b00000000000000000000000000000101 " +b00000000000000000000000000001111 $ +b00000000000000000000000000010000 & +b00000000000000000000000000010001 ( +b00000000000000000000000000010010 * +b00000000000000000000000000011001 , +b00000000000000000000000000011010 . +b00000000000000000000000000011011 0 +b00000000000000000000000000011100 2 +#10 +0! +#11 +1! +b00000000000000000000000000011101 2 +b00000000000000000000000000011100 0 +b00000000000000000000000000011011 . +b00000000000000000000000000011010 , +b00000000000000000000000000010011 * +b00000000000000000000000000010010 ( +b00000000000000000000000000010001 & +b00000000000000000000000000010000 $ +b00000000000000000000000000000110 " +#12 +0! +#13 +1! +b00000000000000000000000000000111 " +b00000000000000000000000000010001 $ +b00000000000000000000000000010010 & +b00000000000000000000000000010011 ( +b00000000000000000000000000010100 * +b00000000000000000000000000011011 , +b00000000000000000000000000011100 . +b00000000000000000000000000011101 0 +b00000000000000000000000000011110 2 +#14 +0! +#15 +1! +b00000000000000000000000000011111 2 +b00000000000000000000000000011110 0 +b00000000000000000000000000011101 . +b00000000000000000000000000011100 , +b00000000000000000000000000010101 * +b00000000000000000000000000010100 ( +b00000000000000000000000000010011 & +b00000000000000000000000000010010 $ +b00000000000000000000000000001000 " +#16 +0! +#17 +1! +b00000000000000000000000000001001 " +b00000000000000000000000000010011 $ +b00000000000000000000000000010100 & +b00000000000000000000000000010101 ( +b00000000000000000000000000010110 * +b00000000000000000000000000011101 , +b00000000000000000000000000011110 . +b00000000000000000000000000011111 0 +b00000000000000000000000000100000 2 +#18 +0! +#19 +1! +b00000000000000000000000000100001 2 +b00000000000000000000000000100000 0 +b00000000000000000000000000011111 . +b00000000000000000000000000011110 , +b00000000000000000000000000010111 * +b00000000000000000000000000010110 ( +b00000000000000000000000000010101 & +b00000000000000000000000000010100 $ +b00000000000000000000000000001010 " +#20 +0! diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl b/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl new file mode 100755 index 000000000..2e62f1f44 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl @@ -0,0 +1,27 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); + +top_filename("t_trace_dumpvars_dyn.v"); + +compile( + make_main => 0, + verilator_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], + ); + +execute( + check_finished => 1, + ); + +fst_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.out b/test_regress/t/t_trace_dumpvars_dyn_fst_1.out new file mode 100644 index 000000000..1a5eae60b --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_1.out @@ -0,0 +1,135 @@ +$date + Sat Mar 5 14:05:37 2022 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var int 32 ! cyc [31:0] $end +$scope module sub1a $end +$var parameter 32 " ADD [31:0] $end +$var wire 32 ! cyc [31:0] $end +$var wire 32 # value [31:0] $end +$upscope $end +$scope module sub1b $end +$var parameter 32 $ ADD [31:0] $end +$var wire 32 ! cyc [31:0] $end +$var wire 32 % value [31:0] $end +$scope module sub2a $end +$var parameter 32 & ADD [31:0] $end +$var wire 32 ! cyc [31:0] $end +$var wire 32 ' value [31:0] $end +$upscope $end +$scope module sub2b $end +$var parameter 32 ( ADD [31:0] $end +$var wire 32 ! cyc [31:0] $end +$var wire 32 ) value [31:0] $end +$upscope $end +$scope module sub2c $end +$var parameter 32 * ADD [31:0] $end +$var wire 32 ! cyc [31:0] $end +$var wire 32 + value [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000000000010111 + +b00000000000000000000000000010111 * +b00000000000000000000000000010110 ) +b00000000000000000000000000010110 ( +b00000000000000000000000000010101 ' +b00000000000000000000000000010101 & +b00000000000000000000000000010100 % +b00000000000000000000000000010100 $ +b00000000000000000000000000001010 # +b00000000000000000000000000001010 " +b00000000000000000000000000000000 ! +$end +#1 +b00000000000000000000000000000001 ! +b00000000000000000000000000001011 # +b00000000000000000000000000010101 % +b00000000000000000000000000010110 ' +b00000000000000000000000000010111 ) +b00000000000000000000000000011000 + +#2 +#3 +b00000000000000000000000000011001 + +b00000000000000000000000000011000 ) +b00000000000000000000000000010111 ' +b00000000000000000000000000010110 % +b00000000000000000000000000001100 # +b00000000000000000000000000000010 ! +#4 +#5 +b00000000000000000000000000000011 ! +b00000000000000000000000000001101 # +b00000000000000000000000000010111 % +b00000000000000000000000000011000 ' +b00000000000000000000000000011001 ) +b00000000000000000000000000011010 + +#6 +#7 +b00000000000000000000000000011011 + +b00000000000000000000000000011010 ) +b00000000000000000000000000011001 ' +b00000000000000000000000000011000 % +b00000000000000000000000000001110 # +b00000000000000000000000000000100 ! +#8 +#9 +b00000000000000000000000000000101 ! +b00000000000000000000000000001111 # +b00000000000000000000000000011001 % +b00000000000000000000000000011010 ' +b00000000000000000000000000011011 ) +b00000000000000000000000000011100 + +#10 +#11 +b00000000000000000000000000011101 + +b00000000000000000000000000011100 ) +b00000000000000000000000000011011 ' +b00000000000000000000000000011010 % +b00000000000000000000000000010000 # +b00000000000000000000000000000110 ! +#12 +#13 +b00000000000000000000000000000111 ! +b00000000000000000000000000010001 # +b00000000000000000000000000011011 % +b00000000000000000000000000011100 ' +b00000000000000000000000000011101 ) +b00000000000000000000000000011110 + +#14 +#15 +b00000000000000000000000000011111 + +b00000000000000000000000000011110 ) +b00000000000000000000000000011101 ' +b00000000000000000000000000011100 % +b00000000000000000000000000010010 # +b00000000000000000000000000001000 ! +#16 +#17 +b00000000000000000000000000001001 ! +b00000000000000000000000000010011 # +b00000000000000000000000000011101 % +b00000000000000000000000000011110 ' +b00000000000000000000000000011111 ) +b00000000000000000000000000100000 + +#18 +#19 +b00000000000000000000000000100001 + +b00000000000000000000000000100000 ) +b00000000000000000000000000011111 ' +b00000000000000000000000000011110 % +b00000000000000000000000000010100 # +b00000000000000000000000000001010 ! +#20 diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl b/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl new file mode 100755 index 000000000..2e62f1f44 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl @@ -0,0 +1,27 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); + +top_filename("t_trace_dumpvars_dyn.v"); + +compile( + make_main => 0, + verilator_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], + ); + +execute( + check_finished => 1, + ); + +fst_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.out b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.out new file mode 100644 index 000000000..c19393619 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.out @@ -0,0 +1,203 @@ +$version Generated by VerilatedVcd $end +$date Sat Mar 5 13:48:47 2022 $end +$timescale 1ps $end + + $scope module top $end + $var wire 1 , clk $end + $scope module t $end + $var wire 1 , clk $end + $var wire 32 # cyc [31:0] $end + $scope module sub1a $end + $var wire 32 - ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ value [31:0] $end + $scope module sub2a $end + $var wire 32 . ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 % value [31:0] $end + $upscope $end + $scope module sub2b $end + $var wire 32 / ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 & value [31:0] $end + $upscope $end + $scope module sub2c $end + $var wire 32 0 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 ' value [31:0] $end + $upscope $end + $upscope $end + $scope module sub1b $end + $var wire 32 1 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 ( value [31:0] $end + $scope module sub2a $end + $var wire 32 2 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 ) value [31:0] $end + $upscope $end + $scope module sub2b $end + $var wire 32 3 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 * value [31:0] $end + $upscope $end + $scope module sub2c $end + $var wire 32 4 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 + value [31:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 # +b00000000000000000000000000001010 $ +b00000000000000000000000000001011 % +b00000000000000000000000000001100 & +b00000000000000000000000000001101 ' +b00000000000000000000000000010100 ( +b00000000000000000000000000010101 ) +b00000000000000000000000000010110 * +b00000000000000000000000000010111 + +0, +b00000000000000000000000000001010 - +b00000000000000000000000000001011 . +b00000000000000000000000000001100 / +b00000000000000000000000000001101 0 +b00000000000000000000000000010100 1 +b00000000000000000000000000010101 2 +b00000000000000000000000000010110 3 +b00000000000000000000000000010111 4 +#1 +b00000000000000000000000000000001 # +b00000000000000000000000000001011 $ +b00000000000000000000000000001100 % +b00000000000000000000000000001101 & +b00000000000000000000000000001110 ' +b00000000000000000000000000010101 ( +b00000000000000000000000000010110 ) +b00000000000000000000000000010111 * +b00000000000000000000000000011000 + +1, +#2 +0, +#3 +b00000000000000000000000000000010 # +b00000000000000000000000000001100 $ +b00000000000000000000000000001101 % +b00000000000000000000000000001110 & +b00000000000000000000000000001111 ' +b00000000000000000000000000010110 ( +b00000000000000000000000000010111 ) +b00000000000000000000000000011000 * +b00000000000000000000000000011001 + +1, +#4 +0, +#5 +b00000000000000000000000000000011 # +b00000000000000000000000000001101 $ +b00000000000000000000000000001110 % +b00000000000000000000000000001111 & +b00000000000000000000000000010000 ' +b00000000000000000000000000010111 ( +b00000000000000000000000000011000 ) +b00000000000000000000000000011001 * +b00000000000000000000000000011010 + +1, +#6 +0, +#7 +b00000000000000000000000000000100 # +b00000000000000000000000000001110 $ +b00000000000000000000000000001111 % +b00000000000000000000000000010000 & +b00000000000000000000000000010001 ' +b00000000000000000000000000011000 ( +b00000000000000000000000000011001 ) +b00000000000000000000000000011010 * +b00000000000000000000000000011011 + +1, +#8 +0, +#9 +b00000000000000000000000000000101 # +b00000000000000000000000000001111 $ +b00000000000000000000000000010000 % +b00000000000000000000000000010001 & +b00000000000000000000000000010010 ' +b00000000000000000000000000011001 ( +b00000000000000000000000000011010 ) +b00000000000000000000000000011011 * +b00000000000000000000000000011100 + +1, +#10 +0, +#11 +b00000000000000000000000000000110 # +b00000000000000000000000000010000 $ +b00000000000000000000000000010001 % +b00000000000000000000000000010010 & +b00000000000000000000000000010011 ' +b00000000000000000000000000011010 ( +b00000000000000000000000000011011 ) +b00000000000000000000000000011100 * +b00000000000000000000000000011101 + +1, +#12 +0, +#13 +b00000000000000000000000000000111 # +b00000000000000000000000000010001 $ +b00000000000000000000000000010010 % +b00000000000000000000000000010011 & +b00000000000000000000000000010100 ' +b00000000000000000000000000011011 ( +b00000000000000000000000000011100 ) +b00000000000000000000000000011101 * +b00000000000000000000000000011110 + +1, +#14 +0, +#15 +b00000000000000000000000000001000 # +b00000000000000000000000000010010 $ +b00000000000000000000000000010011 % +b00000000000000000000000000010100 & +b00000000000000000000000000010101 ' +b00000000000000000000000000011100 ( +b00000000000000000000000000011101 ) +b00000000000000000000000000011110 * +b00000000000000000000000000011111 + +1, +#16 +0, +#17 +b00000000000000000000000000001001 # +b00000000000000000000000000010011 $ +b00000000000000000000000000010100 % +b00000000000000000000000000010101 & +b00000000000000000000000000010110 ' +b00000000000000000000000000011101 ( +b00000000000000000000000000011110 ) +b00000000000000000000000000011111 * +b00000000000000000000000000100000 + +1, +#18 +0, +#19 +b00000000000000000000000000001010 # +b00000000000000000000000000010100 $ +b00000000000000000000000000010101 % +b00000000000000000000000000010110 & +b00000000000000000000000000010111 ' +b00000000000000000000000000011110 ( +b00000000000000000000000000011111 ) +b00000000000000000000000000100000 * +b00000000000000000000000000100001 + +1, +#20 +0, diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl new file mode 100755 index 000000000..31354ab6a --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl @@ -0,0 +1,27 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); + +top_filename("t_trace_dumpvars_dyn.v"); + +compile( + make_main => 0, + verilator_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out new file mode 100644 index 000000000..dd46b59b0 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out @@ -0,0 +1,129 @@ +$version Generated by VerilatedVcd $end +$date Sat Mar 5 13:47:52 2022 $end +$timescale 1ps $end + + $scope module top $end + $scope module t $end + $var wire 32 # cyc [31:0] $end + $scope module sub1a $end + $var wire 32 - ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ value [31:0] $end + $upscope $end + $scope module sub1b $end + $var wire 32 1 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 ( value [31:0] $end + $scope module sub2a $end + $var wire 32 2 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 ) value [31:0] $end + $upscope $end + $scope module sub2b $end + $var wire 32 3 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 * value [31:0] $end + $upscope $end + $scope module sub2c $end + $var wire 32 4 ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 + value [31:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 # +b00000000000000000000000000001010 $ +b00000000000000000000000000010100 ( +b00000000000000000000000000010101 ) +b00000000000000000000000000010110 * +b00000000000000000000000000010111 + +b00000000000000000000000000001010 - +b00000000000000000000000000010100 1 +b00000000000000000000000000010101 2 +b00000000000000000000000000010110 3 +b00000000000000000000000000010111 4 +#1 +b00000000000000000000000000000001 # +b00000000000000000000000000001011 $ +b00000000000000000000000000010101 ( +b00000000000000000000000000010110 ) +b00000000000000000000000000010111 * +b00000000000000000000000000011000 + +#2 +#3 +b00000000000000000000000000000010 # +b00000000000000000000000000001100 $ +b00000000000000000000000000010110 ( +b00000000000000000000000000010111 ) +b00000000000000000000000000011000 * +b00000000000000000000000000011001 + +#4 +#5 +b00000000000000000000000000000011 # +b00000000000000000000000000001101 $ +b00000000000000000000000000010111 ( +b00000000000000000000000000011000 ) +b00000000000000000000000000011001 * +b00000000000000000000000000011010 + +#6 +#7 +b00000000000000000000000000000100 # +b00000000000000000000000000001110 $ +b00000000000000000000000000011000 ( +b00000000000000000000000000011001 ) +b00000000000000000000000000011010 * +b00000000000000000000000000011011 + +#8 +#9 +b00000000000000000000000000000101 # +b00000000000000000000000000001111 $ +b00000000000000000000000000011001 ( +b00000000000000000000000000011010 ) +b00000000000000000000000000011011 * +b00000000000000000000000000011100 + +#10 +#11 +b00000000000000000000000000000110 # +b00000000000000000000000000010000 $ +b00000000000000000000000000011010 ( +b00000000000000000000000000011011 ) +b00000000000000000000000000011100 * +b00000000000000000000000000011101 + +#12 +#13 +b00000000000000000000000000000111 # +b00000000000000000000000000010001 $ +b00000000000000000000000000011011 ( +b00000000000000000000000000011100 ) +b00000000000000000000000000011101 * +b00000000000000000000000000011110 + +#14 +#15 +b00000000000000000000000000001000 # +b00000000000000000000000000010010 $ +b00000000000000000000000000011100 ( +b00000000000000000000000000011101 ) +b00000000000000000000000000011110 * +b00000000000000000000000000011111 + +#16 +#17 +b00000000000000000000000000001001 # +b00000000000000000000000000010011 $ +b00000000000000000000000000011101 ( +b00000000000000000000000000011110 ) +b00000000000000000000000000011111 * +b00000000000000000000000000100000 + +#18 +#19 +b00000000000000000000000000001010 # +b00000000000000000000000000010100 $ +b00000000000000000000000000011110 ( +b00000000000000000000000000011111 ) +b00000000000000000000000000100000 * +b00000000000000000000000000100001 + +#20 diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl new file mode 100755 index 000000000..70ccefe3c --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl @@ -0,0 +1,27 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); + +top_filename("t_trace_dumpvars_dyn.v"); + +compile( + make_main => 0, + verilator_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp -CFLAGS -DVL_DEBUG"], + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_trace_empty.pl b/test_regress/t/t_trace_empty.pl new file mode 100755 index 000000000..314b65d45 --- /dev/null +++ b/test_regress/t/t_trace_empty.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['--trace'], + ); + +execute( + check_finished => 1, + ); + +file_grep_not("$Self->{obj_dir}/simx.vcd", qr/scope/); +file_grep_not("$Self->{obj_dir}/simx.vcd", qr/upscope/); +file_grep_not("$Self->{obj_dir}/simx.vcd", qr/var/); + +ok(1); +1; diff --git a/test_regress/t/t_trace_empty.v b/test_regress/t/t_trace_empty.v new file mode 100644 index 000000000..132598f8a --- /dev/null +++ b/test_regress/t/t_trace_empty.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + /* verilator tracing_off */ + + input clk; + + reg [7:0] cyc = 8'd0; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_trace_fst.out b/test_regress/t/t_trace_fst.out index 16e4dc7d7..ccb48bc22 100644 --- a/test_regress/t/t_trace_fst.out +++ b/test_regress/t/t_trace_fst.out @@ -1,5 +1,5 @@ $date - Tue Aug 10 15:48:30 2021 + Wed Feb 23 00:01:36 2022 $end $version @@ -10,24 +10,24 @@ $timescale $end $scope module top $end $var wire 1 ! clk $end -$var wire 5 " state $end +$var wire 5 " state [4:0] $end $scope module t $end $var wire 1 ! clk $end -$var int 32 # cyc $end +$var int 32 # cyc [31:0] $end $var logic 1 $ rstn $end -$var wire 5 " state $end +$var wire 5 " state [4:0] $end $var real_parameter 64 % fst_gparam_real $end $var real_parameter 64 & fst_lparam_real $end $var real 64 % fst_real $end -$var integer 32 ' fst_integer $end +$var integer 32 ' fst_integer [31:0] $end $var bit 1 ( fst_bit $end $var logic 1 ) fst_logic $end -$var int 32 * fst_int $end -$var shortint 16 + fst_shortint $end -$var longint 64 , fst_longint $end -$var byte 8 - fst_byte $end -$var parameter 32 . fst_parameter $end -$var parameter 32 / fst_lparam $end +$var int 32 * fst_int [31:0] $end +$var shortint 16 + fst_shortint [15:0] $end +$var longint 64 , fst_longint [63:0] $end +$var byte 8 - fst_byte [7:0] $end +$var parameter 32 . fst_parameter [31:0] $end +$var parameter 32 / fst_lparam [31:0] $end $var supply0 1 0 fst_supply0 $end $var supply1 1 1 fst_supply1 $end $var tri0 1 2 fst_tri0 $end @@ -37,16 +37,16 @@ $var wire 1 5 fst_wire $end $scope module test $end $var wire 1 ! clk $end $var wire 1 $ rstn $end -$var wire 5 " state $end -$var logic 5 6 state_w $end -$var logic 5 7 state_array[0] $end -$var logic 5 8 state_array[1] $end -$var logic 5 9 state_array[2] $end -$scope module unnamedblk2 $end -$var int 32 : i $end -$upscope $end +$var wire 5 " state [4:0] $end +$var logic 5 6 state_w [4:0] $end +$var logic 5 7 state_array[0] [4:0] $end +$var logic 5 8 state_array[1] [4:0] $end +$var logic 5 9 state_array[2] [4:0] $end $scope module unnamedblk1 $end -$var int 32 ; i $end +$var int 32 : i [31:0] $end +$upscope $end +$scope module unnamedblk2 $end +$var int 32 ; i [31:0] $end $upscope $end $upscope $end $upscope $end @@ -90,7 +90,7 @@ b10100 6 b00001 7 b00001 8 b00001 9 -b00000000000000000000000000000011 ; +b00000000000000000000000000000011 : #15 0! #20 @@ -149,7 +149,7 @@ b00000000000000000000000000001011 # b00000000000000000000000000001100 # b10100 9 b01010 6 -b00000000000000000000000000000010 : +b00000000000000000000000000000010 ; #125 0! #130 diff --git a/test_regress/t/t_trace_fst_cmake.out b/test_regress/t/t_trace_fst_cmake.out index d3e911409..8b6e1c7d0 100644 --- a/test_regress/t/t_trace_fst_cmake.out +++ b/test_regress/t/t_trace_fst_cmake.out @@ -1,5 +1,5 @@ $date - Tue Aug 10 15:48:40 2021 + Wed Feb 23 00:01:51 2022 $end $version @@ -10,24 +10,24 @@ $timescale $end $scope module top $end $var wire 1 ! clk $end -$var wire 5 " state $end +$var wire 5 " state [4:0] $end $scope module t $end $var wire 1 ! clk $end -$var int 32 # cyc $end +$var int 32 # cyc [31:0] $end $var logic 1 $ rstn $end -$var wire 5 " state $end +$var wire 5 " state [4:0] $end $var real_parameter 64 % fst_gparam_real $end $var real_parameter 64 & fst_lparam_real $end $var real 64 % fst_real $end -$var integer 32 ' fst_integer $end +$var integer 32 ' fst_integer [31:0] $end $var bit 1 ( fst_bit $end $var logic 1 ) fst_logic $end -$var int 32 * fst_int $end -$var shortint 16 + fst_shortint $end -$var longint 64 , fst_longint $end -$var byte 8 - fst_byte $end -$var parameter 32 . fst_parameter $end -$var parameter 32 / fst_lparam $end +$var int 32 * fst_int [31:0] $end +$var shortint 16 + fst_shortint [15:0] $end +$var longint 64 , fst_longint [63:0] $end +$var byte 8 - fst_byte [7:0] $end +$var parameter 32 . fst_parameter [31:0] $end +$var parameter 32 / fst_lparam [31:0] $end $var supply0 1 0 fst_supply0 $end $var supply1 1 1 fst_supply1 $end $var tri0 1 2 fst_tri0 $end @@ -37,16 +37,16 @@ $var wire 1 5 fst_wire $end $scope module test $end $var wire 1 ! clk $end $var wire 1 $ rstn $end -$var wire 5 " state $end -$var logic 5 6 state_w $end -$var logic 5 7 state_array[0] $end -$var logic 5 8 state_array[1] $end -$var logic 5 9 state_array[2] $end -$scope module unnamedblk2 $end -$var int 32 : i $end -$upscope $end +$var wire 5 " state [4:0] $end +$var logic 5 6 state_w [4:0] $end +$var logic 5 7 state_array[0] [4:0] $end +$var logic 5 8 state_array[1] [4:0] $end +$var logic 5 9 state_array[2] [4:0] $end $scope module unnamedblk1 $end -$var int 32 ; i $end +$var int 32 : i [31:0] $end +$upscope $end +$scope module unnamedblk2 $end +$var int 32 ; i [31:0] $end $upscope $end $upscope $end $upscope $end @@ -90,7 +90,7 @@ b10100 6 b00001 7 b00001 8 b00001 9 -b00000000000000000000000000000011 ; +b00000000000000000000000000000011 : #15 0! #20 @@ -149,7 +149,7 @@ b00000000000000000000000000001011 # b00000000000000000000000000001100 # b10100 9 b01010 6 -b00000000000000000000000000000010 : +b00000000000000000000000000000010 ; #125 0! #130 diff --git a/test_regress/t/t_trace_fst_sc.out b/test_regress/t/t_trace_fst_sc.out index 28581fdda..1489d3bb6 100644 --- a/test_regress/t/t_trace_fst_sc.out +++ b/test_regress/t/t_trace_fst_sc.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 00:05:19 2021 + Wed Feb 23 00:01:58 2022 $end $version @@ -11,40 +11,40 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var int 32 " cyc $end +$var int 32 " cyc [31:0] $end $var logic 1 # rstn $end $var real_parameter 64 $ fst_gparam_real $end $var real_parameter 64 % fst_lparam_real $end $var real 64 $ fst_real $end -$var integer 32 & fst_integer $end +$var integer 32 & fst_integer [31:0] $end $var bit 1 ' fst_bit $end $var logic 1 ( fst_logic $end -$var int 32 ) fst_int $end -$var shortint 16 * fst_shortint $end -$var longint 64 + fst_longint $end -$var byte 8 , fst_byte $end -$var parameter 32 - fst_parameter $end -$var parameter 32 . fst_lparam $end +$var int 32 ) fst_int [31:0] $end +$var shortint 16 * fst_shortint [15:0] $end +$var longint 64 + fst_longint [63:0] $end +$var byte 8 , fst_byte [7:0] $end +$var parameter 32 - fst_parameter [31:0] $end +$var parameter 32 . fst_lparam [31:0] $end $var supply0 1 / fst_supply0 $end $var supply1 1 0 fst_supply1 $end $var tri0 1 1 fst_tri0 $end $var tri1 1 2 fst_tri1 $end $var tri 1 3 fst_tri $end $var wire 1 4 fst_wire $end -$var logic 5 5 state $end +$var logic 5 5 state [4:0] $end $scope module test $end $var wire 1 ! clk $end $var wire 1 # rstn $end -$var wire 5 5 state $end -$var logic 5 6 state_w $end -$var logic 5 7 state_array[0] $end -$var logic 5 8 state_array[1] $end -$var logic 5 9 state_array[2] $end -$scope module unnamedblk2 $end -$var int 32 : i $end -$upscope $end +$var wire 5 5 state [4:0] $end +$var logic 5 6 state_w [4:0] $end +$var logic 5 7 state_array[0] [4:0] $end +$var logic 5 8 state_array[1] [4:0] $end +$var logic 5 9 state_array[2] [4:0] $end $scope module unnamedblk1 $end -$var int 32 ; i $end +$var int 32 : i [31:0] $end +$upscope $end +$scope module unnamedblk2 $end +$var int 32 ; i [31:0] $end $upscope $end $upscope $end $upscope $end @@ -88,7 +88,7 @@ b10100 6 b00001 7 b00001 8 b00001 9 -b00000000000000000000000000000011 ; +b00000000000000000000000000000011 : #11 #12 #13 @@ -235,7 +235,7 @@ b00000000000000000000000000001011 " b00000000000000000000000000001100 " b10100 9 b01010 6 -b00000000000000000000000000000010 : +b00000000000000000000000000000010 ; #121 #122 #123 diff --git a/test_regress/t/t_trace_fst_sc_cmake.out b/test_regress/t/t_trace_fst_sc_cmake.out index 79ed28e84..e05529c9d 100644 --- a/test_regress/t/t_trace_fst_sc_cmake.out +++ b/test_regress/t/t_trace_fst_sc_cmake.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 02:14:06 2021 + Wed Feb 23 10:00:37 2022 $end $version @@ -11,40 +11,40 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var int 32 " cyc $end +$var int 32 " cyc [31:0] $end $var logic 1 # rstn $end $var real_parameter 64 $ fst_gparam_real $end $var real_parameter 64 % fst_lparam_real $end $var real 64 $ fst_real $end -$var integer 32 & fst_integer $end +$var integer 32 & fst_integer [31:0] $end $var bit 1 ' fst_bit $end $var logic 1 ( fst_logic $end -$var int 32 ) fst_int $end -$var shortint 16 * fst_shortint $end -$var longint 64 + fst_longint $end -$var byte 8 , fst_byte $end -$var parameter 32 - fst_parameter $end -$var parameter 32 . fst_lparam $end +$var int 32 ) fst_int [31:0] $end +$var shortint 16 * fst_shortint [15:0] $end +$var longint 64 + fst_longint [63:0] $end +$var byte 8 , fst_byte [7:0] $end +$var parameter 32 - fst_parameter [31:0] $end +$var parameter 32 . fst_lparam [31:0] $end $var supply0 1 / fst_supply0 $end $var supply1 1 0 fst_supply1 $end $var tri0 1 1 fst_tri0 $end $var tri1 1 2 fst_tri1 $end $var tri 1 3 fst_tri $end $var wire 1 4 fst_wire $end -$var logic 5 5 state $end +$var logic 5 5 state [4:0] $end $scope module test $end $var wire 1 ! clk $end $var wire 1 # rstn $end -$var wire 5 5 state $end -$var logic 5 6 state_w $end -$var logic 5 7 state_array[0] $end -$var logic 5 8 state_array[1] $end -$var logic 5 9 state_array[2] $end -$scope module unnamedblk2 $end -$var int 32 : i $end -$upscope $end +$var wire 5 5 state [4:0] $end +$var logic 5 6 state_w [4:0] $end +$var logic 5 7 state_array[0] [4:0] $end +$var logic 5 8 state_array[1] [4:0] $end +$var logic 5 9 state_array[2] [4:0] $end $scope module unnamedblk1 $end -$var int 32 ; i $end +$var int 32 : i [31:0] $end +$upscope $end +$scope module unnamedblk2 $end +$var int 32 ; i [31:0] $end $upscope $end $upscope $end $upscope $end @@ -88,7 +88,7 @@ b10100 6 b00001 7 b00001 8 b00001 9 -b00000000000000000000000000000011 ; +b00000000000000000000000000000011 : #11 #12 #13 @@ -235,7 +235,7 @@ b00000000000000000000000000001011 " b00000000000000000000000000001100 " b10100 9 b01010 6 -b00000000000000000000000000000010 : +b00000000000000000000000000000010 ; #121 #122 #123 diff --git a/test_regress/t/t_trace_litendian_fst.out b/test_regress/t/t_trace_litendian_fst.out index fca4ff32e..c89874b49 100644 --- a/test_regress/t/t_trace_litendian_fst.out +++ b/test_regress/t/t_trace_litendian_fst.out @@ -1,5 +1,5 @@ $date - Sun May 3 21:53:46 2020 + Wed Feb 23 00:02:30 2022 $end $version @@ -11,32 +11,32 @@ $end $scope module top $end $var wire 1 ! clk $end $scope module t $end -$var parameter 8 " P $end +$var parameter 8 " P [0:7] $end $var wire 1 ! clk $end -$var int 32 # cyc $end -$var parameter 8 $ Q $end -$var logic 1 % v_a $end -$var logic 2 & v_b $end -$var logic 8 ' v_c $end -$var logic 9 ( v_d $end -$var logic 16 ) v_e $end -$var logic 17 * v_f $end -$var logic 32 + v_g $end -$var logic 33 , v_h $end -$var logic 64 - v_i $end -$var logic 65 . v_j $end -$var logic 128 / v_k $end -$var logic 129 0 v_l $end -$var logic 256 1 v_m $end -$var logic 257 2 v_n $end -$var logic 512 3 v_o $end -$var logic 3 4 v_p $end -$var logic 15 5 v_q $end -$var logic 31 6 v_r $end -$var logic 63 7 v_s $end -$var logic 127 8 v_t $end -$var logic 255 9 v_u $end -$var logic 511 : v_v $end +$var int 32 # cyc [31:0] $end +$var parameter 8 $ Q [0:7] $end +$var logic 1 % v_a [0:0] $end +$var logic 2 & v_b [0:1] $end +$var logic 8 ' v_c [0:7] $end +$var logic 9 ( v_d [0:8] $end +$var logic 16 ) v_e [0:15] $end +$var logic 17 * v_f [0:16] $end +$var logic 32 + v_g [0:31] $end +$var logic 33 , v_h [0:32] $end +$var logic 64 - v_i [0:63] $end +$var logic 65 . v_j [0:64] $end +$var logic 128 / v_k [0:127] $end +$var logic 129 0 v_l [0:128] $end +$var logic 256 1 v_m [0:255] $end +$var logic 257 2 v_n [0:256] $end +$var logic 512 3 v_o [0:511] $end +$var logic 3 4 v_p [-1:1] $end +$var logic 15 5 v_q [-7:7] $end +$var logic 31 6 v_r [-15:15] $end +$var logic 63 7 v_s [-31:31] $end +$var logic 127 8 v_t [-63:63] $end +$var logic 255 9 v_u [-127:127] $end +$var logic 511 : v_v [-255:255] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_litendian_fst_sc.out b/test_regress/t/t_trace_litendian_fst_sc.out index 1a837701c..c71d0eec7 100644 --- a/test_regress/t/t_trace_litendian_fst_sc.out +++ b/test_regress/t/t_trace_litendian_fst_sc.out @@ -1,5 +1,5 @@ $date - Thu Apr 1 15:29:34 2021 + Wed Feb 23 00:02:36 2022 $end $version @@ -10,32 +10,32 @@ $timescale $end $scope module top $end $scope module t $end -$var parameter 8 ! P $end +$var parameter 8 ! P [0:7] $end $var wire 1 " clk $end -$var int 32 # cyc $end -$var parameter 8 $ Q $end -$var logic 1 % v_a $end -$var logic 2 & v_b $end -$var logic 8 ' v_c $end -$var logic 9 ( v_d $end -$var logic 16 ) v_e $end -$var logic 17 * v_f $end -$var logic 32 + v_g $end -$var logic 33 , v_h $end -$var logic 64 - v_i $end -$var logic 65 . v_j $end -$var logic 128 / v_k $end -$var logic 129 0 v_l $end -$var logic 256 1 v_m $end -$var logic 257 2 v_n $end -$var logic 512 3 v_o $end -$var logic 3 4 v_p $end -$var logic 15 5 v_q $end -$var logic 31 6 v_r $end -$var logic 63 7 v_s $end -$var logic 127 8 v_t $end -$var logic 255 9 v_u $end -$var logic 511 : v_v $end +$var int 32 # cyc [31:0] $end +$var parameter 8 $ Q [0:7] $end +$var logic 1 % v_a [0:0] $end +$var logic 2 & v_b [0:1] $end +$var logic 8 ' v_c [0:7] $end +$var logic 9 ( v_d [0:8] $end +$var logic 16 ) v_e [0:15] $end +$var logic 17 * v_f [0:16] $end +$var logic 32 + v_g [0:31] $end +$var logic 33 , v_h [0:32] $end +$var logic 64 - v_i [0:63] $end +$var logic 65 . v_j [0:64] $end +$var logic 128 / v_k [0:127] $end +$var logic 129 0 v_l [0:128] $end +$var logic 256 1 v_m [0:255] $end +$var logic 257 2 v_n [0:256] $end +$var logic 512 3 v_o [0:511] $end +$var logic 3 4 v_p [-1:1] $end +$var logic 15 5 v_q [-7:7] $end +$var logic 31 6 v_r [-15:15] $end +$var logic 63 7 v_s [-31:31] $end +$var logic 127 8 v_t [-63:63] $end +$var logic 255 9 v_u [-127:127] $end +$var logic 511 : v_v [-255:255] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_packed_struct_fst.out b/test_regress/t/t_trace_packed_struct_fst.out index 05ed7013f..83fea4dc4 100644 --- a/test_regress/t/t_trace_packed_struct_fst.out +++ b/test_regress/t/t_trace_packed_struct_fst.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 12:42:37 2021 + Wed Feb 23 00:02:43 2022 $end $version @@ -12,10 +12,10 @@ $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var int 32 " cnt $end -$var parameter 96 # v[0] $end -$var parameter 96 $ v[1] $end -$var parameter 96 % v[2] $end +$var int 32 " cnt [31:0] $end +$var parameter 96 # v[0] [95:0] $end +$var parameter 96 $ v[1] [95:0] $end +$var parameter 96 % v[2] [95:0] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.out b/test_regress/t/t_trace_packed_struct_fst_sc.out index c42a1574d..77ca0d48b 100644 --- a/test_regress/t/t_trace_packed_struct_fst_sc.out +++ b/test_regress/t/t_trace_packed_struct_fst_sc.out @@ -1,5 +1,5 @@ $date - Wed Aug 11 12:42:40 2021 + Wed Feb 23 00:02:49 2022 $end $version @@ -11,10 +11,10 @@ $end $scope module top $end $scope module t $end $var wire 1 ! clk $end -$var int 32 " cnt $end -$var parameter 96 # v[0] $end -$var parameter 96 $ v[1] $end -$var parameter 96 % v[2] $end +$var int 32 " cnt [31:0] $end +$var parameter 96 # v[0] [95:0] $end +$var parameter 96 $ v[1] [95:0] $end +$var parameter 96 % v[2] [95:0] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_public_sig_vlt.pl b/test_regress/t/t_trace_public_sig_vlt.pl index c29e1cdc2..2bf507248 100755 --- a/test_regress/t/t_trace_public_sig_vlt.pl +++ b/test_regress/t/t_trace_public_sig_vlt.pl @@ -22,7 +22,7 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_trace_two_dumpfst_cc.out b/test_regress/t/t_trace_two_dumpfst_cc.out index c22d2b128..acf81917a 100755 --- a/test_regress/t/t_trace_two_dumpfst_cc.out +++ b/test_regress/t/t_trace_two_dumpfst_cc.out @@ -1,5 +1,5 @@ $date - Sun Apr 19 04:15:48 2020 + Wed Feb 23 00:03:30 2022 $end $version @@ -12,74 +12,75 @@ $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var integer 32 # c_trace_on $end +$var integer 32 " cyc [31:0] $end +$var integer 32 # c_trace_on [31:0] $end $scope module sub $end -$var integer 32 $ inside_sub_a $end +$var integer 32 $ inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end -$dumpvars #10 +$dumpvars b00000000000000000000000000000001 $ b00000000000000000000000000000000 # b00000000000000000000000000000001 " 1! +$end #15 0! #20 1! -b00000000000000000000000000000011 # b00000000000000000000000000000010 " +b00000000000000000000000000000011 # #25 0! #30 1! -b00000000000000000000000000000011 " b00000000000000000000000000000100 # +b00000000000000000000000000000011 " #35 0! #40 1! -b00000000000000000000000000000101 # b00000000000000000000000000000100 " +b00000000000000000000000000000101 # #45 0! #50 1! -b00000000000000000000000000000101 " b00000000000000000000000000000110 # +b00000000000000000000000000000101 " #55 0! #60 1! -b00000000000000000000000000000111 # b00000000000000000000000000000110 " +b00000000000000000000000000000111 # #65 0! #70 1! -b00000000000000000000000000000111 " b00000000000000000000000000001000 # +b00000000000000000000000000000111 " #75 0! #80 1! -b00000000000000000000000000001001 # b00000000000000000000000000001000 " +b00000000000000000000000000001001 # #85 0! #90 1! -b00000000000000000000000000001001 " b00000000000000000000000000001010 # +b00000000000000000000000000001001 " #95 0! #100 1! -b00000000000000000000000000001011 # b00000000000000000000000000001010 " +b00000000000000000000000000001011 # #105 0! #110 diff --git a/test_regress/t/t_trace_two_hdrfst_cc.out b/test_regress/t/t_trace_two_hdrfst_cc.out index 538f5e7e6..b75e81726 100755 --- a/test_regress/t/t_trace_two_hdrfst_cc.out +++ b/test_regress/t/t_trace_two_hdrfst_cc.out @@ -1,5 +1,5 @@ $date - Sun Apr 19 04:15:51 2020 + Wed Feb 23 00:03:39 2022 $end $version @@ -12,10 +12,10 @@ $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var integer 32 # c_trace_on $end +$var integer 32 " cyc [31:0] $end +$var integer 32 # c_trace_on [31:0] $end $scope module sub $end -$var integer 32 $ inside_sub_a $end +$var integer 32 $ inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end @@ -23,109 +23,111 @@ $scope module topb $end $var wire 1 % clk $end $scope module t $end $var wire 1 % clk $end -$var integer 32 & cyc $end -$var integer 32 ' c_trace_on $end +$var integer 32 & cyc [31:0] $end +$var integer 32 ' c_trace_on [31:0] $end $var real 64 ( r $end $scope module sub $end -$var integer 32 ) inside_sub_a $end +$var integer 32 ) inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end +#0 $dumpvars -0! -b00000000000000000000000000000001 " -b00000000000000000000000000000000 # -b00000000000000000000000000000001 $ -0% -b00000000000000000000000000000001 & -b00000000000000000000000000000000 ' -r0 ( b00000000000000000000000000000010 ) +r0 ( +b00000000000000000000000000000000 ' +b00000000000000000000000000000001 & +0% +b00000000000000000000000000000001 $ +b00000000000000000000000000000000 # +b00000000000000000000000000000001 " +0! +$end #10 -r0.1 ( -1% -b00000000000000000000000000000011 # +1! b00000000000000000000000000000010 " -1! +b00000000000000000000000000000011 # +1% +r0.1 ( #15 -0! 0% +0! #20 -1% 1! -b00000000000000000000000000000011 " -b00000000000000000000000000000100 # +1% r0.2 ( +b00000000000000000000000000000100 # +b00000000000000000000000000000011 " #25 -0! 0% +0! #30 -1% 1! -r0.3 ( -b00000000000000000000000000000101 # +1% b00000000000000000000000000000100 " +b00000000000000000000000000000101 # +r0.3 ( #35 -0! 0% +0! #40 -1% 1! -b00000000000000000000000000000101 " -b00000000000000000000000000000110 # +1% r0.4 ( +b00000000000000000000000000000110 # +b00000000000000000000000000000101 " #45 -0! 0% +0! #50 -1% 1! -r0.5 ( -b00000000000000000000000000000111 # +1% b00000000000000000000000000000110 " +b00000000000000000000000000000111 # +r0.5 ( #55 -0! 0% +0! #60 -1% 1! -b00000000000000000000000000000111 " -b00000000000000000000000000001000 # +1% r0.6 ( +b00000000000000000000000000001000 # +b00000000000000000000000000000111 " #65 -0! 0% +0! #70 -1% 1! -r0.7 ( -b00000000000000000000000000001001 # +1% b00000000000000000000000000001000 " +b00000000000000000000000000001001 # +r0.7 ( #75 -0! 0% +0! #80 -1% 1! -b00000000000000000000000000001001 " -b00000000000000000000000000001010 # +1% r0.7999999999999999 ( +b00000000000000000000000000001010 # +b00000000000000000000000000001001 " #85 -0! 0% +0! #90 -1% 1! -r0.8999999999999999 ( -b00000000000000000000000000001011 # +1% b00000000000000000000000000001010 " +b00000000000000000000000000001011 # +r0.8999999999999999 ( #95 -0! 0% +0! #100 -1% 1! -b00000000000000000000000000001011 " -b00000000000000000000000000001100 # +1% r0.9999999999999999 ( +b00000000000000000000000000001100 # +b00000000000000000000000000001011 " diff --git a/test_regress/t/t_trace_two_portfst_cc.out b/test_regress/t/t_trace_two_portfst_cc.out index a8a068954..b5d162d32 100755 --- a/test_regress/t/t_trace_two_portfst_cc.out +++ b/test_regress/t/t_trace_two_portfst_cc.out @@ -1,5 +1,5 @@ $date - Sun Apr 19 04:13:00 2020 + Wed Feb 23 00:03:49 2022 $end $version @@ -12,74 +12,75 @@ $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end -$var integer 32 " cyc $end -$var integer 32 # c_trace_on $end +$var integer 32 " cyc [31:0] $end +$var integer 32 # c_trace_on [31:0] $end $scope module sub $end -$var integer 32 $ inside_sub_a $end +$var integer 32 $ inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end -$dumpvars #10 +$dumpvars b00000000000000000000000000000001 $ b00000000000000000000000000000000 # b00000000000000000000000000000001 " 1! +$end #15 0! #20 1! -b00000000000000000000000000000011 # b00000000000000000000000000000010 " +b00000000000000000000000000000011 # #25 0! #30 1! -b00000000000000000000000000000011 " b00000000000000000000000000000100 # +b00000000000000000000000000000011 " #35 0! #40 1! -b00000000000000000000000000000101 # b00000000000000000000000000000100 " +b00000000000000000000000000000101 # #45 0! #50 1! -b00000000000000000000000000000101 " b00000000000000000000000000000110 # +b00000000000000000000000000000101 " #55 0! #60 1! -b00000000000000000000000000000111 # b00000000000000000000000000000110 " +b00000000000000000000000000000111 # #65 0! #70 1! -b00000000000000000000000000000111 " b00000000000000000000000000001000 # +b00000000000000000000000000000111 " #75 0! #80 1! -b00000000000000000000000000001001 # b00000000000000000000000000001000 " +b00000000000000000000000000001001 # #85 0! #90 1! -b00000000000000000000000000001001 " b00000000000000000000000000001010 # +b00000000000000000000000000001001 " #95 0! #100 1! -b00000000000000000000000000001011 # b00000000000000000000000000001010 " +b00000000000000000000000000001011 # #105 0! #110 diff --git a/test_regress/t/t_trace_two_sc.cpp b/test_regress/t/t_trace_two_sc.cpp index bd4f0ad77..232b932a6 100644 --- a/test_regress/t/t_trace_two_sc.cpp +++ b/test_regress/t/t_trace_two_sc.cpp @@ -40,6 +40,7 @@ int sc_main(int argc, char** argv) { #ifdef TEST_HDR_TRACE VerilatedVcdSc* tfp = new VerilatedVcdSc; + sc_core::sc_start(sc_core::SC_ZERO_TIME); ap->trace(tfp, 99); bp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); diff --git a/test_regress/t/t_tri_dangle.v b/test_regress/t/t_tri_dangle.v index 20a5363e4..de92cd777 100644 --- a/test_regress/t/t_tri_dangle.v +++ b/test_regress/t/t_tri_dangle.v @@ -29,4 +29,6 @@ module sub (/*AUTOARG*/ // verilator no_inline_module inout AVDD; inout AVSS; + tri NON_IO; + initial if (NON_IO !== 'z) $stop; endmodule diff --git a/test_regress/t/t_tri_inout.v b/test_regress/t/t_tri_inout.v index d466259cd..d6624b04d 100644 --- a/test_regress/t/t_tri_inout.v +++ b/test_regress/t/t_tri_inout.v @@ -11,7 +11,7 @@ module top (input A, input B, input SEL, output Y1, output Y2, output Z); endmodule module pass (input A, input OE, inout Z, output Y); - io io(.A(A), .OE(OE), .Z(Z), .Y(Y)); + io_noinline io(.A(A), .OE(OE), .Z(Z), .Y(Y)); assign Z = 1'bz; endmodule @@ -20,3 +20,10 @@ module io (input A, input OE, inout Z, output Y); assign Y = Z; assign Z = 1'bz; endmodule + +module io_noinline (input A, input OE, inout Z, output Y); + /*verilator no_inline_module*/ + assign Z = (OE) ? A : 1'bz; + assign Y = Z; + assign Z = 1'bz; +endmodule diff --git a/test_regress/t/t_unopt_combo_isolate.pl b/test_regress/t/t_unopt_combo_isolate.pl index cd9c893bb..cbc33dab8 100755 --- a/test_regress/t/t_unopt_combo_isolate.pl +++ b/test_regress/t/t_unopt_combo_isolate.pl @@ -19,11 +19,11 @@ compile( if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.pl b/test_regress/t/t_unopt_combo_isolate_vlt.pl index a71d1a004..f8aa4fcc3 100755 --- a/test_regress/t/t_unopt_combo_isolate_vlt.pl +++ b/test_regress/t/t_unopt_combo_isolate_vlt.pl @@ -19,11 +19,11 @@ compile( if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_var_pins_cc.pl b/test_regress/t/t_var_pins_cc.pl index 6c48aeee9..b8e67d8a0 100755 --- a/test_regress/t/t_var_pins_cc.pl +++ b/test_regress/t/t_var_pins_cc.pl @@ -25,14 +25,14 @@ compile( file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN16 \(&i16,15,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN \(&i32,31,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN64 \(&i64,63,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_INW \(\(&i65\),64,0,3\);/x); + file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_INW \(&i65,64,0,3\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8 \(&o1,0,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8 \(&o8,7,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT16\(&o16,15,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT \(&o32,31,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT64\(&o64,63,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUTW \(\(&o65\),64,0,3\);/x); + file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUTW \(&o65,64,0,3\);/x); } ok(1); diff --git a/test_regress/t/t_var_port_xml.out b/test_regress/t/t_var_port_xml.out index 5ca861df1..abbbdb652 100644 --- a/test_regress/t/t_var_port_xml.out +++ b/test_regress/t/t_var_port_xml.out @@ -11,119 +11,119 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - - + + + + + - - - - - + + + + + - - - - + + + + diff --git a/test_regress/t/t_verilated_debug.out b/test_regress/t/t_verilated_debug.out index 932ee8483..9cbfc96c8 100644 --- a/test_regress/t/t_verilated_debug.out +++ b/test_regress/t/t_verilated_debug.out @@ -8,7 +8,7 @@ internalsDump: -V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval_step -V{t#,#}+ Vt_verilated_debug___024root___eval_debug_assertions -V{t#,#}+ Vt_verilated_debug___024root___eval_initial --V{t#,#}+ Vt_verilated_debug___024root___initial__TOP__1 +-V{t#,#}+ Vt_verilated_debug___024root___initial__TOP__0 Data: w96: 000000aa 000000bb 000000cc -V{t#,#}+ Initial loop -V{t#,#}+ Vt_verilated_debug___024root___eval_settle @@ -19,6 +19,6 @@ internalsDump: -V{t#,#}+ Vt_verilated_debug___024root___eval_debug_assertions -V{t#,#}+ Clock loop -V{t#,#}+ Vt_verilated_debug___024root___eval --V{t#,#}+ Vt_verilated_debug___024root___sequent__TOP__2 +-V{t#,#}+ Vt_verilated_debug___024root___sequent__TOP__0 *-* All Finished *-* -V{t#,#}+ Vt_verilated_debug___024root___final diff --git a/test_regress/t/t_vlt_warn.vlt b/test_regress/t/t_vlt_warn.vlt index e4f858780..33725c2ca 100644 --- a/test_regress/t/t_vlt_warn.vlt +++ b/test_regress/t/t_vlt_warn.vlt @@ -11,7 +11,7 @@ lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v" lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 19 lint_off -rule DECLFILENAME -file "*/t_vlt_warn.v" // Test wildcard filenames -lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 20-20 +lint_off -rule WIDTH -file "*/t_vlt_warn.v" -lines 20-20 // Test global disables lint_off -file "*/t_vlt_warn.v" -lines 21-21 // Test match diff --git a/test_regress/t/t_vlt_warn_bad.out b/test_regress/t/t_vlt_warn_bad.out index 29c29c3b9..f8f64f115 100644 --- a/test_regress/t/t_vlt_warn_bad.out +++ b/test_regress/t/t_vlt_warn_bad.out @@ -1,10 +1,7 @@ -%Warning-DEPRECATED: t/t_vlt_warn_bad.vlt:12:10: Deprecated -msg in configuration files, use -rule instead. - 12 | lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 - | ^~~~ - ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest - ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. : ... In instance t 21 | reg width_warn3_var_line20 = 2'b11; | ^~~~~ + ... For warning description see https://verilator.org/warn/WIDTH?v=latest + ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_vlt_warn_bad.vlt b/test_regress/t/t_vlt_warn_bad.vlt index 3b07dacac..d7becb03f 100644 --- a/test_regress/t/t_vlt_warn_bad.vlt +++ b/test_regress/t/t_vlt_warn_bad.vlt @@ -9,7 +9,7 @@ lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v" lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 18 // Test wildcard filenames -lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 +lint_off -rule WIDTH -file "*/t_vlt_warn.v" -lines 19-19 // Test global disables lint_off -file "*/t_vlt_warn.v" -lines 20-20 diff --git a/test_regress/t/t_wrapper_context.cpp b/test_regress/t/t_wrapper_context.cpp index 9e203673c..87332eb8c 100644 --- a/test_regress/t/t_wrapper_context.cpp +++ b/test_regress/t/t_wrapper_context.cpp @@ -15,6 +15,11 @@ #include VM_PREFIX_INCLUDE +// Check we properly define the version integer +#if VERILATOR_VERSION_INTEGER < 4219000 // Added in 4.219 +#error "VERILATOR_VERSION_INTEGER not set" +#endif + double sc_time_stamp() { return 0; } int errors = 0; diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out index bbe26868f..7ef8e07b3 100644 --- a/test_regress/t/t_xml_debugcheck.out +++ b/test_regress/t/t_xml_debugcheck.out @@ -11,171 +11,171 @@ - - + + - + - - - - - - - - + + + + + + + + - - - - - - - - - + + + + + + + + + - - - + + + - - - - + + + + - + - + - - - - + + + + - - - + + + - - - - + + + + - - - - - - - - - + + + + + + + + + - - - - - - - + + + + + + + - + - - - + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -183,18 +183,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -202,82 +202,82 @@ - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -285,18 +285,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -304,128 +304,128 @@ - + - - - + + + - - - - + + + + - - - - - - - - - + + + + + + + + + - - - - - - - + + + + + + + - + - - - + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -433,18 +433,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -452,82 +452,82 @@ - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -535,18 +535,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -554,128 +554,128 @@ - + - - - + + + - - - - + + + + - - - - - - - - - + + + + + + + + + - - - - - - - + + + + + + + - + - - - + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -683,18 +683,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -702,82 +702,82 @@ - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -785,18 +785,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -804,25 +804,25 @@ - + - - - + + + - - - - + + + + - - + + - + @@ -833,70 +833,70 @@ - - - + + + - - - + + + - - - - - - - + + + + + + + - - - + + + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -904,18 +904,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -923,22 +923,22 @@ - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -946,18 +946,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -965,26 +965,26 @@ - + - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + @@ -994,22 +994,22 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -1019,26 +1019,26 @@ - + - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + @@ -1048,22 +1048,22 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -1073,26 +1073,26 @@ - + - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + @@ -1102,22 +1102,22 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -1127,82 +1127,82 @@ - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -1210,18 +1210,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -1229,22 +1229,22 @@ - + - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -1252,18 +1252,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -1271,288 +1271,288 @@ - + - - - - - - - - - + + + + + + + + + - - - - - - - + + + + + + + - + - - - + + + - + - - - + + + - - - + + + - + - - - - + + + + - - - - - - - - - + + + + + + + + + - + - - - - - - - + + + + + + + - + - - - + + + - - - - + + + + - + - - - - + + + + - - - + + + - + - - - - - + + + + + - - - + + + - + - - - + + + - - - - + + + + - + - - - - - - - + + + + + + + - - + + - - - + + + - - + + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - + + - - + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + - - + + - - + + - - - - - - - + + + + + + + - - - - + + + + - - - - + + + + - - - - - - + + + + + + - - + + diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out index 929ff89c1..50968cab7 100644 --- a/test_regress/t/t_xml_first.out +++ b/test_regress/t/t_xml_first.out @@ -11,75 +11,75 @@ - - - + + + - - - - - - - - + + + + + + + + - - + + - - + + - - - + + + - - + + - - + + - - - + + + + + + + + + + + + - - - - - + + + + + - - - - + + + + - - - + + + - - - - - - - - - - - - - + + + + diff --git a/test_regress/t/t_xml_flat.out b/test_regress/t/t_xml_flat.out index ea35502fc..eae232855 100644 --- a/test_regress/t/t_xml_flat.out +++ b/test_regress/t/t_xml_flat.out @@ -11,104 +11,104 @@ - + - - - - - - - - - - + + + + + + + + + + - - - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - + + + + diff --git a/test_regress/t/t_xml_flat_no_inline_mod.out b/test_regress/t/t_xml_flat_no_inline_mod.out index e1d070bce..228c0e8f2 100644 --- a/test_regress/t/t_xml_flat_no_inline_mod.out +++ b/test_regress/t/t_xml_flat_no_inline_mod.out @@ -11,31 +11,31 @@ - + - - - - - - - - - - - - + + + + + + + + + + + + - - - + + + - - + + diff --git a/test_regress/t/t_xml_flat_pub_mod.out b/test_regress/t/t_xml_flat_pub_mod.out index 88b51b3ca..e659f2ba4 100644 --- a/test_regress/t/t_xml_flat_pub_mod.out +++ b/test_regress/t/t_xml_flat_pub_mod.out @@ -11,31 +11,31 @@ - + - - - - - - - - - - - - + + + + + + + + + + + + - - - + + + - - + + diff --git a/test_regress/t/t_xml_flat_vlvbound.out b/test_regress/t/t_xml_flat_vlvbound.out index 0ccd4afa3..214b2626a 100644 --- a/test_regress/t/t_xml_flat_vlvbound.out +++ b/test_regress/t/t_xml_flat_vlvbound.out @@ -11,205 +11,205 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + - - - + + + - - - + + + - - - - - + + + + + - - - + + + - + - - - + + + - - - - - - - - - + + + + + + + + + - - + + - + - - - - - - + + + + + + - + - - - - + + + + - + - - - + + + - - - + + + - - - - - + + + + + - - - + + + - + - - - + + + - - - - - - - - - + + + + + + + + + - - + + - + - - - - - - + + + + + + - + - - - - + + + + - + - - - + + + - - - + + + - - - - - - - - + + + + + + + + - - - - - - - - - - + + + + + + + + + + diff --git a/test_regress/t/t_xml_output.out b/test_regress/t/t_xml_output.out index 645a7b61b..c2ca4faf4 100644 --- a/test_regress/t/t_xml_output.out +++ b/test_regress/t/t_xml_output.out @@ -11,14 +11,14 @@ - + - - + + - - + + diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out index 9c4c044e7..71b99ee25 100644 --- a/test_regress/t/t_xml_tag.out +++ b/test_regress/t/t_xml_tag.out @@ -11,72 +11,72 @@ - - + + - - - - - - - - - - - - + + + + + + + + + + + + - - - - - - + + + + + + - - - - - + + + + + - - - - + + + + - - - - - - - - - - - - + + + + + + + + + + + + - - - - - - - + + + + + + + - + diff --git a/verilator-config-version.cmake.in b/verilator-config-version.cmake.in index d07e29f2c..d878347c7 100644 --- a/verilator-config-version.cmake.in +++ b/verilator-config-version.cmake.in @@ -7,7 +7,7 @@ # # find_package(verilate 4.0) # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index c75e469d4..f408721c4 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -11,7 +11,7 @@ # add_executable(simulator ) # verilate(simulator SOURCES ) # -# Copyright 2003-2021 by Wilson Snyder. This program is free software; you +# Copyright 2003-2022 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0.