diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index f5e55d2a7..e11285aa6 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -9661,7 +9661,8 @@ class WidthVisitor final : public VNVisitor {
                     continue;
                 } else if (const AstNodeUOrStructDType* const adtypep
                            = VN_CAST(dtypep, NodeUOrStructDType)) {
-                    bits *= adtypep->width();
+                    bits *= adtypep->isStreamableFixedAggregate() ? adtypep->widthStream()
+                                                                  : adtypep->width();
                     break;
                 } else if (const AstBasicDType* const adtypep = VN_CAST(dtypep, BasicDType)) {
                     bits *= adtypep->width();
diff --git a/test_regress/t/t_stream_unpacked_struct.v b/test_regress/t/t_stream_unpacked_struct.v
index 8a169c20e..d125a9039 100644
--- a/test_regress/t/t_stream_unpacked_struct.v
+++ b/test_regress/t/t_stream_unpacked_struct.v
@@ -122,6 +122,7 @@ module t;
   logic [15:0] packed_union_bits;
   logic [11:0] narrow_bits;
   logic [19:0] simple_streaml_src;
+  logic [$bits(simple_t)-1:0] simple_bits_from_bits;
   byte byte_array_out[2];
 
   assign {>>{simple_cont_out}} = 20'habcde;
@@ -138,6 +139,13 @@ module t;
     `checkh(simple_bits, 20'h54321);
 
     simple = '{8'h12, 4'ha, '{4'hb, 4'hc}};
+    `checkh($bits(simple_t), 20);
+    `checkh($bits(array_t), 32);
+    `checkh($bits(nested_t), 36);
+    `checkh($bits(struct_array_t), 56);
+    `checkh($bits(simple_array), 40);
+    simple_bits_from_bits = {>>{simple}};
+    `checkh(simple_bits_from_bits, 20'h12abc);
     simple_bits = {>>{simple}};
     `checkh(simple_bits, 20'h12abc);
     /* verilator lint_off WIDTHEXPAND */