diff --git a/src/verilog.l b/src/verilog.l
index 07fb87abf..b2cf6533f 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -318,7 +318,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "endmodule"           { FL; return yENDMODULE; }
   "endprimitive"        { FL; return yENDPRIMITIVE; }
   "endspecify"          { FL; return yENDSPECIFY; }
-  "endtable"            { FL; yylval.fl->v3error("Syntax error: ENDTABLE outside of TABLE"); FL_BRK; }
+  "endtable"            { FL; yylval.fl->v3error("Syntax error: 'endtable' outside of 'table'"); FL_BRK; }
   "endtask"             { FL; return yENDTASK; }
   "event"               { FL; return yEVENT; }
   "for"                 { FL; return yFOR; }
@@ -961,7 +961,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 <TABLE>"endtable"       { yy_pop_state(); FL; return yENDTABLE; }
 <TABLE>"`line"{ws}+[^\n\r]*{crnl}       { FL_FWD; PARSEP->lexPpline(yytext); FL_BRK; }
 <TABLE>.                { yymore(); }
-<TABLE><<EOF>>          { FL; yylval.fl->v3error("EOF in TABLE");
+<TABLE><<EOF>>          { FL; yylval.fl->v3error("EOF in 'table'");
                           yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
 
   /************************************************************************/
diff --git a/test_regress/t/t_udp_tableend_bad.out b/test_regress/t/t_udp_tableend_bad.out
new file mode 100644
index 000000000..d673497d0
--- /dev/null
+++ b/test_regress/t/t_udp_tableend_bad.out
@@ -0,0 +1,4 @@
+%Error: t/t_udp_tableend_bad.v:11:4: Syntax error: 'endtable' outside of 'table'
+   11 |    endtable   
+      |    ^~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_udp_tableend_bad.pl b/test_regress/t/t_udp_tableend_bad.pl
new file mode 100755
index 000000000..fc220ea47
--- /dev/null
+++ b/test_regress/t/t_udp_tableend_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only --bbox-unsup"],
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_udp_tableend_bad.v b/test_regress/t/t_udp_tableend_bad.v
new file mode 100644
index 000000000..6597e7be6
--- /dev/null
+++ b/test_regress/t/t_udp_tableend_bad.v
@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2009 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+primitive udp_x (a_bad, b, c_bad);
+   tri  a_bad;
+   output b;
+   output c_bad;
+   endtable  // BAD
+endprimitive
diff --git a/test_regress/t/t_udp_tableeof_bad.out b/test_regress/t/t_udp_tableeof_bad.out
new file mode 100644
index 000000000..bf61e32d3
--- /dev/null
+++ b/test_regress/t/t_udp_tableeof_bad.out
@@ -0,0 +1,3 @@
+%Error: t/t_udp_tableeof_bad.v:16:1: EOF in 'table'
+%Error: t/t_udp_tableeof_bad.v:16:1: syntax error, unexpected end of file, expecting TABLE LINE or endtable
+%Error: Cannot continue
diff --git a/test_regress/t/t_udp_tableeof_bad.pl b/test_regress/t/t_udp_tableeof_bad.pl
new file mode 100755
index 000000000..fc220ea47
--- /dev/null
+++ b/test_regress/t/t_udp_tableeof_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only --bbox-unsup"],
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_udp_tableeof_bad.v b/test_regress/t/t_udp_tableeof_bad.v
new file mode 100644
index 000000000..064573395
--- /dev/null
+++ b/test_regress/t/t_udp_tableeof_bad.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2009 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+primitive udp_x (a_bad, b, c_bad);
+   tri  a_bad;
+   output b;
+   output c_bad;
+   table
+      //a   b
+      0  :   1;
+      1  :   0;