diff --git a/Changes b/Changes
index a207b925a..42ce9b19b 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.66***
+
+**** Add error message when modules have duplicate names. [Stefan Thiede]
+
 * Verilator 3.661 2008/04/04
 
 ***  The --enable-defenv configure option added in 3.660 is now the default.
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index f850830d1..675061d0b 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -210,7 +210,11 @@ private:
     void readModNames() {
 	// Look at all modules, and store pointers to all module names
 	for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
-	    if (!m_mods.findIdName(nodep->name())) {
+	    AstNode* foundp = m_mods.findIdName(nodep->name());
+	    if (foundp && foundp != nodep) {
+		nodep->v3error("Duplicate declaration of module: "<<nodep->prettyName());
+		foundp->v3error("... Location of original declaration");
+	    } else if (!foundp) {
 		m_mods.insert(nodep->name(), nodep);
 	    }
 	}
diff --git a/test_regress/t/t_mod_dup_bad.pl b/test_regress/t/t_mod_dup_bad.pl
new file mode 100755
index 000000000..3803c9144
--- /dev/null
+++ b/test_regress/t/t_mod_dup_bad.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 fails=>$Last_Self->{v3},
+	 nc=>0,  # Need to get it not to give the prompt
+	 expect=>
+'%Error: t/t_mod_dup_bad.v:\d+: Duplicate declaration of module: a
+%Error: t/t_mod_dup_bad.v:\d+: ... Location of original declaration
+.*
+%Error: Exiting due to.*',
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;
diff --git a/test_regress/t/t_mod_dup_bad.v b/test_regress/t/t_mod_dup_bad.v
new file mode 100644
index 000000000..a139be462
--- /dev/null
+++ b/test_regress/t/t_mod_dup_bad.v
@@ -0,0 +1,18 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module a();
+endmodule
+
+module test();
+   a a();
+endmodule
+
+module a();
+endmodule
+
+module b();
+endmodule