diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp
index 05b0bdcd0..bb4353899 100644
--- a/src/V3Inline.cpp
+++ b/src/V3Inline.cpp
@@ -283,7 +283,7 @@ class InlineRelinkVisitor final : public VNVisitor {
// user2p is either a const or a var.
FileLine* const flp = nodep->fileline();
AstConst* const exprconstp = VN_CAST(nodep->user2p(), Const);
- const AstVarRef* const exprvarrefp = VN_CAST(nodep->user2p(), VarRef);
+ AstVarRef* exprvarrefp = VN_CAST(nodep->user2p(), VarRef);
UINFO(8, "connectto: " << nodep->user2p() << endl);
UASSERT_OBJ(exprconstp || exprvarrefp, nodep,
"Unknown interconnect type; pinReconnectSimple should have cleared up");
@@ -296,30 +296,32 @@ class InlineRelinkVisitor final : public VNVisitor {
// remove the change detection on the output variable.
UINFO(9, "public pin assign: " << exprvarrefp << endl);
UASSERT_OBJ(!nodep->isNonOutput(), nodep, "Outputs only - inputs use AssignAlias");
- m_modp->addStmtsp(
- new AstAssignW{flp, new AstVarRef{flp, exprvarrefp->varp(), VAccess::WRITE},
- new AstVarRef{flp, nodep, VAccess::READ}});
+ m_modp->addStmtsp(new AstAssignW{flp, exprvarrefp->cloneTree(false),
+ new AstVarRef{flp, nodep, VAccess::READ}});
} else if (nodep->isSigPublic() && VN_IS(nodep->dtypep(), UnpackArrayDType)) {
// Public variable at this end and it is an unpacked array. We need to assign
// instead of aliased, because otherwise it will pass V3Slice and invalid
// code will be emitted.
UINFO(9, "assign to public and unpacked: " << nodep << endl);
+ exprvarrefp = exprvarrefp->cloneTree(false);
+ exprvarrefp->access(VAccess::READ);
m_modp->addStmtsp(
- new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
- new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
+ new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp});
} else if (nodep->isIfaceRef()) {
- m_modp->addStmtsp(
- new AstAssignVarScope{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
- new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
+ exprvarrefp = exprvarrefp->cloneTree(false);
+ exprvarrefp->access(VAccess::READ);
+ m_modp->addStmtsp(new AstAssignVarScope{
+ flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp});
FileLine* const flbp = exprvarrefp->varp()->fileline();
flp->modifyStateInherit(flbp);
flbp->modifyStateInherit(flp);
} else {
// Do to inlining child's variable now within the same
// module, so a AstVarRef not AstVarXRef below
- m_modp->addStmtsp(
- new AstAssignAlias{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
- new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
+ exprvarrefp = exprvarrefp->cloneTree(false);
+ exprvarrefp->access(VAccess::READ);
+ m_modp->addStmtsp(new AstAssignAlias{
+ flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp});
FileLine* const flbp = exprvarrefp->varp()->fileline();
flp->modifyStateInherit(flbp);
flbp->modifyStateInherit(flp);
@@ -376,6 +378,7 @@ class InlineRelinkVisitor final : public VNVisitor {
return;
} else if (const AstVarRef* const vrefp = VN_CAST(varp->user2p(), VarRef)) {
nodep->varp(vrefp->varp());
+ nodep->classOrPackagep(vrefp->classOrPackagep());
} else {
nodep->v3fatalSrc("Null connection?");
}
diff --git a/test_regress/t/t_param_passed_to_port.pl b/test_regress/t/t_param_passed_to_port.pl
new file mode 100755
index 000000000..e191e87f4
--- /dev/null
+++ b/test_regress/t/t_param_passed_to_port.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile();
+
+execute(
+ check_finished => 1,
+ );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_passed_to_port.v b/test_regress/t/t_param_passed_to_port.v
new file mode 100644
index 000000000..7b1fb67d5
--- /dev/null
+++ b/test_regress/t/t_param_passed_to_port.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+parameter int HwDataAttr[1] = '{1};
+
+module flash_mp_data_region_sel (
+ input int region_attrs_i[1]
+);
+ initial begin
+ int o = 0;
+ for (int i = 0; i < 1; i++) begin
+ o = region_attrs_i[i];
+ end
+ if (o != 1) $stop;
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+endmodule
+
+module t;
+ flash_mp_data_region_sel u_hw_sel (.region_attrs_i(HwDataAttr));
+endmodule
diff --git a/test_regress/t/t_xml_flat.out b/test_regress/t/t_xml_flat.out
index e17361489..454eb60d2 100644
--- a/test_regress/t/t_xml_flat.out
+++ b/test_regress/t/t_xml_flat.out
@@ -64,15 +64,15 @@
-
+
-
+
-
+
@@ -87,15 +87,15 @@
-
+
-
+
-
+
diff --git a/test_regress/t/t_xml_flat_no_inline_mod.out b/test_regress/t/t_xml_flat_no_inline_mod.out
index d39485a05..da52f5e15 100644
--- a/test_regress/t/t_xml_flat_no_inline_mod.out
+++ b/test_regress/t/t_xml_flat_no_inline_mod.out
@@ -28,7 +28,7 @@
-
+
diff --git a/test_regress/t/t_xml_flat_pub_mod.out b/test_regress/t/t_xml_flat_pub_mod.out
index 6257a743a..55f3600d4 100644
--- a/test_regress/t/t_xml_flat_pub_mod.out
+++ b/test_regress/t/t_xml_flat_pub_mod.out
@@ -28,7 +28,7 @@
-
+