From ebe49552b0c8f29347debbe172d0018c133ccf53 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 24 Apr 2025 18:25:55 -0400
Subject: [PATCH] Fix packed selection using over 32-bit index (#5957).

---
 Changes                           |  1 +
 src/V3WidthSel.cpp                |  7 +++++-
 test_regress/t/t_bitsel_over32.py | 16 +++++++++++++
 test_regress/t/t_bitsel_over32.v  | 38 +++++++++++++++++++++++++++++++
 4 files changed, 61 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_bitsel_over32.py
 create mode 100644 test_regress/t/t_bitsel_over32.v

diff --git a/Changes b/Changes
index 327bb537a..e990be339 100644
--- a/Changes
+++ b/Changes
@@ -83,6 +83,7 @@ Verilator 5.035 devel
 * Fix port default values with `--coverage-line` creating `0=0` (#5920). [Drew Ranck]
 * Fix missing C++ regeneration when Verilog files are updated (#5934). [Zhouyi Shen]
 * Fix stream expressions (#5938). [Ryszard Rozak, Antmicro Ltd.]
+* Fix packed selection using over 32-bit index (#5957).
 
 
 Verilator 5.034 2025-02-24
diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp
index 88e0630fe..fbed8af3a 100644
--- a/src/V3WidthSel.cpp
+++ b/src/V3WidthSel.cpp
@@ -168,7 +168,12 @@ class WidthSelVisitor final : public VNVisitor {
         }
     }
     AstNodeExpr* newMulConst(FileLine* fl, uint32_t elwidth, AstNodeExpr* indexp) {
-        AstNodeExpr* const extendp = new AstExtend{fl, indexp};
+        AstNodeExpr* extendp;
+        if (indexp->width() > 32) {
+            extendp = new AstSel{fl, indexp, 0, 32};
+        } else {
+            extendp = new AstExtend{fl, indexp};
+        }
         extendp->dtypeSetLogicUnsized(
             32, std::max(V3Number::log2b(elwidth) + 1, indexp->widthMin()), VSigning::UNSIGNED);
         AstNodeExpr* const mulp
diff --git a/test_regress/t/t_bitsel_over32.py b/test_regress/t/t_bitsel_over32.py
new file mode 100755
index 000000000..46a3e3c1e
--- /dev/null
+++ b/test_regress/t/t_bitsel_over32.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--trace-vcd'])
+
+test.passes()
diff --git a/test_regress/t/t_bitsel_over32.v b/test_regress/t/t_bitsel_over32.v
new file mode 100644
index 000000000..0940bc915
--- /dev/null
+++ b/test_regress/t/t_bitsel_over32.v
@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(aw_addr, orig_aw_size);
+
+   typedef logic [63:0] addr_t;
+   typedef logic [7:0][7:0] mst_data_t;
+
+   logic [127:0] slv_req_i_w_data;
+   input addr_t aw_addr;
+   mst_data_t w_data;
+   input logic [2:0] orig_aw_size;
+
+   always_comb begin
+
+      // verilator lint_off WIDTHEXPAND
+      automatic addr_t mst_port_offset = aw_addr[2:0];
+      automatic addr_t slv_port_offset = aw_addr[3:0];
+
+      w_data = '0;
+
+      for (int b=0; b<16; b++) begin
+         if ((b >= slv_port_offset) &&
+             (b - slv_port_offset < (1 << orig_aw_size)) &&
+             (b + mst_port_offset - slv_port_offset < 8)) begin
+            automatic addr_t index = b + mst_port_offset - slv_port_offset;
+
+            // verilator lint_on WIDTHEXPAND
+            // [#][7:0] = [ +: 8]
+            w_data[index] = slv_req_i_w_data[8*b +: 8];
+
+         end
+      end
+   end
+endmodule