diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index afc7a238c..964910e38 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -67,7 +67,7 @@ private:
 	    timesp->unlinkFrBackWithNext();
 	    timenewp->addNext(timesp);
 	}
-	nodep->fmtp()->exprsp(timenewp);
+	nodep->fmtp()->addExprsp(timenewp);
 	if (!nodep->fmtp()->scopeNamep() && nodep->fmtp()->formatScopeTracking()) {
 	    nodep->fmtp()->scopeNamep(new AstScopeName(nodep->fileline()));
 	}
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 3909aa52f..be7fcb377 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -2397,7 +2397,7 @@ public:
     virtual bool hasDType() const { return true; }
     virtual bool same(AstNode* samep) const { return text()==samep->castSFormatF()->text(); }
     virtual string verilogKwd() const { return "$sformatf"; }
-    void exprsp(AstNode* nodep)	{ addOp1p(nodep); }	// op1 = Expressions to output
+    void addExprsp(AstNode* nodep) { addOp1p(nodep); }  // op1 = Expressions to output
     AstNode* exprsp() const { return op1p(); }	// op1 = Expressions to output
     string text() const { return m_text; }		// * = Text to display
     void text(const string& text) { m_text=text; }
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 39df8c73b..187ec6452 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -1943,6 +1943,8 @@ private:
             || !prevp->filep()->sameTree(nodep->filep())) return false;
         if (!prevp->fmtp() || prevp->fmtp()->nextp()
             || !nodep->fmtp() || nodep->fmtp()->nextp()) return false;
+        // We don't merge scopeNames as might be different scopes (late in process)
+        // We don't merge arguments as might need to later print warnings with right line numbers
         AstSFormatF* pformatp = prevp->fmtp();
         if (!pformatp || pformatp->exprsp() || pformatp->scopeNamep()) return false;
         AstSFormatF* nformatp = nodep->fmtp();
diff --git a/test_regress/t/t_display_merge.pl b/test_regress/t/t_display_merge.pl
index 39fa98e3f..6918a7df9 100755
--- a/test_regress/t/t_display_merge.pl
+++ b/test_regress/t/t_display_merge.pl
@@ -16,12 +16,28 @@ execute (
     expect=> (quotemeta(
 'Merge:
 This should merge
+f
+ a=top.t
+ b=top.t
+ pre
+ t=0
+ t2=0
+ post
+ t3=0
+ t4=0 t5=00000000000000000
+m
+ t=0 t2=0 t3=0 t4=0 t5=0
+ t=0 t2=0 t3=0 t4=0 t5=0
+mm
+
+f a=top.t b=top.t pre t=0 t2=0 post t3=0 t4=0 t5=00000000000000000m t=0 t2=0 t3=0 t4=0 t5=0 t=0 t2=0 t3=0 t4=0 t5=0mm
+
 *-* All Finished *-*')
 	      .'.*')
     );
 
 file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}__stats.txt",
-	   qr/Node count, DISPLAY \s+ 5 \s+ 1 \s+ 1 \s+ 1/);
+	   qr/Node count, DISPLAY \s+ 32 \s+ 25 \s+ 25 \s+ 25/);
 
 ok(1);
 1;
diff --git a/test_regress/t/t_display_merge.v b/test_regress/t/t_display_merge.v
index 2ab343756..c8e83b1d1 100644
--- a/test_regress/t/t_display_merge.v
+++ b/test_regress/t/t_display_merge.v
@@ -9,7 +9,37 @@ module t (/*AUTOARG*/);
       $write("This ");
       $write("should ");
       $display("merge");
-      $write("*-* All Finished *-*\n");
+
+      $display("f");
+      $display(" a=%m");
+      $display(" b=%m");
+      $display(" pre");
+      $display(" t=%0d",$time);
+      $display(" t2=%0d",$time);
+      $display(" post");
+      $display(" t3=%0d",$time);
+      $display(" t4=%0d t5=%0d",$time,$time,$time);
+      $display("m");
+      $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
+      $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
+      $display("mm");
+      $display("");
+
+      $write("f");
+      $write(" a=%m");
+      $write(" b=%m");
+      $write(" pre");
+      $write(" t=%0d",$time);
+      $write(" t2=%0d",$time);
+      $write(" post");
+      $write(" t3=%0d",$time);
+      $write(" t4=%0d t5=%0d",$time,$time,$time);
+      $write("m");
+      $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
+      $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
+      $display("mm");
+
+      $write("\n*-* All Finished *-*\n");
       $finish;
    end
 endmodule