diff --git a/Changes b/Changes
index 8f926736d..681ad4ffa 100644
--- a/Changes
+++ b/Changes
@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Add --clk and related optimizations, msg1533. [Jie Xu]
 
+***   Fix order of C style arrays. [Duraid Madina]
+
 ****  Add --dump-treei-<srcfile>, bug894. [Jie Xu]
 
 ****  Fix comma-instantiations with parameters, bug884. [Franck Jullien]
diff --git a/src/verilog.y b/src/verilog.y
index 6784aa1c5..a8c1c114a 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1464,7 +1464,7 @@ variable_dimension<rangep>:	// ==IEEE: variable_dimension
 	//UNSUP	'[' ']'					{ UNSUP }
 	//			// IEEE: unpacked_dimension
 		anyrange				{ $$ = $1; }
-	|	'[' constExpr ']'			{ $$ = new AstRange($1,new AstSub($1,$2, new AstConst($1,1)), new AstConst($1,0)); }
+	|	'[' constExpr ']'			{ $$ = new AstRange($1, new AstConst($1, 0), new AstSub($1, $2, new AstConst($1, 1))); }
 	//			// IEEE: associative_dimension
 	//UNSUP	'[' data_type ']'			{ UNSUP }
 	//UNSUP	yP_BRASTAR ']'				{ UNSUP }
diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v
index 128263f23..4da2ad524 100644
--- a/test_regress/t/t_mem.v
+++ b/test_regress/t/t_mem.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
    input clk;
    integer cyc; initial cyc=1;
 
-   // [16] is SV syntax for [15:0]
+   // [16] is SV syntax for [0:15]
    reg [7:0] memory8_16 [16];
 
    reg 	      m_we;
diff --git a/test_regress/t/t_unpacked_array_order.pl b/test_regress/t/t_unpacked_array_order.pl
new file mode 100755
index 000000000..814a9a3bb
--- /dev/null
+++ b/test_regress/t/t_unpacked_array_order.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+);
+
+execute (
+    check_finished=>1,
+);
+
+ok(1);
+1;
diff --git a/test_regress/t/t_unpacked_array_order.v b/test_regress/t/t_unpacked_array_order.v
new file mode 100644
index 000000000..ea1c67ad3
--- /dev/null
+++ b/test_regress/t/t_unpacked_array_order.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Duraid Madina.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   parameter logic [1:0] t0 [  2][  2] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}};
+   parameter logic [1:0] t1 [0:1][0:1] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}};
+   parameter logic [1:0] t2 [1:0][1:0] = '{'{2'd3, 2'd2}, '{2'd1, 2'd0}};
+
+   always @ (posedge clk) begin
+      if (t0[0][0] != t1[0][0]) $stop;
+      if (t0[0][1] != t1[0][1]) $stop;
+      if (t0[1][0] != t1[1][0]) $stop;
+      if (t0[1][1] != t1[1][1]) $stop;
+      if (t0[0][0] != t2[0][0]) $stop;
+      if (t0[0][1] != t2[0][1]) $stop;
+      if (t0[1][0] != t2[1][0]) $stop;
+      if (t0[1][1] != t2[1][1]) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule