diff --git a/Changes b/Changes
index a06c20b3f..0e3940bd5 100644
--- a/Changes
+++ b/Changes
@@ -29,6 +29,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix missing error on interface size mismatch, bug1143.  [Johan Bjork]
 
+****  Fix error on parameters with dotted references, bug1146. [Johan Bjork]
+
 
 * Verilator 3.900 2017-01-15
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 0ed8ebf94..020e109d9 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1184,7 +1184,14 @@ private:
     }
     virtual void visit(AstNodeVarRef* nodep) {
 	if (nodep->didWidth()) return;
-	if (!nodep->varp()) nodep->v3fatalSrc("Unlinked varref");
+	if (!nodep->varp()) {
+	    if (m_paramsOnly && nodep->castVarXRef()) {
+		checkConstantOrReplace(nodep, "Parameter-resolved constants must not use dotted references: "+nodep->prettyName()); VL_DANGLING(nodep);
+		return;
+	    } else {
+		nodep->v3fatalSrc("Unlinked varref");
+	    }
+	}
 	if (!nodep->varp()->didWidth()) {
 	    // Var hasn't been widthed, so make it so.
 	    userIterate(nodep->varp(), NULL);
diff --git a/test_regress/t/t_interface_param_another_bad.pl b/test_regress/t/t_interface_param_another_bad.pl
new file mode 100755
index 000000000..e0cefdebf
--- /dev/null
+++ b/test_regress/t/t_interface_param_another_bad.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	fails=>1,
+	expect=>
+q{%Error: t/t_interface_param_another_bad.v:\d+: Parameter-resolved constants must not use dotted references: dummy
+%Error: Exiting due to.*},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_param_another_bad.v b/test_regress/t/t_interface_param_another_bad.v
new file mode 100644
index 000000000..13a6fded5
--- /dev/null
+++ b/test_regress/t/t_interface_param_another_bad.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Johan Bjork.
+
+module t ();
+   simple_bus sb_intf();
+   simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple();
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+interface simple_bus #(PARAMETER = 0);
+   logic dummy;
+endinterface