From e8f596ed909f14240c6f0435771a5d2f6593e696 Mon Sep 17 00:00:00 2001
From: Kamil Danecki <kdanecki@internships.antmicro.com>
Date: Fri, 20 Mar 2026 14:33:08 +0100
Subject: [PATCH] Remove unsup test

Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
---
 test_regress/t/t_fork_dynscope_unsup.out | 10 ----------
 test_regress/t/t_fork_dynscope_unsup.py  | 16 ----------------
 test_regress/t/t_fork_dynscope_unsup.v   | 24 ------------------------
 3 files changed, 50 deletions(-)
 delete mode 100644 test_regress/t/t_fork_dynscope_unsup.out
 delete mode 100755 test_regress/t/t_fork_dynscope_unsup.py
 delete mode 100644 test_regress/t/t_fork_dynscope_unsup.v

diff --git a/test_regress/t/t_fork_dynscope_unsup.out b/test_regress/t/t_fork_dynscope_unsup.out
deleted file mode 100644
index c87c7fd3f..000000000
--- a/test_regress/t/t_fork_dynscope_unsup.out
+++ /dev/null
@@ -1,10 +0,0 @@
-%Error-UNSUPPORTED: t/t_fork_dynscope_unsup.v:17:7: Unsupported: Writing to a captured inout variable in a fork after a timing control
-                                                  : ... note: In instance 't'
-   17 |       p = #1 1;
-      |       ^
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_fork_dynscope_unsup.v:22:5: Unsupported: Writing to a captured output variable in a non-blocking assignment after a timing control
-                                                  : ... note: In instance 't'
-   22 |     q <= #1 1;
-      |     ^
-%Error: Exiting due to
diff --git a/test_regress/t/t_fork_dynscope_unsup.py b/test_regress/t/t_fork_dynscope_unsup.py
deleted file mode 100755
index 382ad0d44..000000000
--- a/test_regress/t/t_fork_dynscope_unsup.py
+++ /dev/null
@@ -1,16 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of either the GNU Lesser General Public License Version 3
-# or the Perl Artistic License Version 2.0.
-# SPDX-FileCopyrightText: 2024 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('simulator')
-
-test.lint(fails=True, expect_filename=test.golden_filename)
-
-test.passes()
diff --git a/test_regress/t/t_fork_dynscope_unsup.v b/test_regress/t/t_fork_dynscope_unsup.v
deleted file mode 100644
index 893c44a8b..000000000
--- a/test_regress/t/t_fork_dynscope_unsup.v
+++ /dev/null
@@ -1,24 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain
-// SPDX-FileCopyrightText: 2024 Antmicro
-// SPDX-License-Identifier: CC0-1.0
-
-module t;
-  bit p = 0, q = 0;
-
-  initial begin
-    t1(p);
-    t2(q);
-  end
-
-  task t1(inout p);
-    fork
-      p = #1 1;
-    join_none
-  endtask
-
-  task t2(output q);
-    q <= #1 1;
-  endtask
-endmodule