diff --git a/test_regress/t/t_net_delay.out b/test_regress/t/t_net_delay.out
index afade27cb..d812684ed 100644
--- a/test_regress/t/t_net_delay.out
+++ b/test_regress/t/t_net_delay.out
@@ -1,15 +1,15 @@
-%Warning-STMTDLY: t/t_net_delay.v:13:14: Ignoring delay on this statement due to --no-timing
+%Warning-STMTDLY: t/t_net_delay.v:15:14: Ignoring delay on this statement due to --no-timing
                                        : ... In instance t
-   13 |    wire[3:0] #4 val1 = cyc;
+   15 |    wire[3:0] #4 val1 = half_cyc;
       |              ^
                   ... For warning description see https://verilator.org/warn/STMTDLY?v=latest
                   ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
-%Warning-STMTDLY: t/t_net_delay.v:14:14: Ignoring delay on this statement due to --no-timing
+%Warning-STMTDLY: t/t_net_delay.v:16:14: Ignoring delay on this statement due to --no-timing
                                        : ... In instance t
-   14 |    wire[3:0] #4 val2;
+   16 |    wire[3:0] #4 val2;
       |              ^
-%Warning-ASSIGNDLY: t/t_net_delay.v:17:11: Ignoring timing control on this assignment/primitive due to --no-timing
+%Warning-ASSIGNDLY: t/t_net_delay.v:19:11: Ignoring timing control on this assignment/primitive due to --no-timing
                                          : ... In instance t
-   17 |    assign #4 val2 = cyc;
+   19 |    assign #4 val2 = half_cyc;
       |           ^
 %Error: Exiting due to
diff --git a/test_regress/t/t_net_delay.v b/test_regress/t/t_net_delay.v
index c9b524005..13fece4e5 100644
--- a/test_regress/t/t_net_delay.v
+++ b/test_regress/t/t_net_delay.v
@@ -4,25 +4,30 @@
 // any use, without warranty, 2022 by Antmicro Ltd.
 // SPDX-License-Identifier: CC0-1.0
 
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
+
 module t (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;
 
-   wire[3:0] #4 val1 = cyc;
+   wire[3:0] #4 val1 = half_cyc;
    wire[3:0] #4 val2;
-   reg[3:0] cyc = 0;
+   reg[3:0] half_cyc = 0;
 
-   assign #4 val2 = cyc;
+   assign #4 val2 = half_cyc;
 
-   always @(posedge clk) begin
-       cyc <= cyc + 1;
+   always @(clk) begin
+       if ($time > 0) half_cyc <= half_cyc + 1;
 `ifdef TEST_VERBOSE
-       $write("[%0t] cyc=%0d, val1=%0d, val2=%0d\n", $time, cyc, val1, val2);
+       $strobe("[%0t] half_cyc=%0d, val1=%0d, val2=%0d", $time, half_cyc, val1, val2);
 `endif
-       if (cyc >= 7 && val1 != cyc-1 && val2 != cyc-7) $stop;
-       if (cyc == 15) begin
+       if (half_cyc >= 7) begin
+          `checkh(val1, half_cyc - 3);
+          `checkh(val2, half_cyc - 7);
+       end
+       if (half_cyc == 15) begin
            $write("*-* All Finished *-*\n");
            $finish;
        end