diff --git a/Changes b/Changes
index b5732acdf..59fe2a096 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.65****
+
+**** Fix genvar to be signed, so "< 0" works properly.  [Niranjan Prabhu]
+
 * Verilator 3.658 2008/02/25
 
 **** Fix unistd compile error in 3.657.  [Patricio Kaplan, Jonathan Kimmitt]
diff --git a/src/verilog.y b/src/verilog.y
index adef6368c..703b045a5 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1403,7 +1403,10 @@ AstVar* V3Parse::createVariable(FileLine* fileline, string name, AstRange* array
 			       rangep->cloneTree(false),
 			       arrayp);
     nodep->isSigned(V3Parse::s_varSigned);
-    if (type == AstVarType::INTEGER || V3Parse::s_varDecl == AstVarType::INTEGER) nodep->isSigned(true);
+    if (type == AstVarType::INTEGER || V3Parse::s_varDecl == AstVarType::INTEGER
+	|| type == AstVarType::GENVAR) {
+	nodep->isSigned(true);
+    }
     if (V3Parse::s_varDecl != AstVarType::UNKNOWN) nodep->combineType(V3Parse::s_varDecl);
     if (V3Parse::s_varIO != AstVarType::UNKNOWN) nodep->combineType(V3Parse::s_varIO);
 
diff --git a/test_regress/t/t_gen_for1.pl b/test_regress/t/t_gen_for1.pl
new file mode 100755
index 000000000..7bfdbe852
--- /dev/null
+++ b/test_regress/t/t_gen_for1.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_for1.v b/test_regress/t/t_gen_for1.v
new file mode 100644
index 000000000..3543e1cd1
--- /dev/null
+++ b/test_regress/t/t_gen_for1.v
@@ -0,0 +1,85 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   wire  b;
+   reg 	 reset;
+   integer 	cyc=0;
+
+   Testit testit (/*AUTOINST*/
+		  // Outputs
+		  .b			(b),
+		  // Inputs
+		  .clk			(clk),
+		  .reset		(reset));
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==0) begin
+	 reset <= 1'b0;
+      end
+      else if (cyc<10) begin
+	 reset <= 1'b1;
+      end
+      else if (cyc<90) begin
+	 reset <= 1'b0;
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Testit (clk, reset, b);
+   input                  clk;
+   input 		  reset;
+   output 		  b;
+
+   wire [0:0] 		  c;
+   wire 		  my_sig;
+   wire [0:0] 		  d;
+
+   genvar 		     i;
+   generate
+      for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
+	 fnxtclk fnxtclk1
+	   (.u(c[i]),
+	    .reset(reset),
+	    .clk(clk),
+	    .w(d[i]) );
+      end
+   endgenerate
+
+   assign b                    = d[0];
+   assign c[0]                 = my_sig;
+   assign my_sig               = 1'b1;
+
+endmodule 
+
+module fnxtclk (u, reset, clk, w );
+   input                    u;
+   input 		    reset;
+   input 		    clk;
+   output reg 		    w;
+
+   always @ (posedge clk or posedge reset) begin
+      if (reset == 1'b1) begin
+         w            <= 1'b0;
+      end
+      else begin
+         w            <= u;
+      end
+   end 
+
+endmodule 
+