diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index c75d21f3a..3024d07f0 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -1,9 +1,9 @@
 .. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-=====================
- verilator Arguments
-=====================
+===================
+verilator Arguments
+===================
 
 The following arguments may be passed to the "verilator" executable.
 
@@ -1774,7 +1774,7 @@ Summary:
    them systematically.
 
    The generated file is in the Verilator Configuration format, see
-   :ref:`Configuration Files`. The standard file extension is ".vlt".
+   :ref:`Verilator Configuration Files`. The standard file extension is ".vlt".
    These files can directly be consumed by Verilator, typically by placing
    the filename as part of the Verilator command line options. Waiver files
    need to be listed on the command line before listing the files they are
@@ -2015,18 +2015,20 @@ Summary:
    filenames.
 
 
-.. _Configuration Files:
+.. _Verilator Configuration Files:
 
-=====================
- Configuration Files
-=====================
+=============================
+Verilator Configuration Files
+=============================
 
 In addition to the command line, warnings and other features for the
-:command:`verilator` command may be controlled with configuration files,
-typically named with the `.vlt` extension (what makes it a configuration
-file is the :option:`\`verilator_config` directive).  These files, when
-named `.vlt`, are read before source code files; if this behavior is
-undesired, name the config file with a `.v` suffix.
+:command:`verilator` command may be controlled with Verilator Configuration
+Files, not to be confused with IEEE Configurations blocks
+(`config...endconfig`) inside a file.  Typically named with the `.vlt`
+extension, what makes it a Verilator Configuration File is the
+:option:`\`verilator_config` directive.  These files, when named `.vlt`,
+are read before source code files; if this behavior is undesired, name the
+config file with a `.v` suffix.
 
 An example:
 
@@ -2038,9 +2040,9 @@ An example:
 
 This disables WIDTH warnings globally, and CASEX for a specific file.
 
-Configuration files are fed through the normal Verilog preprocessor prior
-to parsing, so "\`ifdef", "\`define", and comments may be used as if the
-configuration file was standard Verilog code.
+Verilator configuration files are fed through the normal Verilog
+preprocessor prior to parsing, so "\`ifdef", "\`define", and comments may
+be used as if the configuration file was standard Verilog code.
 
 Note that file or line-specific configuration only applies to files read
 after the configuration file. It is therefore recommended to pass the
diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst
index b01c28f91..1d54ca0b2 100644
--- a/docs/guide/extensions.rst
+++ b/docs/guide/extensions.rst
@@ -30,7 +30,7 @@ or "`ifdef`"'s may break other tools.
 
    Specifies the entire begin/end block should be ignored for coverage
    analysis.  Must be inside a code block, e.g., within a begin/end pair.
-   Same as :option:`coverage_block_off` in :ref:`Configuration Files`.
+   Same as :option:`coverage_block_off` in :ref:`Verilator Configuration Files`.
 
 .. option:: `error [string]
 
@@ -135,8 +135,9 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: `verilator_config
 
-   Take the remaining text up to the next :option:`\`verilog` mode switch and
-   treat it as Verilator configuration commands.  See :ref:`Configuration Files`.
+   Take the remaining text up to the next :option:`\`verilog` mode switch
+   and treat it as Verilator configuration commands.  See :ref:`Verilator
+   Configuration Files`.
 
 .. option:: `VERILATOR_TIMING
 
diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst
index a13c11184..f21a2666b 100644
--- a/docs/guide/languages.rst
+++ b/docs/guide/languages.rst
@@ -6,7 +6,7 @@ Input Languages
 ***************
 
 This section describes the languages Verilator takes as input.  See also
-:ref:`Configuration Files`.
+:ref:`Verilator Configuration Files`.
 
 
 Language Standard Support
diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst
index 058caa52f..9b0d3f15b 100644
--- a/docs/guide/verilating.rst
+++ b/docs/guide/verilating.rst
@@ -94,7 +94,7 @@ There are two ways to mark a module:
 
 * Write :option:`/*verilator&32;hier_block*/` metacomment in HDL code.
 
-* Add a :option:`hier_block` line in the :ref:`Configuration Files`.
+* Add a :option:`hier_block` line in the :ref:`Verilator Configuration Files`.
 
 Then pass the :vlopt:`--hierarchical` option to Verilator.
 
diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst
index 0a97c30e1..bafd1827f 100644
--- a/docs/guide/warnings.rst
+++ b/docs/guide/warnings.rst
@@ -37,7 +37,7 @@ Warnings may be disabled in multiple ways:
    propagate upwards to any parent file (file that included the file with
    the lint_off).
 
-#. Disable the warning using :ref:`Configuration Files` with a
+#. Disable the warning using :ref:`Verilator Configuration Files` with a
    :option:`lint_off` command.  This is useful when a script suppresses
    warnings, and the Verilog source should not be changed.  This method also
    allows matching on the warning text.