diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 1c610de57..8a38c03a0 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -4769,7 +4769,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } else { nodep->v3warn(E_UNSUPPORTED, "Unsupported: " << foundp->nodep()->prettyTypeName() - << " in AstClassExtends"); + << " in 'class extends'"); return; } } else { diff --git a/test_regress/t/t_class_extends_alias.out b/test_regress/t/t_class_extends_alias.out new file mode 100644 index 000000000..f668ed890 --- /dev/null +++ b/test_regress/t/t_class_extends_alias.out @@ -0,0 +1,5 @@ +%Error-UNSUPPORTED: t/t_class_extends_alias.v:24:21: Unsupported: TYPEDEF 'foo_t' in 'class extends' + 24 | class bar extends foo_t; + | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_class_extends_alias_unsup.py b/test_regress/t/t_class_extends_alias.py similarity index 100% rename from test_regress/t/t_class_extends_alias_unsup.py rename to test_regress/t/t_class_extends_alias.py diff --git a/test_regress/t/t_class_extends_alias.v b/test_regress/t/t_class_extends_alias.v new file mode 100644 index 000000000..2e0ec59fe --- /dev/null +++ b/test_regress/t/t_class_extends_alias.v @@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +package pkg; +endpackage + +module t; + + class foo; + int x = 1; + function int get_x; + return x; + endfunction + function int get_3; + return 3; + endfunction + endclass + + typedef foo foo_t; + + class bar extends foo_t; + endclass + + bar bar_foo_t_i; + + initial begin + bar_foo_t_i = new; + if (bar_foo_t_i.get_x() == 1 && bar_foo_t_i.get_3() == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + +endmodule diff --git a/test_regress/t/t_class_extends_alias_unsup.out b/test_regress/t/t_class_extends_alias_unsup.out deleted file mode 100644 index ff50572f7..000000000 --- a/test_regress/t/t_class_extends_alias_unsup.out +++ /dev/null @@ -1,5 +0,0 @@ -%Error-UNSUPPORTED: t/t_class_extends_alias_unsup.v:22:22: Unsupported: TYPEDEF 'foo_t' in AstClassExtends - 22 | class bar extends foo_t; - | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Exiting due to diff --git a/test_regress/t/t_class_extends_alias_unsup.v b/test_regress/t/t_class_extends_alias_unsup.v deleted file mode 100644 index a0a8f7197..000000000 --- a/test_regress/t/t_class_extends_alias_unsup.v +++ /dev/null @@ -1,38 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - ); - - class foo; - int x = 1; - function int get_x; - return x; - endfunction - function int get_3; - return 3; - endfunction - endclass - - typedef foo foo_t; - - class bar extends foo_t; - endclass - - - bar bar_foo_t_i; - - initial begin - bar_foo_t_i = new; - if (bar_foo_t_i.get_x() == 1 && bar_foo_t_i.get_3() == 3) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end - end -endmodule diff --git a/test_regress/t/t_class_extends_pkg_bad.out b/test_regress/t/t_class_extends_pkg_bad.out new file mode 100644 index 000000000..248615fd6 --- /dev/null +++ b/test_regress/t/t_class_extends_pkg_bad.out @@ -0,0 +1,5 @@ +%Error-UNSUPPORTED: t/t_class_extends_pkg_bad.v:22:21: Unsupported: PACKAGE 'pkg' in 'class extends' + 22 | class bar extends pkg; + | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_class_extends_pkg_bad.py b/test_regress/t/t_class_extends_pkg_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_pkg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_pkg_bad.v b/test_regress/t/t_class_extends_pkg_bad.v new file mode 100644 index 000000000..8939067b3 --- /dev/null +++ b/test_regress/t/t_class_extends_pkg_bad.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +package pkg; +endpackage + +module t; + + class foo; + int x = 1; + function int get_x; + return x; + endfunction + function int get_3; + return 3; + endfunction + endclass + + class bar extends pkg; + endclass + + + bar bar_foo_t_i; + + initial begin + bar_foo_t_i = new; + if (bar_foo_t_i.get_x() == 1 && bar_foo_t_i.get_3() == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end +endmodule