diff --git a/test_regress/t/t_array_packed_literals.v b/test_regress/t/t_array_packed_literals.v deleted file mode 100644 index fa3028327..000000000 --- a/test_regress/t/t_array_packed_literals.v +++ /dev/null @@ -1,119 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Iztok Jeras. - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - // parameters for array sizes - localparam WA = 4; // address dimension size - localparam WB = 4; // bit dimension size - - localparam NO = 10; // number of access events - - // 2D packed arrays - logic [WA-1:0] [WB-1:0] array_bg; // big endian array - /* verilator lint_off LITENDIAN */ - logic [0:WA-1] [0:WB-1] array_lt; // little endian array - /* verilator lint_on LITENDIAN */ - - integer cnt = 0; - - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin - $write("*-* All Finished *-*\n"); - $finish; - end - - // big endian - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaults (all bits 1'bx) - if (cnt[30:2]==0) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }}; - end else if (cnt[1:0]==2'd1) begin - // write data into whole or part of the array using literals - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_bg = '{ 3 ,2 ,1, 0 }; - else if (cnt[30:2]==2) array_bg = '{0:4, 1:5, 2:6, 3:7}; - else if (cnt[30:2]==3) array_bg = '{default:13}; - else if (cnt[30:2]==4) array_bg = '{2:15, default:13}; - else if (cnt[30:2]==5) array_bg = '{WA { {WB/2 {2'b10}} }}; - else if (cnt[30:2]==6) array_bg = '{WA { {3'b101, {WB/2-1{2'b10}}} }}; - else if (cnt[30:2]==7) array_bg = '{WA { {WB/2-1{2'b10}} }}; - else if (cnt[30:2]==8) array_bg [WA/2-1:0 ] = '{WA/2{ {WB/2 {2'b10}} }}; - else if (cnt[30:2]==9) array_bg [WA -1:WA/2] = '{WA/2{ {WB/2 {2'b01}} }}; - end else if (cnt[1:0]==2'd2) begin - // chack array agains expected value - if (cnt[30:2]==0) begin if (array_bg !== 16'bxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==2) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==3) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==6) begin if (array_bg !== 16'b0110011001100110) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==7) begin if (array_bg !== 16'b0010001000100010) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==8) begin if (array_bg !== 16'b10101010xxxxxxxx) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==9) begin if (array_bg !== 16'bxxxxxxxx10101010) begin $display("%b", array_bg); $stop(); end end - end - - // little endian - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaults (all bits 1'bx) - if (cnt[30:2]==0) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }}; - end else if (cnt[1:0]==2'd1) begin - // write data into whole or part of the array using literals - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_lt = '{ 3 ,2 ,1, 0 }; - else if (cnt[30:2]==2) array_lt = '{3:4, 2:5, 1:6, 0:7}; - else if (cnt[30:2]==3) array_lt = '{default:13}; - else if (cnt[30:2]==4) array_lt = '{1:15, default:13}; - else if (cnt[30:2]==5) array_lt = '{WA { {WB/2 {2'b10}} }}; - else if (cnt[30:2]==6) array_lt = '{WA { {3'b101, {WB/2-1{2'b10}}} }}; - else if (cnt[30:2]==7) array_lt = '{WA { {WB/2-1{2'b10}} }}; - else if (cnt[30:2]==8) array_lt [0 :WA/2-1] = '{WA/2{ {WB/2 {2'b10}} }}; - else if (cnt[30:2]==9) array_lt [WA/2:WA -1] = '{WA/2{ {WB/2 {2'b01}} }}; - end else if (cnt[1:0]==2'd2) begin - // chack array agains expected value - if (cnt[30:2]==0) begin if (array_lt !== 16'bxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==2) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==3) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==6) begin if (array_lt !== 16'b0110011001100110) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==7) begin if (array_lt !== 16'b0010001000100010) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==8) begin if (array_lt !== 16'b10101010xxxxxxxx) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==9) begin if (array_lt !== 16'bxxxxxxxx10101010) begin $display("%b", array_lt); $stop(); end end - end - -endmodule diff --git a/test_regress/t/t_array_packed_methods.v b/test_regress/t/t_array_packed_methods.v deleted file mode 100644 index 3cfb77617..000000000 --- a/test_regress/t/t_array_packed_methods.v +++ /dev/null @@ -1,143 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - // parameters for array sizes - localparam WA = 4; - localparam WB = 6; - localparam WC = 8; - - // 2D packed arrays - logic [WA-1:0] [WB-1:0] [WC-1:0] array_bg; // big endian array - /* verilator lint_off LITENDIAN */ - logic [0:WA-1] [0:WB-1] [0:WC-1] array_lt; // little endian array - /* verilator lint_on LITENDIAN */ - - integer cnt = 0; - integer slc = 0; // slice type - integer dim = 0; // dimension - integer wdt = 0; // width - - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin - $write("*-* All Finished *-*\n"); - $finish; - end - - // calculation of dimention sizes - always @ (posedge clk) - begin - // slicing tipe counter - case (cnt[3:2]) - 2'd0 : begin slc = 0; end // full array - 2'd1 : begin slc = 1; end // half array - 2'd2 : begin slc = 2; end // single array element - default: begin slc = 0; end - endcase - // dimmension counter - case (cnt[1:0]) - 2'd0 : begin dim = 1; wdt = (slc==1) ? WA/2 - : (slc==2) ? 1 - : WA; end - 2'd1 : begin dim = 2; wdt = WB; end - 2'd2 : begin dim = 3; wdt = WC; end - default: begin dim = 0; wdt = 0; end - endcase - end - - always @ (posedge clk) - if (cnt[30:4]==1) begin - // big endian - if (cnt[3:2]==0) begin - // full array - if ($dimensions (array_bg) != 3) $stop; - if ($bits (array_bg) != WA*WB*WC) $stop; - if ((dim>=1)&&(dim<=3)) begin - if ($left (array_bg, dim) != wdt-1) $stop; - if ($right (array_bg, dim) != 0 ) $stop; - if ($low (array_bg, dim) != 0 ) $stop; - if ($high (array_bg, dim) != wdt-1) $stop; - if ($increment (array_bg, dim) != 1 ) $stop; - if ($size (array_bg, dim) != wdt ) $stop; - end - end else if (cnt[3:2]==1) begin - // half array - if ($dimensions (array_bg[WA/2-1:0]) != 3) $stop; - if ($bits (array_bg[WA/2-1:0]) != WA/2*WB*WC) $stop; - if ((dim>=1)&&(dim<=3)) begin - if ($left (array_bg[WA/2-1:0], dim) != wdt-1) $stop; - if ($right (array_bg[WA/2-1:0], dim) != 0 ) $stop; - if ($low (array_bg[WA/2-1:0], dim) != 0 ) $stop; - if ($high (array_bg[WA/2-1:0], dim) != wdt-1) $stop; - if ($increment (array_bg[WA/2-1:0], dim) != 1 ) $stop; - if ($size (array_bg[WA/2-1:0], dim) != wdt ) $stop; - end - end else if (cnt[3:2]==2) begin - // single array element - if ($dimensions (array_bg[0]) != 2) $stop; - if ($bits (array_bg[0]) != WB*WC) $stop; - if ((dim>=2)&&(dim<=3)) begin - if ($left (array_bg[0], dim-1) != wdt-1) $stop; - if ($right (array_bg[0], dim-1) != 0 ) $stop; - if ($low (array_bg[0], dim-1) != 0 ) $stop; - if ($high (array_bg[0], dim-1) != wdt-1) $stop; - if ($increment (array_bg[0], dim-1) != 1 ) $stop; - if ($size (array_bg[0], dim-1) != wdt ) $stop; - end - end - end else if (cnt[30:4]==2) begin - // little endian - if (cnt[3:2]==0) begin - // full array - if ($dimensions (array_lt) != 3) $stop; - if ($bits (array_lt) != WA*WB*WC) $stop; - if ((dim>=1)&&(dim<=3)) begin - if ($left (array_lt, dim) != 0 ) $stop; - if ($right (array_lt, dim) != wdt-1) $stop; - if ($low (array_lt, dim) != 0 ) $stop; - if ($high (array_lt, dim) != wdt-1) $stop; - if ($increment (array_lt, dim) != -1 ) $stop; - if ($size (array_lt, dim) != wdt ) $stop; - end - end else if (cnt[3:2]==1) begin - // half array - if ($dimensions (array_lt[0:WA/2-1]) != 3) $stop; - if ($bits (array_lt[0:WA/2-1]) != WA/2*WB*WC) $stop; - if ((dim>=1)&&(dim<=3)) begin - if ($left (array_lt[0:WA/2-1], dim) != 0 ) $stop; - if ($right (array_lt[0:WA/2-1], dim) != wdt-1) $stop; - if ($low (array_lt[0:WA/2-1], dim) != 0 ) $stop; - if ($high (array_lt[0:WA/2-1], dim) != wdt-1) $stop; - if ($increment (array_lt[0:WA/2-1], dim) != -1 ) $stop; - if ($size (array_lt[0:WA/2-1], dim) != wdt ) $stop; - end - end else if (cnt[3:2]==2) begin - // single array element - if ($dimensions (array_lt[0]) != 2) $stop; - if ($bits (array_lt[0]) != WB*WC) $stop; - if ((dim>=2)&&(dim<=3)) begin - if ($left (array_lt[0], dim-1) != 0 ) $stop; - if ($right (array_lt[0], dim-1) != wdt-1) $stop; - if ($low (array_lt[0], dim-1) != 0 ) $stop; - if ($high (array_lt[0], dim-1) != wdt-1) $stop; - if ($increment (array_lt[0], dim-1) != -1 ) $stop; - if ($size (array_lt[0], dim-1) != wdt ) $stop; - end - end - end - -endmodule diff --git a/test_regress/t/t_array_packed_methods.pl b/test_regress/t/t_array_packed_sysfunct.pl similarity index 100% rename from test_regress/t/t_array_packed_methods.pl rename to test_regress/t/t_array_packed_sysfunct.pl diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v new file mode 100644 index 000000000..28010613c --- /dev/null +++ b/test_regress/t/t_array_packed_sysfunct.v @@ -0,0 +1,141 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // parameters for array sizes + localparam WA = 4; + localparam WB = 6; + localparam WC = 8; + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] [WC-1:0] array_bg; // big endian array + /* verilator lint_off LITENDIAN */ + logic [0:WA-1] [0:WB-1] [0:WC-1] array_lt; // little endian array + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + integer slc = 0; // slice type + integer dim = 0; // dimension + integer wdt = 0; // width + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // calculation of dimention sizes + always @ (posedge clk) + begin + // slicing tipe counter + case (cnt[3:2]) + 2'd0 : begin slc <= 0; end // full array + 2'd1 : begin slc <= 1; end // half array + 2'd2 : begin slc <= 2; end // single array element + default: begin slc <= 0; end + endcase + // dimmension counter + case (cnt[1:0]) + 2'd0 : begin dim <= 1; wdt = (slc==1) ? WA/2 : (slc==2) ? 1 : WA; end + 2'd1 : begin dim <= 2; wdt = WB; end + 2'd2 : begin dim <= 3; wdt = WC; end + default: begin dim <= 0; wdt = 0; end + endcase + end + + always @ (posedge clk) + if (cnt[30:4]==1) begin + // big endian + if (cnt[3:2]==0) begin + // full array + if ($dimensions (array_bg) != 3) $stop; + if ($bits (array_bg) != WA*WB*WC) $stop; + if ((dim>=1)&&(dim<=3)) begin + if ($left (array_bg, dim) != wdt-1) $stop; + if ($right (array_bg, dim) != 0 ) $stop; + if ($low (array_bg, dim) != 0 ) $stop; + if ($high (array_bg, dim) != wdt-1) $stop; + if ($increment (array_bg, dim) != 1 ) $stop; + if ($size (array_bg, dim) != wdt ) $stop; + end + end else if (cnt[3:2]==1) begin + // half array + if ($dimensions (array_bg[WA/2-1:0]) != 3) $stop; + if ($bits (array_bg[WA/2-1:0]) != WA/2*WB*WC) $stop; + if ((dim>=1)&&(dim<=3)) begin + if ($left (array_bg[WA/2-1:0], dim) != wdt-1) $stop; + if ($right (array_bg[WA/2-1:0], dim) != 0 ) $stop; + if ($low (array_bg[WA/2-1:0], dim) != 0 ) $stop; + if ($high (array_bg[WA/2-1:0], dim) != wdt-1) $stop; + if ($increment (array_bg[WA/2-1:0], dim) != 1 ) $stop; + if ($size (array_bg[WA/2-1:0], dim) != wdt ) $stop; + end + end else if (cnt[3:2]==2) begin + // single array element + if ($dimensions (array_bg[0]) != 2) $stop; + if ($bits (array_bg[0]) != WB*WC) $stop; + if ((dim>=2)&&(dim<=3)) begin + if ($left (array_bg[0], dim-1) != wdt-1) $stop; + if ($right (array_bg[0], dim-1) != 0 ) $stop; + if ($low (array_bg[0], dim-1) != 0 ) $stop; + if ($high (array_bg[0], dim-1) != wdt-1) $stop; + if ($increment (array_bg[0], dim-1) != 1 ) $stop; + if ($size (array_bg[0], dim-1) != wdt ) $stop; + end + end + end else if (cnt[30:4]==2) begin + // little endian + if (cnt[3:2]==0) begin + // full array + if ($dimensions (array_lt) != 3) $stop; + if ($bits (array_lt) != WA*WB*WC) $stop; + if ((dim>=1)&&(dim<=3)) begin + if ($left (array_lt, dim) != 0 ) $stop; + if ($right (array_lt, dim) != wdt-1) $stop; + if ($low (array_lt, dim) != 0 ) $stop; + if ($high (array_lt, dim) != wdt-1) $stop; + if ($increment (array_lt, dim) != -1 ) $stop; + if ($size (array_lt, dim) != wdt ) $stop; + end + end else if (cnt[3:2]==1) begin + // half array + if ($dimensions (array_lt[0:WA/2-1]) != 3) $stop; + if ($bits (array_lt[0:WA/2-1]) != WA/2*WB*WC) $stop; + if ((dim>=1)&&(dim<=3)) begin + if ($left (array_lt[0:WA/2-1], dim) != 0 ) $stop; + if ($right (array_lt[0:WA/2-1], dim) != wdt-1) $stop; + if ($low (array_lt[0:WA/2-1], dim) != 0 ) $stop; + if ($high (array_lt[0:WA/2-1], dim) != wdt-1) $stop; + if ($increment (array_lt[0:WA/2-1], dim) != -1 ) $stop; + if ($size (array_lt[0:WA/2-1], dim) != wdt ) $stop; + end + end else if (cnt[3:2]==2) begin + // single array element + if ($dimensions (array_lt[0]) != 2) $stop; + if ($bits (array_lt[0]) != WB*WC) $stop; + if ((dim>=2)&&(dim<=3)) begin + if ($left (array_lt[0], dim-1) != 0 ) $stop; + if ($right (array_lt[0], dim-1) != wdt-1) $stop; + if ($low (array_lt[0], dim-1) != 0 ) $stop; + if ($high (array_lt[0], dim-1) != wdt-1) $stop; + if ($increment (array_lt[0], dim-1) != -1 ) $stop; + if ($size (array_lt[0], dim-1) != wdt ) $stop; + end + end + end + +endmodule diff --git a/test_regress/t/t_array_packed_literals.pl b/test_regress/t/t_array_packed_value_list.pl similarity index 100% rename from test_regress/t/t_array_packed_literals.pl rename to test_regress/t/t_array_packed_value_list.pl diff --git a/test_regress/t/t_array_packed_value_list.v b/test_regress/t/t_array_packed_value_list.v new file mode 100644 index 000000000..1561c2cce --- /dev/null +++ b/test_regress/t/t_array_packed_value_list.v @@ -0,0 +1,125 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // parameters for array sizes + localparam WA = 4; // address dimension size + localparam WB = 4; // bit dimension size + + localparam NO = 11; // number of access events + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] array_bg; // big endian array + /* verilator lint_off LITENDIAN */ + logic [0:WA-1] [0:WB-1] array_lt; // little endian array + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'bx) + if (cnt[30:2]== 0) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 1) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 2) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 3) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 4) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 5) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 6) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 7) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 8) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 9) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==10) array_bg <= {WA{ {WB{1'bx}} }}; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]== 0) begin end + else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_bg <= '{0:4, 1:5, 2:6, 3:7}; + else if (cnt[30:2]== 3) array_bg <= '{default:13}; + else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13}; + else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]== 6) array_bg <= '{WA { {3'b101, {WB/2-1{2'b10}}} }}; + else if (cnt[30:2]== 7) array_bg <= '{WA { {WB/2-1{2'b10}} }}; + else if (cnt[30:2]== 8) array_bg [WA/2-1:0 ] <= '{WA/2{ {WB/2 {2'b10}} }}; + else if (cnt[30:2]== 9) array_bg [WA -1:WA/2] <= '{WA/2{ {WB/2 {2'b01}} }}; + else if (cnt[30:2]==10) array_bg <= '{cnt+0, cnt+1, cnt+2, cnt+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]== 0) begin if (array_bg !== 16'bxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 6) begin if (array_bg !== 16'b0110011001100110) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 7) begin if (array_bg !== 16'b0010001000100010) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 8) begin if (array_bg !== 16'b10101010xxxxxxxx) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 9) begin if (array_bg !== 16'bxxxxxxxx10101010) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==10) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'bx) + if (cnt[30:2]== 0) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 1) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 2) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 3) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 4) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 5) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 6) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 7) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 8) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]== 9) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==10) array_lt <= {WA{ {WB{1'bx}} }}; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]== 0) begin end + else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_lt <= '{3:4, 2:5, 1:6, 0:7}; + else if (cnt[30:2]== 3) array_lt <= '{default:13}; + else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13}; + else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]== 6) array_lt <= '{WA { {3'b101, {WB/2-1{2'b10}}} }}; + else if (cnt[30:2]== 7) array_lt <= '{WA { {WB/2-1{2'b10}} }}; + else if (cnt[30:2]== 8) array_lt [0 :WA/2-1] <= '{WA/2{ {WB/2 {2'b10}} }}; + else if (cnt[30:2]== 9) array_lt [WA/2:WA -1] <= '{WA/2{ {WB/2 {2'b01}} }}; + else if (cnt[30:2]==10) array_lt <= '{cnt+0, cnt+1, cnt+2, cnt+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]== 0) begin if (array_lt !== 16'bxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 6) begin if (array_lt !== 16'b0110011001100110) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 7) begin if (array_lt !== 16'b0010001000100010) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 8) begin if (array_lt !== 16'b10101010xxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 9) begin if (array_lt !== 16'bxxxxxxxx10101010) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end + end + +endmodule diff --git a/test_regress/t/t_array_packed_write_read.v b/test_regress/t/t_array_packed_write_read.v index 93173b38a..c41edf9fa 100644 --- a/test_regress/t/t_array_packed_write_read.v +++ b/test_regress/t/t_array_packed_write_read.v @@ -17,9 +17,9 @@ module t (/*AUTOARG*/ localparam NO = 10; // number of access events // 2D packed arrays - logic [WA-1:0] [WB-1:0] array_bg; // big endian array + logic [WA-1:0] [WB-1:0] array_bg; // big endian array /* verilator lint_off LITENDIAN */ - logic [0:WA-1] [0:WB-1] array_lt; // little endian array + logic [0:WA-1] [0:WB-1] array_lt; // little endian array /* verilator lint_on LITENDIAN */ integer cnt = 0; @@ -31,113 +31,113 @@ module t (/*AUTOARG*/ // finish report always @ (posedge clk) - if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end // big endian always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaaults (all bits to x) - if (cnt[30:2]==0) array_bg <= {WA *WB{1'bx} }; - else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }}; - end else if (cnt[1:0]==2'd1) begin - // write value to array - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_bg = {WA *WB +0{1'b1}}; - else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] = {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==3) array_bg [WA -1:WA/2] = {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==4) array_bg [ 0 ] = {1 *WB +0{1'b1}}; - else if (cnt[30:2]==5) array_bg [WA -1 ] = {1 *WB +0{1'b1}}; - else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] = {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] = {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] = {1 *1 +0{1'b1}}; - else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] = {1 *1 +0{1'b1}}; - end else if (cnt[1:0]==2'd2) begin - // check array value - if (cnt[30:2]==0) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) $stop(); end - else if (cnt[30:2]==2) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) $stop(); end - else if (cnt[30:2]==3) begin if (array_bg !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==4) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) $stop(); end - else if (cnt[30:2]==5) begin if (array_bg !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==6) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) $stop(); end - else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==8) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) $stop(); end - else if (cnt[30:2]==9) begin if (array_bg !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - end else if (cnt[1:0]==2'd3) begin - // read value from array (not a very good test for now) - if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'bx}}) $stop(); end - else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end - else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end - end + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to x) + if (cnt[30:2]==0) array_bg <= {WA *WB{1'bx} }; + else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }}; + end else if (cnt[1:0]==2'd1) begin + // write value to array + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) array_bg <= {WA *WB +0{1'b1}}; + else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==3) array_bg [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==4) array_bg [ 0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==5) array_bg [WA -1 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; + end else if (cnt[1:0]==2'd2) begin + // check array value + if (cnt[30:2]==0) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==2) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==3) begin if (array_bg !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==4) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==5) begin if (array_bg !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==6) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==8) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==9) begin if (array_bg !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end + end else if (cnt[1:0]==2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'bx}}) $stop(); end + else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end + end // little endian always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaaults (all bits to x) - if (cnt[30:2]==0) array_lt <= {WA *WB{1'bx} }; - else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }}; - else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }}; - end else if (cnt[1:0]==2'd1) begin - // write value to array - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_lt = {WA *WB +0{1'b1}}; - else if (cnt[30:2]==2) array_lt [0 :WA/2-1] = {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==3) array_lt [WA/2:WA -1] = {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==4) array_lt [0 ] = {1 *WB +0{1'b1}}; - else if (cnt[30:2]==5) array_lt [ WA -1] = {1 *WB +0{1'b1}}; - else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] = {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] = {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==8) array_lt [0 ][0 ] = {1 *1 +0{1'b1}}; - else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] = {1 *1 +0{1'b1}}; - end else if (cnt[1:0]==2'd2) begin - // check array value - if (cnt[30:2]==0) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) $stop(); end - else if (cnt[30:2]==2) begin if (array_lt !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==3) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) $stop(); end - else if (cnt[30:2]==4) begin if (array_lt !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==5) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) $stop(); end - else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==7) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) $stop(); end - else if (cnt[30:2]==8) begin if (array_lt !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end - else if (cnt[30:2]==9) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) $stop(); end - end else if (cnt[1:0]==2'd3) begin - // read value from array (not a very good test for now) - if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'bx}}) $stop(); end - else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end - else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end - end + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to x) + if (cnt[30:2]==0) array_lt <= {WA *WB{1'bx} }; + else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }}; + else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }}; + end else if (cnt[1:0]==2'd1) begin + // write value to array + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) array_lt <= {WA *WB +0{1'b1}}; + else if (cnt[30:2]==2) array_lt [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==3) array_lt [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==4) array_lt [0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==5) array_lt [ WA -1] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==8) array_lt [0 ][0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; + end else if (cnt[1:0]==2'd2) begin + // check array value + if (cnt[30:2]==0) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==2) begin if (array_lt !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==3) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==4) begin if (array_lt !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==5) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==7) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==8) begin if (array_lt !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==9) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) begin $display("%b", array_lt); $stop(); end end + end else if (cnt[1:0]==2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'bx}}) $stop(); end + else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end + end endmodule diff --git a/test_regress/t/t_enumeration.pl b/test_regress/t/t_enumeration.pl new file mode 100755 index 000000000..92e2f5596 --- /dev/null +++ b/test_regress/t/t_enumeration.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} and $Self->skip("Verilator unsupported, bug460"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_enumeration.v b/test_regress/t/t_enumeration.v new file mode 100644 index 000000000..49bb9b89b --- /dev/null +++ b/test_regress/t/t_enumeration.v @@ -0,0 +1,276 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cnt = 0; + integer mod = 0; + + // event counter + always @ (posedge clk) + if (cnt==20) begin + cnt <= 0; + mod <= mod + 1; + end else begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if (mod==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // anonymous type variable declaration + enum logic [2:0] {red=1, orange, yellow, green, blue, indigo, violet} rainbow7; + + // named type + typedef enum logic {OFF, ON} t_switch; + t_switch switch; + + // numbering examples + enum integer {father, mother, son[2], daughter, gerbil, dog[3]=10, cat[3:5]=20, car[3:1]=30} family; + + // test of raibow7 type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.first(); + // check number + if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end + if (rainbow7 !== 3'bxxx ) begin $display("%b", rainbow7 ); $stop(); end + end + else if (cnt== 1) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 2) begin + if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 3) begin + if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 4) begin + if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 5) begin + if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 6) begin + if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 7) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 8) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + end else if (mod==1) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.last(); + // check number + if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end + end + else if (cnt== 1) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 2) begin + if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 3) begin + if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 4) begin + if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 5) begin + if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 6) begin + if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 7) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 8) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + end + + // test of t_switch type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + switch <= switch.first(); + // check number + if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end + if (switch !== 1'bx) begin $display("%b", switch ); $stop(); end + end + else if (cnt== 1) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + else if (cnt== 2) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + else if (cnt== 3) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + end else if (mod==1) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.last(); + // check number + if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end + end + else if (cnt== 1) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + else if (cnt== 2) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + else if (cnt== 3) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + end + + // test of raibow7 type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + family <= family.first(); + // check number + if (family.num() !== 15 ) begin $display("%d", family.num() ); $stop(); end + if (family !== 32'dx ) begin $display("%b", family ); $stop(); end + end + else if (cnt== 1) begin + if (family !== 0 ) begin $display("%b", family ); $stop(); end + if (family !== father ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 2) begin + if (family !== 1 ) begin $display("%b", family ); $stop(); end + if (family !== mother ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 3) begin + if (family !== 2 ) begin $display("%b", family ); $stop(); end + if (family !== son0 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 4) begin + if (family !== 3 ) begin $display("%b", family ); $stop(); end + if (family !== son1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 5) begin + if (family !== 4 ) begin $display("%b", family ); $stop(); end + if (family !== daughter ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 6) begin + if (family !== 5 ) begin $display("%b", family ); $stop(); end + if (family !== gerbil ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 7) begin + if (family !== 10 ) begin $display("%b", family ); $stop(); end + if (family !== dog0 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 8) begin + if (family !== 11 ) begin $display("%b", family ); $stop(); end + if (family !== dog1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 9) begin + if (family !== 12 ) begin $display("%b", family ); $stop(); end + if (family !== dog2 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 10) begin + if (family !== 20 ) begin $display("%b", family ); $stop(); end + if (family !== cat3 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 11) begin + if (family !== 21 ) begin $display("%b", family ); $stop(); end + if (family !== cat4 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 12) begin + if (family !== 22 ) begin $display("%b", family ); $stop(); end + if (family !== cat5 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 13) begin + if (family !== 30 ) begin $display("%b", family ); $stop(); end + if (family !== car3 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 14) begin + if (family !== 31 ) begin $display("%b", family ); $stop(); end + if (family !== car2 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 15) begin + if (family !== 32 ) begin $display("%b", family ); $stop(); end + if (family !== car1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + end +endmodule diff --git a/test_regress/t/t_hierarchy_identifier.v b/test_regress/t/t_hierarchy_identifier.v index 2656922a2..48911ba82 100644 --- a/test_regress/t/t_hierarchy_identifier.v +++ b/test_regress/t/t_hierarchy_identifier.v @@ -18,7 +18,7 @@ module t (/*AUTOARG*/ logic vld_if = 1'b0; logic vld_else = 1'b0; - genvar i; + genvar i; // event counter always @ (posedge clk) begin @@ -27,27 +27,27 @@ module t (/*AUTOARG*/ // finish report always @ (posedge clk) - if (cnt==SIZE) begin : if_cnt_finish - $write("*-* All Finished *-*\n"); - $finish; - end : if_cnt_finish + if (cnt==SIZE) begin : if_cnt_finish + $write("*-* All Finished *-*\n"); + $finish; + end : if_cnt_finish generate - for (i=0; i0) begin : generate_if_if - always @ (posedge clk) - vld_if <= 1'b1; - end : generate_if_if - else begin : generate_if_else - always @ (posedge clk) - vld_else <= 1'b1; - end : generate_if_else + if (SIZE>0) begin : generate_if_if + always @ (posedge clk) + vld_if <= 1'b1; + end : generate_if_if + else begin : generate_if_else + always @ (posedge clk) + vld_else <= 1'b1; + end : generate_if_else endgenerate endmodule : t diff --git a/test_regress/t/t_hierarchy_identifier_bad.pl b/test_regress/t/t_hierarchy_identifier_bad.pl index 64a865a77..45c69b502 100755 --- a/test_regress/t/t_hierarchy_identifier_bad.pl +++ b/test_regress/t/t_hierarchy_identifier_bad.pl @@ -18,7 +18,7 @@ q{%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'if_cnt_finis %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 't_bad' does not match begin label 't' %Error: Exiting due to.*}, - ); + ); ok(1); 1; diff --git a/test_regress/t/t_hierarchy_identifier_bad.v b/test_regress/t/t_hierarchy_identifier_bad.v index e31eaf193..f8f12de5a 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.v +++ b/test_regress/t/t_hierarchy_identifier_bad.v @@ -18,36 +18,36 @@ module t (/*AUTOARG*/ logic vld_if = 1'b0; logic vld_else = 1'b0; - genvar i; + genvar i; // event counter always @ (posedge clk) begin - cnt <= cnt + 1; - end + cnt <= cnt + 1; + end // finish report always @ (posedge clk) - if (cnt==SIZE) begin : if_cnt_finish - $write("*-* All Finished *-*\n"); - $finish; - end : if_cnt_finish_bad + if (cnt==SIZE) begin : if_cnt_finish + $write("*-* All Finished *-*\n"); + $finish; + end : if_cnt_finish_bad generate - for (i=0; i0) begin : generate_if_if - always @ (posedge clk) - vld_if <= 1'b1; - end : generate_if_if_bad - else begin : generate_if_else - always @ (posedge clk) - vld_else <= 1'b1; - end : generate_if_else_bad + if (SIZE>0) begin : generate_if_if + always @ (posedge clk) + vld_if <= 1'b1; + end : generate_if_if_bad + else begin : generate_if_else + always @ (posedge clk) + vld_else <= 1'b1; + end : generate_if_else_bad endgenerate endmodule : t_bad diff --git a/test_regress/t/t_structure_packed_sysfunct.pl b/test_regress/t/t_structure_packed_sysfunct.pl new file mode 100755 index 000000000..e6361ac39 --- /dev/null +++ b/test_regress/t/t_structure_packed_sysfunct.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} and $Self->skip("Verilator unsupported, bug181"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_structure_packed_sysfunct.v b/test_regress/t/t_structure_packed_sysfunct.v new file mode 100644 index 000000000..da47b758f --- /dev/null +++ b/test_regress/t/t_structure_packed_sysfunct.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_bg; // big endian structure + /* verilator lint_off LITENDIAN */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_lt; // little endian structure + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + + // event counter + always @ (posedge clk) + begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if (cnt==2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + always @ (posedge clk) + if (cnt==1) begin + // big endian + if ($bits (struct_bg ) != 15) $stop; + if ($bits (struct_bg.e0) != 1) $stop; + if ($bits (struct_bg.e1) != 2) $stop; + if ($bits (struct_bg.e2) != 4) $stop; + if ($bits (struct_bg.e3) != 8) $stop; +// if ($increment (struct_bg, 1) != 1) $stop; + // little endian + if ($bits (struct_lt ) != 15) $stop; + if ($bits (struct_lt.e0) != 1) $stop; + if ($bits (struct_lt.e1) != 2) $stop; + if ($bits (struct_lt.e2) != 4) $stop; + if ($bits (struct_lt.e3) != 8) $stop; +// if ($increment (struct_lt, 1) != -1) $stop; + end + +endmodule diff --git a/test_regress/t/t_structure_packed_value_list.pl b/test_regress/t/t_structure_packed_value_list.pl new file mode 100755 index 000000000..2f21be6f8 --- /dev/null +++ b/test_regress/t/t_structure_packed_value_list.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} and $Self->skip("Verilator unsupported, bug355"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_structure_packed_value_list.v b/test_regress/t/t_structure_packed_value_list.v new file mode 100644 index 000000000..0a833ffee --- /dev/null +++ b/test_regress/t/t_structure_packed_value_list.v @@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam NO = 7; // number of access events + + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_bg; // big endian structure + /* verilator lint_off LITENDIAN */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_lt; // little endian structure + /* verilator lint_on LITENDIAN */ + + localparam WS = 15; // $bits(struct_bg) + + integer cnt = 0; + + // event counter + always @ (posedge clk) + begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'bx) + if (cnt[30:2]==0) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==1) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==2) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==3) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==4) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==5) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==6) struct_bg <= {WS{1'bx}}; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3}; + else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4}; + else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0}; + else if (cnt[30:2]==4) struct_bg <= '{default:13}; + else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1}; + else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]==0) begin if (struct_bg !== 15'bx_xx_xxxx_xxxxxxxx) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'bx) + if (cnt[30:2]==0) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==1) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==2) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==3) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==4) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==5) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==6) struct_lt <= {WS{1'bx}}; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3}; + else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4}; + else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0}; + else if (cnt[30:2]==4) struct_lt <= '{default:13}; + else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1}; + else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]==0) begin if (struct_lt !== 15'bx_xx_xxxx_xxxxxxxx) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end + end + +endmodule diff --git a/test_regress/t/t_structure_packed_write_read.pl b/test_regress/t/t_structure_packed_write_read.pl new file mode 100755 index 000000000..e6361ac39 --- /dev/null +++ b/test_regress/t/t_structure_packed_write_read.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} and $Self->skip("Verilator unsupported, bug181"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_structure_packed_write_read.v b/test_regress/t/t_structure_packed_write_read.v new file mode 100644 index 000000000..de2ba3ea3 --- /dev/null +++ b/test_regress/t/t_structure_packed_write_read.v @@ -0,0 +1,120 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam NO = 10; // number of access events + + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_bg; // big endian structure + /* verilator lint_off LITENDIAN */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_lt; // little endian structure + /* verilator lint_on LITENDIAN */ + + localparam WS = 15; // $bits(struct_bg) + + integer cnt = 0; + + // event counter + always @ (posedge clk) + begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to x) + if (cnt[30:2]==0) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==1) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==2) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==3) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==4) struct_bg <= {WS{1'bx}}; + else if (cnt[30:2]==5) struct_bg <= {WS{1'bx}}; + end else if (cnt[1:0]==2'd1) begin + // write value to structure + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) struct_bg <= {WS{1'b1}}; + else if (cnt[30:2]==2) struct_bg.e0 <= {WS{1'b1}}; + else if (cnt[30:2]==3) struct_bg.e1 <= {WS{1'b1}}; + else if (cnt[30:2]==4) struct_bg.e2 <= {WS{1'b1}}; + else if (cnt[30:2]==5) struct_bg.e3 <= {WS{1'b1}}; + end else if (cnt[1:0]==2'd2) begin + // check structure value + if (cnt[30:2]==0) begin if (struct_bg !== 15'bxxxxxxxxxxxxxxx) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1xxxxxxxxxxxxxx) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_bg !== 15'bx11xxxxxxxxxxxx) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_bg !== 15'bxxx1111xxxxxxxx) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_bg !== 15'bxxxxxxx11111111) begin $display("%b", struct_bg); $stop(); end end + end else if (cnt[1:0]==2'd3) begin + // read value from structure (not a very good test for now) + if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'bx}}) $stop(); end + else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to x) + if (cnt[30:2]==0) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==1) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==2) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==3) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==4) struct_lt <= {WS{1'bx}}; + else if (cnt[30:2]==5) struct_lt <= {WS{1'bx}}; + end else if (cnt[1:0]==2'd1) begin + // write value to structure + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) struct_lt <= {WS{1'b1}}; + else if (cnt[30:2]==2) struct_lt.e0 <= {WS{1'b1}}; + else if (cnt[30:2]==3) struct_lt.e1 <= {WS{1'b1}}; + else if (cnt[30:2]==4) struct_lt.e2 <= {WS{1'b1}}; + else if (cnt[30:2]==5) struct_lt.e3 <= {WS{1'b1}}; + end else if (cnt[1:0]==2'd2) begin + // check structure value + if (cnt[30:2]==0) begin if (struct_lt !== 15'bxxxxxxxxxxxxxxx) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1xxxxxxxxxxxxxx) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_lt !== 15'bx11xxxxxxxxxxxx) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_lt !== 15'bxxx1111xxxxxxxx) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_lt !== 15'bxxxxxxx11111111) begin $display("%b", struct_lt); $stop(); end end + end else if (cnt[1:0]==2'd3) begin + // read value from structure (not a very good test for now) + if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'bx}}) $stop(); end + else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end + end + +endmodule diff --git a/test_regress/t/t_sv_bus_mux_demux.pl b/test_regress/t/t_sv_bus_mux_demux.pl new file mode 100755 index 000000000..e6361ac39 --- /dev/null +++ b/test_regress/t/t_sv_bus_mux_demux.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} and $Self->skip("Verilator unsupported, bug181"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_sv_bus_mux_demux.v b/test_regress/t/t_sv_bus_mux_demux.v new file mode 100644 index 000000000..f62c837e7 --- /dev/null +++ b/test_regress/t/t_sv_bus_mux_demux.v @@ -0,0 +1,193 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// // +// This testbench contains a bus source and a bus drain. The source creates // +// address and data bus values, while the drain is the final destination of // +// such pairs. All source and drain transfers are logged into memories, which // +// are used at the end of simulation to check for data transfer correctness. // +// Inside the RLT wrapper there is a multiplexer and a demultiplexer, they // +// bus transfers into a 8bit data stream and back. Both stream input and // +// output are exposed, they are connected together into a loopback. // +// // +// ----------- --------------------- // +// | bso_mem | | wrap | // +// ----------- | | // +// ----------- | | ----------- | // +// | bsi src | ------------> | -> | mux | -> | -> - sto // +// ----------- | ----------- | \ // +// | | | loopback // +// ----------- | ----------- | / // +// | bso drn | <------------ | <- | demux | <- | <- - sti // +// ----------- | | ----------- | // +// ----------- | | // +// | bso_mem | | | // +// ----------- --------------------- // +// // +// PROTOCOL: // +// // +// The 'vld' signal is driven by the source to indicate valid data is // +// available, 'rdy' is used by the drain to indicate is is ready to accept // +// valid data. A data transfer only happens if both 'vld' & 'rdy' are active. // +// // +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + +// include RTL files +`include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv" +`include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv" +`include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv" +`include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + +input clk; + +parameter SIZ = 10; + +// system signals +//logic clk = 1'b1; // clock +logic rst = 1'b1; // reset +integer rst_cnt = 0; + +// input bus +logic bsi_vld; // valid (chip select) +logic [31:0] bsi_adr; // address +logic [31:0] bsi_dat; // data +logic bsi_rdy; // ready (acknowledge) +logic bsi_trn; // data transfer +logic [31:0] bsi_mem [SIZ]; +// output stream +logic sto_vld; // valid (chip select) +logic [7:0] sto_bus; // data bus +logic sto_rdy; // ready (acknowledge) + +// input stream +logic sti_vld; // valid (chip select) +logic [7:0] sti_bus; // data bus +logic sti_rdy; // ready (acknowledge) +// output bus +logic bso_vld; // valid (chip select) +logic [31:0] bso_adr; // address +logic [31:0] bso_dat; // data +logic bso_rdy; // ready (acknowledge) +logic bso_trn; // data transfer +logic [31:0] bso_mem [SIZ]; +integer bso_cnt = 0; + +//////////////////////////////////////////////////////////////////////////////// +// clock and reset +//////////////////////////////////////////////////////////////////////////////// + +// clock toggling +//always #5 clk = ~clk; + +// reset is removed after a delay +always @ (posedge clk) +begin + rst_cnt <= rst_cnt + 1; + rst <= rst_cnt <= 3; +end + +// reset is removed after a delay +always @ (posedge clk) +if (bso_cnt == SIZ) begin + if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end + else begin $display ("FAILED"); $stop(); end +end + +//////////////////////////////////////////////////////////////////////////////// +// input data generator +//////////////////////////////////////////////////////////////////////////////// + +// input data transfer +assign bsi_trn = bsi_vld & bsi_rdy; + +// valid (for SIZ transfers) +always @ (posedge clk, posedge rst) +if (rst) bsi_vld = 1'b0; +else bsi_vld = (bsi_adr < SIZ); + +// address (increments every transfer) +always @ (posedge clk, posedge rst) +if (rst) bsi_adr <= 32'h00000000; +else if (bsi_trn) bsi_adr <= bsi_adr + 'd1; + +// data (new random value generated after every transfer) +always @ (posedge clk, posedge rst) +if (rst) bsi_dat <= 32'h00000000; +else if (bsi_trn) bsi_dat <= $random(); + +// storing transferred data into memory for final check +always @ (posedge clk) +if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat; + +//////////////////////////////////////////////////////////////////////////////// +// RTL instance +//////////////////////////////////////////////////////////////////////////////// + +sv_bus_mux_demux_wrap wrap ( + // system signals + .clk (clk), + .rst (rst), + // input bus + .bsi_vld (bsi_vld), + .bsi_adr (bsi_adr), + .bsi_dat (bsi_dat), + .bsi_rdy (bsi_rdy), + // output stream + .sto_vld (sto_vld), + .sto_bus (sto_bus), + .sto_rdy (sto_rdy), + // input stream + .sti_vld (sti_vld), + .sti_bus (sti_bus), + .sti_rdy (sti_rdy), + // output bus + .bso_vld (bso_vld), + .bso_adr (bso_adr), + .bso_dat (bso_dat), + .bso_rdy (bso_rdy) +); + +// stream output from mux is looped back into stream input for demux +assign sti_vld = sto_vld; +assign sti_bus = sto_bus; +assign sto_rdy = sti_rdy; + +//////////////////////////////////////////////////////////////////////////////// +// output data monitor +//////////////////////////////////////////////////////////////////////////////// + +// input data transfer +assign bso_trn = bso_vld & bso_rdy; + +// output transfer counter used to end the test +always @ (posedge clk, posedge rst) +if (rst) bso_cnt <= 0; +else if (bso_trn) bso_cnt <= bso_cnt + 1; + +// storing transferred data into memory for final check +always @ (posedge clk) +if (bso_trn) bso_mem [bso_adr] <= bso_dat; + +// every output transfer against expected value stored in memory +always @ (posedge clk) +if (bso_trn && (bsi_mem [bso_adr] !== bso_dat)) +$display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat); + +// ready is active for SIZ transfers +always @ (posedge clk, posedge rst) +if (rst) bso_rdy = 1'b0; +else bso_rdy = 1'b1; + +endmodule : sv_bus_mux_demux_tb diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv new file mode 100644 index 000000000..c68194655 --- /dev/null +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv @@ -0,0 +1,29 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +// definition of data bus structure +package package_bus; + typedef struct packed { + logic [3:0] [7:0] adr; // address + logic [3:0] [7:0] dat; // data + } t_bus; +endpackage : package_bus + +// definition of streaming bus packet as an array +package package_str; + typedef logic [7:0][7:0] t_str; +endpackage : package_str + +// union of the structure and array representation +package package_uni; + import package_bus::*; + import package_str::*; + typedef union packed { + t_bus bus; + t_str str; + } t_uni; +endpackage : package_uni diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv new file mode 100644 index 000000000..4f214ae07 --- /dev/null +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv @@ -0,0 +1,68 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +import package_bus::*; +import package_str::*; + +module sv_bus_mux_demux_demux ( + // system signals + input logic clk, // clock + input logic rst, // reset + // output stream + input logic str_vld, // valid (chip select) + input logic [7:0] str_bus, // byte data bus + output logic str_rdy, // ready (acknowledge) + // input bus + output logic bus_vld, // valid (chip select) + output logic [31:0] bus_adr, // address + output logic [31:0] bus_dat, // data + input logic bus_rdy // ready (acknowledge) +); + +logic bus_trn; // bus data transfer +logic str_trn; // stream data transfer + +logic [2:0] pkt_cnt; // packet byte counter +logic pkt_end; // packet byte counter end + +t_str pkt_str; // transfer packet as a structure +t_bus pkt_bus; // transfer packet as an array + +// stream data transfer +assign str_trn = str_vld & str_rdy; + +// ready if pipe is empty or output is ready +assign str_rdy = ~bus_vld | bus_rdy; + +// packet byte counter +always @ (posedge clk, posedge rst) +if (rst) pkt_cnt <= 3'd0; +else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; + +// packet byte counter end +assign pkt_end = (&pkt_cnt); + +always @ (posedge clk) +if (str_trn) pkt_str [pkt_cnt] <= str_bus; + +// the input packed array is mapped onto the output structure +assign pkt_bus = pkt_str; + +// the output structure is mapped onto address/data outputs +assign bus_adr = pkt_bus.adr; +assign bus_dat = pkt_bus.dat; + +// output valid is set on the last input packed byte +// or cleared by each output transfer +always @ (posedge clk, posedge rst) +if (rst) bus_vld <= 1'b0; +else bus_vld <= str_trn & pkt_end | bus_vld & ~bus_rdy; + +// bus data transfer +assign bus_trn = bus_vld & bus_rdy; + +endmodule : sv_bus_mux_demux_demux diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv new file mode 100644 index 000000000..93e320049 --- /dev/null +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv @@ -0,0 +1,70 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +import package_bus::*; +import package_str::*; +import package_uni::*; + +module sv_bus_mux_demux_mux ( + // system signals + input logic clk, // clock + input logic rst, // reset + // input bus + input logic bus_vld, // valid (chip select) + input logic [31:0] bus_adr, // address + input logic [31:0] bus_dat, // data + output logic bus_rdy, // ready (acknowledge) + // output stream + output logic str_vld, // valid (chip select) + output logic [7:0] str_bus, // byte data bus + input logic str_rdy // ready (acknowledge) +); + +logic bus_trn; // bus data transfer +logic str_trn; // stream data transfer + +logic [2:0] pkt_cnt; // packet byte counter +logic pkt_end; // packet byte counter end + +//t_bus pkt_bus; // transfer packet as a structure +//t_str pkt_str; // transfer packet as an array +t_uni pkt_uni; // transfer packet as an union + +// bus data transfer +assign bus_trn = bus_vld & bus_rdy; + +// ready if pipe is empty or output is ready +assign bus_rdy = ~str_vld | pkt_end; + +// writing input address/data into a structure +always @ (posedge clk) +if (bus_trn) begin + pkt_uni.bus.adr <= bus_adr; + pkt_uni.bus.dat <= bus_dat; +end + +// output valid is set by an input transfer +// or cleared by the last output transfer +always @ (posedge clk, posedge rst) +if (rst) str_vld <= 1'b0; +else str_vld <= bus_trn | (str_vld & ~pkt_end); + +// packet byte counter +always @ (posedge clk, posedge rst) +if (rst) pkt_cnt <= 4'd0; +else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; + +// packet byte counter end +assign pkt_end = str_rdy & (&pkt_cnt); + +// TODO, this should be a registered signal +assign str_bus = pkt_uni.str [pkt_cnt]; + +// stream data transfer +assign str_trn = str_vld & str_rdy; + +endmodule : sv_bus_mux_demux_mux diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv new file mode 100644 index 000000000..0715188ac --- /dev/null +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv @@ -0,0 +1,82 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// // +// This wrapper contains a bus multiplexer and a bus demultiplexer. Both // +// modules have all ports exposed an there are no signals connecting them. // +// // +// --------------------- // +// | wrap | // +// | | // +// | ----------- | // +// bsi -> | -> | mux | -> | -> sto // +// | ----------- | // +// | | // +// | ----------- | // +// bso <- | <- | demux | <- | <- sto // +// | ----------- | // +// | | // +// --------------------- // +// // +//////////////////////////////////////////////////////////////////////////////// + +module sv_bus_mux_demux_wrap ( + // system signals + input logic clk, + input logic rst, + // input bus + input logic bsi_vld, // valid (chip select) + input logic [31:0] bsi_adr, // address + input logic [31:0] bsi_dat, // data + output logic bsi_rdy, // ready (acknowledge) + // output stream + output logic sto_vld, + output logic [7:0] sto_bus, + input logic sto_rdy, + // input stream + input logic sti_vld, + input logic [7:0] sti_bus, + output logic sti_rdy, + // output bus + output logic bso_vld, // valid (chip select) + output logic [31:0] bso_adr, // address + output logic [31:0] bso_dat, // data + input logic bso_rdy // ready (acknowledge) +); + +sv_bus_mux_demux_mux mux ( + // system signals + .clk (clk), + .rst (rst), + // input bus + .bus_vld (bsi_vld), + .bus_adr (bsi_adr), + .bus_dat (bsi_dat), + .bus_rdy (bsi_rdy), + // output stream + .str_vld (sto_vld), + .str_bus (sto_bus), + .str_rdy (sto_rdy) +); + +sv_bus_mux_demux_demux demux ( + // system signals + .clk (clk), + .rst (rst), + // input stream + .str_vld (sti_vld), + .str_bus (sti_bus), + .str_rdy (sti_rdy), + // output bus + .bus_vld (bso_vld), + .bus_adr (bso_adr), + .bus_dat (bso_dat), + .bus_rdy (bso_rdy) +); + +endmodule : sv_bus_mux_demux_wrap