diff --git a/Changes b/Changes
index 4191175e0..faa8203bd 100644
--- a/Changes
+++ b/Changes
@@ -10,6 +10,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix dpi exports with > 32 bit but < 64 bit args, bug423. [Chandan Egbert]
 
+****  Fix array of instantiations with sub-range output, bug414. [Jeremy Bennett]
+
 
 * Verilator 3.830 2011/11/27
 
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index 491c269c0..c40f442cb 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -203,8 +203,10 @@ private:
 		// Arrayed instants: one bit for each of the instants (each assign is 1 pinwidth wide)
 		AstNode* exprp = nodep->exprp()->unlinkFrBack();
 		bool inputPin = nodep->modVarp()->isInput();
-		if (!inputPin && !exprp->castVarRef()) {
+		if (!inputPin && !exprp->castVarRef()
+		    && !exprp->castSel()) {  // V3Const will collapse the SEL with the one we're about to make
 		    nodep->v3error("Unsupported: Per-bit array instantiations with output connections to non-wires.");
+		    // Note spec allows more complicated matches such as slices and such
 		}
 		exprp = new AstSel (exprp->fileline(), exprp,
 				    pinwidth*(m_instNum-m_instLsb),
diff --git a/test_regress/t/t_inst_array_partial.pl b/test_regress/t/t_inst_array_partial.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_inst_array_partial.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_inst_array_partial.v b/test_regress/t/t_inst_array_partial.v
new file mode 100644
index 000000000..da6439ee2
--- /dev/null
+++ b/test_regress/t/t_inst_array_partial.v
@@ -0,0 +1,88 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Jeremy Bennett.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   wire [17:10] bitout;
+   wire [27:24] short_bitout;
+   wire [7:0] 	allbits;
+   wire [15:0] 	twobits;
+
+   sub
+     i_sub1 [7:4] (.allbits (allbits),
+		   .twobits (twobits[15:8]),
+		   .bitout (bitout[17:14])),
+     i_sub2 [3:0] (.allbits (allbits),
+		   .twobits (twobits[7:0]),
+		   .bitout (bitout[13:10]));
+
+   sub
+     i_sub3 [7:4] (.allbits (allbits),
+		   .twobits (twobits[15:8]),
+		   .bitout (bitout[17:14]));
+
+   sub
+     i_sub4 [7:4] (.allbits (allbits),
+		   .twobits (twobits[15:8]),
+		   .bitout (short_bitout[27:24]));
+
+   sub
+     i_sub5 [7:0] (.allbits (allbits),
+		   .twobits (twobits),
+		   .bitout (bitout[17:10]));
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Signals under test
+   assign allbits = crc[7:0];
+   assign twobits = crc[15:0];
+   wire [63:0] result = {52'h0, short_bitout, bitout};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h0bf9559ce1f98425
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+   
+endmodule // t
+
+
+module sub
+  ( input wire  [7:0] allbits,
+    input wire  [1:0] twobits,
+    output wire       bitout);
+
+   assign bitout = (^ twobits) ^ (^ allbits);
+  
+endmodule // sub