From e40b5819bd2ad0d0d0fc9cd8ae89f8a5c3747988 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 14 Jan 2010 21:03:06 -0500
Subject: [PATCH] Speed compiles by avoiding including the STL iostream header.

---
 Changes                           |  3 +++
 include/verilated.h               |  3 ++-
 include/verilatedimp.h            |  1 +
 src/V3EmitC.cpp                   | 12 ++++++------
 test_regress/t/t_extend.v         |  6 +++---
 test_regress/t/t_func_graphcirc.v |  6 +++---
 test_regress/t/t_initial.v        |  4 ++--
 test_regress/t/t_tri_gate.cpp     |  2 +-
 test_regress/t/t_tri_inout.cpp    |  2 +-
 test_regress/t/t_tri_pullup.cpp   |  2 +-
 test_regress/t/t_tri_select.cpp   |  2 +-
 test_regress/t/t_var_pinsizes.cpp |  2 +-
 12 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/Changes b/Changes
index 918c9cba7..ece36e9c2 100644
--- a/Changes
+++ b/Changes
@@ -29,6 +29,9 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Add experimental clock domain crossing checks.
 
+***  Speed compiles by avoiding including the STL iostream header.
+     Application programs may need to include it themselves to avoid errors.
+
 **** Support optional cell parenthesis, bug179. [by Byron Bradley]
 
 **** Support for loop i++, ++i, i--, --i, bug175. [by Byron Bradley]
diff --git a/include/verilated.h b/include/verilated.h
index c7d60ac8a..e729a0275 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -35,7 +35,8 @@
 #include <cstdio>
 #include <cstdlib>
 #include <cstring>
-#include <iostream>
+// <iostream> avoided to reduce compile time
+// <string> avoided to reduce compile time
 using namespace std;
 
 //=========================================================================
diff --git a/include/verilatedimp.h b/include/verilatedimp.h
index ce0b97b79..7e2c4afc4 100644
--- a/include/verilatedimp.h
+++ b/include/verilatedimp.h
@@ -33,6 +33,7 @@
 
 #include <map>
 #include <vector>
+#include <string>
 
 class VerilatedScope;
 
diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp
index 7f7c2f759..3f019d1c8 100644
--- a/src/V3EmitC.cpp
+++ b/src/V3EmitC.cpp
@@ -705,10 +705,10 @@ class EmitCImp : EmitCStmts {
 	puts(modClassName(m_modp)+"::"+nodep->name()
 	     +"("+cFuncArgs(nodep)+") {\n");
 
-	puts("VL_DEBUG_IF(cout<<\"  ");
+	puts("VL_DEBUG_IF(VL_PRINTF(\"  ");
 	for (int i=0;i<m_modp->level();i++) { puts("  "); }
 	puts(modClassName(m_modp)+"::"+nodep->name()
-	     +"\"<<endl; );\n");
+	     +"\\n\"); );\n");
 
 	if (nodep->symProlog()) puts(EmitCBaseVisitor::symTopAssign()+"\n");
 
@@ -771,8 +771,8 @@ class EmitCImp : EmitCStmts {
 		    if (nodep->lhsp()->castVarRef()) {
 			varname = ": "+nodep->lhsp()->castVarRef()->varp()->prettyName();
 		    }
-		    puts(")) cout<<\"\tCHANGE: "+nodep->fileline()->ascii()
-			 +varname+"\"<<endl; );\n");
+		    puts(")) VL_PRINTF(\"\tCHANGE: "+nodep->fileline()->ascii()
+			 +varname+"\\n\"); );\n");
 		}
 	    }
 	}
@@ -1435,12 +1435,12 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
 	puts("if (VL_UNLIKELY(__Vm_inhibitSim)) return;\n");
     }
     puts("// Evaluate till stable\n");
-    puts("VL_DEBUG_IF(cout<<\"\\n----TOP Evaluate "+modClassName(modp)+"::eval\"<<endl; );\n");
+    puts("VL_DEBUG_IF(VL_PRINTF(\"\\n----TOP Evaluate "+modClassName(modp)+"::eval\\n\"); );\n");
 #ifndef NEW_ORDERING
     puts("int __VclockLoop = 0;\n");
     puts("IData __Vchange=1;\n");
     puts("while (VL_LIKELY(__Vchange)) {\n");
-    puts(    "VL_DEBUG_IF(cout<<\" Clock loop\"<<endl;);\n");
+    puts(    "VL_DEBUG_IF(VL_PRINTF(\" Clock loop\\n\"););\n");
 #endif
     puts(    "vlSymsp->__Vm_activity = true;\n");
     puts(    "_eval(vlSymsp);\n");
diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v
index 6ddf1a985..4babc6f48 100644
--- a/test_regress/t/t_extend.v
+++ b/test_regress/t/t_extend.v
@@ -30,9 +30,9 @@ module t (/*AUTOARG*/
 	 c_worked <= 0;
       end
       if (cyc == 8'd2) begin
-`ifdef verilator
-	 $c("cout<<\"Calling $c, calling $c...\"<<endl;");
-	 $c("cout<<\"Cyc=\"<<dec<<(int)(",cyc,")<<endl;");
+`ifdef VERILATOR
+	 $c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
+	 $c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
 	 c_worked <= $c("my_function()");
 	 c_wider <= $c9("0x10");
 `else
diff --git a/test_regress/t/t_func_graphcirc.v b/test_regress/t/t_func_graphcirc.v
index 562962f1b..8773c24a3 100644
--- a/test_regress/t/t_func_graphcirc.v
+++ b/test_regress/t/t_func_graphcirc.v
@@ -37,10 +37,10 @@ module t (clk);
             if ( cyc >= 4 ) begin
 	       dindex = dindex + 2; //*** Error line
 	       $display("%m: DIndex increment %d", cyc);
-	       $c("cout<<\"Hello1?\"<<endl;");
+	       $c("VL_PRINTF(\"Hello1?\\n\");");
             end
-	    $c("cout<<\"Hello2?\"<<endl;");
-	    $c("cout<<\"Hello3?\"<<endl;");
+	    $c("VL_PRINTF(\"Hello2?\\n\");");
+	    $c("VL_PRINTF(\"Hello3?\\n\");");
 	 end
       end
    endtask
diff --git a/test_regress/t/t_initial.v b/test_regress/t/t_initial.v
index 96431c72e..7cb6d14b8 100644
--- a/test_regress/t/t_initial.v
+++ b/test_regress/t/t_initial.v
@@ -32,8 +32,8 @@ module t_initial (/*AUTOARG*/
 	 if (user_loaded_value!=1) $stop;
 
 	 // Test $c
-`ifdef verilator
-	 $c ("cout<<\"Hi From C++\"<<endl;");
+`ifdef VERILATOR
+	 $c ("VL_PRINTF(\"Hi From C++\\n\");");
 `endif
 	 user_loaded_value <= 2;
 
diff --git a/test_regress/t/t_tri_gate.cpp b/test_regress/t/t_tri_gate.cpp
index da9fc384a..247d98c5e 100644
--- a/test_regress/t/t_tri_gate.cpp
+++ b/test_regress/t/t_tri_gate.cpp
@@ -53,7 +53,7 @@ int main() {
     }
 
     if(pass) {
-	cout << "*-* All Finished *-*" << endl;
+	VL_PRINTF("*-* All Finished *-*\n");
 	tb->final();
     } else {
 	vl_fatal(__FILE__,__LINE__,"top", "Unexpected results from tristate test\n");
diff --git a/test_regress/t/t_tri_inout.cpp b/test_regress/t/t_tri_inout.cpp
index fca375e97..f5766528a 100644
--- a/test_regress/t/t_tri_inout.cpp
+++ b/test_regress/t/t_tri_inout.cpp
@@ -48,7 +48,7 @@ int main() {
     }
 
     if(pass) {
-	cout << "*-* All Finished *-*" << endl;
+	VL_PRINTF("*-* All Finished *-*\n");
 	tb->final();
     } else {
 	vl_fatal(__FILE__,__LINE__,"top", "Unexpected results from inout test\n");
diff --git a/test_regress/t/t_tri_pullup.cpp b/test_regress/t/t_tri_pullup.cpp
index d0731f4c5..e111db01c 100644
--- a/test_regress/t/t_tri_pullup.cpp
+++ b/test_regress/t/t_tri_pullup.cpp
@@ -50,7 +50,7 @@ int main() {
     }
 
     if (pass) {
-	cout << "*-* All Finished *-*" << endl;
+	VL_PRINTF("*-* All Finished *-*\n");
 	tb->final();
     } else {
 	vl_fatal(__FILE__,__LINE__,"top", "Unexpected results from pullup test\n");
diff --git a/test_regress/t/t_tri_select.cpp b/test_regress/t/t_tri_select.cpp
index ce8d4225e..caea7c884 100644
--- a/test_regress/t/t_tri_select.cpp
+++ b/test_regress/t/t_tri_select.cpp
@@ -50,7 +50,7 @@ int main() {
     }
 
     if(pass) {
-	cout << "*-* All Finished *-*" << endl;
+	VL_PRINTF("*-* All Finished *-*\n");
 	tb->final();
     } else {
 	vl_fatal(__FILE__,__LINE__,"top", "Unexpected results from t_tri_select\n");
diff --git a/test_regress/t/t_var_pinsizes.cpp b/test_regress/t/t_var_pinsizes.cpp
index 247fd8c8c..a347e9ea5 100644
--- a/test_regress/t/t_var_pinsizes.cpp
+++ b/test_regress/t/t_var_pinsizes.cpp
@@ -24,7 +24,7 @@ int main() {
     Verilated::debug(0);
     tb  = new VM_PREFIX("tb");
 
-    cout << "*-* All Finished *-*" << endl;
+    VL_PRINTF("*-* All Finished *-*\n");
     tb->final();
     return 0;
 }