From e3bdae77a0cb5a3ac3f89f50cb604d9199828343 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 9 Apr 2023 17:08:04 -0400 Subject: [PATCH] Tests: Add randsequence test --- test_regress/t/t_randsequence_bad.out | 20 ++++++++++++++++++++ test_regress/t/t_randsequence_bad.pl | 19 +++++++++++++++++++ test_regress/t/t_randsequence_bad.v | 25 +++++++++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 test_regress/t/t_randsequence_bad.out create mode 100755 test_regress/t/t_randsequence_bad.pl create mode 100644 test_regress/t/t_randsequence_bad.v diff --git a/test_regress/t/t_randsequence_bad.out b/test_regress/t/t_randsequence_bad.out new file mode 100644 index 000000000..9cc011c04 --- /dev/null +++ b/test_regress/t/t_randsequence_bad.out @@ -0,0 +1,20 @@ +%Error-UNSUPPORTED: t/t_randsequence_bad.v:13:25: Unsupported: randsequence production + 13 | such_production: { }; + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_randsequence_bad.v:12:7: Unsupported: randsequence + 12 | randsequence(no_such_production) + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_randsequence_bad.v:17:16: Unsupported: randsequence production id + 17 | main: production_bad; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_randsequence_bad.v:17:14: Unsupported: randsequence production + 17 | main: production_bad; + | ^ +%Error-UNSUPPORTED: t/t_randsequence_bad.v:18:24: Unsupported: randsequence production + 18 | production_baa: {}; + | ^ +%Error-UNSUPPORTED: t/t_randsequence_bad.v:16:7: Unsupported: randsequence + 16 | randsequence(main) + | ^~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_randsequence_bad.pl b/test_regress/t/t_randsequence_bad.pl new file mode 100755 index 000000000..a083f46f5 --- /dev/null +++ b/test_regress/t/t_randsequence_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_randsequence_bad.v b/test_regress/t/t_randsequence_bad.v new file mode 100644 index 000000000..5e335f237 --- /dev/null +++ b/test_regress/t/t_randsequence_bad.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2023 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t(/*AUTOARG*/); + + initial begin; + randsequence(no_such_production) // Bad + such_production: { }; + endsequence + + randsequence(main) + main: production_bad; // Bad + production_baa: {}; + endsequence + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule