From e33b24fad24b7a7429cf685118c3f2040833a29c Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Thu, 9 Oct 2025 09:25:39 +0100 Subject: [PATCH] Fix Dfg circular driver tracing with partial assignments --- src/V3DfgBreakCycles.cpp | 3 ++- test_regress/t/t_dfg_break_cycles.v | 12 ++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/V3DfgBreakCycles.cpp b/src/V3DfgBreakCycles.cpp index 8f15bf405..97ba8c16c 100644 --- a/src/V3DfgBreakCycles.cpp +++ b/src/V3DfgBreakCycles.cpp @@ -187,7 +187,8 @@ class TraceDriver final : public DfgVisitor { // as a splice cannot be fed into arbitray logic if (DfgVertexSplice* const splicep = resp->cast()) { DfgVertexVar* const tmpp = createTmp("TraceDriver", splicep); - splicep->replaceWith(tmpp); + // Note: we can't do 'splicep->replaceWith(tmpp)', as other + // variable sinks of the splice might have a defaultp driver. tmpp->srcp(splicep); resp = tmpp; } diff --git a/test_regress/t/t_dfg_break_cycles.v b/test_regress/t/t_dfg_break_cycles.v index 4413dff92..3e9891188 100644 --- a/test_regress/t/t_dfg_break_cycles.v +++ b/test_regress/t/t_dfg_break_cycles.v @@ -249,4 +249,16 @@ module t ( `signal(ARRAY_4, 32); assign ARRAY_4 = array_4[2]; + logic [1:0] packed_0; // UNOPTFLAT + logic packed_0_lsb; + always_comb begin + packed_0[1] = rand_b[1]; + packed_0_lsb = packed_0[0]; + end + always_comb packed_0[0] = rand_b[0]; + assign PACKED_0 = packed_0; + `signal(PACKED_0, 2); + `signal(PACKED_0_LSB, 1); + assign PACKED_0_LSB = packed_0_lsb; + endmodule