diff --git a/test_regress/t/t_cover_branch_option.out b/test_regress/t/t_cover_branch_option.out deleted file mode 100644 index 167e21908..000000000 --- a/test_regress/t/t_cover_branch_option.out +++ /dev/null @@ -1,457 +0,0 @@ -// // verilator_coverage annotation - // DESCRIPTION: Verilator: Verilog Test module - // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2008 by Wilson Snyder. - // SPDX-License-Identifier: CC0-1.0 - - module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - reg toggle; - initial toggle=0; - - integer cyc; - initial cyc=1; - - wire [7:0] cyc_copy = cyc[7:0]; - - alpha a1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - alpha a2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - beta b2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - tsk t1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - tab tab1 (/*AUTOINST*/ - // Inputs - .clk (clk)); - par par1 (/*AUTOINST*/); - cond cond1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .cyc (cyc)); - - always @ (posedge clk) begin -~000010 if (cyc!=0) begin -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t - 000010 cyc <= cyc + 1; -+000010 point: comment=if hier=top.t - 000010 toggle <= '0; -+000010 point: comment=if hier=top.t - // Single and multiline if -%000009 if (cyc==3) $write(""); --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t -%000009 if (cyc==3) --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t -%000001 begin --000001 point: comment=if hier=top.t -%000001 $write(""); --000001 point: comment=if hier=top.t - end - // Single and multiline else -%000009 if (cyc==3) ; else $write(""); --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t -%000009 if (cyc==3) ; --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t - else -%000009 begin --000009 point: comment=else hier=top.t -%000009 $write(""); --000009 point: comment=else hier=top.t - end - // Single and multiline if else -%000009 if (cyc==3) $write(""); else $write(""); --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t -%000009 if (cyc==3) --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t -%000001 begin --000001 point: comment=if hier=top.t -%000001 $write(""); --000001 point: comment=if hier=top.t - end - else -%000009 begin --000009 point: comment=else hier=top.t -%000009 $write(""); --000009 point: comment=else hier=top.t - end - // multiline elseif - if (cyc==3) - begin - $write(""); - end - else if (cyc==4) - begin - $write(""); - end - else if (cyc==5) - begin - $write(""); - end - else - begin - $write(""); - end - // Single and multiline while - while (0); - while (0) begin - $write(""); - end - do ; while (0); - 000010 do begin -+000010 point: comment=if hier=top.t - 000010 $write(""); -+000010 point: comment=if hier=top.t - end while (0); - //=== - // Task and complicated - if (cyc==3) begin - toggle <= '1; - end - else if (cyc==5) begin - `ifdef VERILATOR - $c("this->call_task();"); - `else - call_task(); - `endif - end -%000007 else if (cyc==10) begin --000001 point: comment=if hier=top.t --000007 point: comment=else hier=top.t -%000001 $write("*-* All Finished *-*\n"); --000001 point: comment=if hier=top.t -%000001 $finish; --000001 point: comment=if hier=top.t - end - end - end - - task call_task; - /* verilator public */ - t1.center_task(1'b1); - endtask - - endmodule - - module alpha (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - always @ (posedge clk) begin -~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) --000002 point: comment=if hier=top.t.a* -+000018 point: comment=else hier=top.t.a* -%000002 $write(""); --000002 point: comment=if hier=top.t.a* - // t.a1 and t.a2 collapse to a count of 2 - end - if (toggle) begin // *** t_cover_line.vlt turns this off - $write(""); // CHECK_COVER_MISSING(0) - // This doesn't even get added - `ifdef ATTRIBUTE - // verilator coverage_block_off - `endif - end - end - endmodule - - module beta (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - - /* verilator public_module */ - - always @ (posedge clk) begin - $write(""); // Always covered -~000020 if (0) begin // CHECK_COVER(0,"top.t.b*",0) --000000 point: comment=if hier=top.t.b* -+000020 point: comment=else hier=top.t.b* - // Make sure that we don't optimize away zero buckets -%000000 $write(""); --000000 point: comment=if hier=top.t.b* - end -~000018 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) --000002 point: comment=if hier=top.t.b* -+000018 point: comment=else hier=top.t.b* - // t.b1 and t.b2 collapse to a count of 2 -%000002 $write(""); --000002 point: comment=if hier=top.t.b* - end - if (toggle) begin : block - // This doesn't - `ifdef ATTRIBUTE - // verilator coverage_block_off - `endif - begin end // *** t_cover_line.vlt turns this off (so need begin/end) - if (1) begin end // CHECK_COVER_MISSING(0) - $write(""); // CHECK_COVER_MISSING(0) - end - end - endmodule - - class Cls; - bit m_toggle; - function new(bit toggle); - m_toggle = toggle; -%000001 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) --000001 point: comment=if hier=top.$unit::Cls__Vclpkg --000000 point: comment=else hier=top.$unit::Cls__Vclpkg -%000001 $write(""); --000001 point: comment=if hier=top.$unit::Cls__Vclpkg - end - endfunction - static function void fstatic(bit toggle); -~000011 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg --000000 point: comment=else hier=top.$unit::Cls__Vclpkg - 000011 $write(""); -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg - end - endfunction - function void fauto(); -~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg --000000 point: comment=else hier=top.$unit::Cls__Vclpkg - 000011 $write(""); -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg - end - endfunction - endclass - - module tsk (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - - /* verilator public_module */ - - always @ (posedge clk) begin - center_task(1'b0); - end - - task center_task; - input external; - begin -~000010 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) --000001 point: comment=if hier=top.t.t1 -+000010 point: comment=else hier=top.t.t1 -%000001 $write(""); --000001 point: comment=if hier=top.t.t1 - end -~000010 if (external) begin // CHECK_COVER(0,"top.t.t1",1) --000001 point: comment=if hier=top.t.t1 -+000010 point: comment=else hier=top.t.t1 -%000001 $write("[%0t] Got external pulse\n", $time); --000001 point: comment=if hier=top.t.t1 - end - end - begin - Cls c = new(1'b1); - c.fauto(); - Cls::fstatic(1'b1); - end - endtask - endmodule - - module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - - // verilator coverage_off - always @ (posedge clk) begin - if (toggle) begin - $write(""); // CHECK_COVER_MISSING(0) - // because under coverage_module_off - end - end - // verilator coverage_on - always @ (posedge clk) begin -%000009 if (toggle) begin --000001 point: comment=if hier=top.t.o1 --000009 point: comment=else hier=top.t.o1 - // because under coverage_module_off -%000001 $write(""); --000001 point: comment=if hier=top.t.o1 -%000001 if (0) ; // CHECK_COVER(0,"top.t.o1",1) --000000 point: comment=if hier=top.t.o1 --000001 point: comment=else hier=top.t.o1 - end - end - endmodule - - module tab (input clk); - bit [3:0] cyc4; - int decoded; - - always @ (posedge clk) begin - case (cyc4) - 1: decoded = 10; - 2: decoded = 20; - 3: decoded = 30; - 4: decoded = 40; - 5: decoded = 50; - default: decoded = 0; - endcase - end - - always @ (posedge clk) begin - cyc4 <= cyc4 + 1; - end - endmodule - - module par(); - localparam int CALLS_FUNC = param_func(1); - - // We don't currently count elaboration time use towards coverage. This - // seems safer for functions used both at elaboration time and not - but may - // revisit this. - function automatic int param_func(int i); -%000000 if (i == 0) begin --000000 point: comment=if hier=top.t.par1 --000000 point: comment=else hier=top.t.par1 -%000000 i = 99; // Uncovered --000000 point: comment=if hier=top.t.par1 - end -%000000 else begin --000000 point: comment=else hier=top.t.par1 -%000000 i = i + 1; --000000 point: comment=else hier=top.t.par1 - end - return i; - endfunction - - endmodule - - package my_pkg; - int x = 1 ? 1 : 0; - endpackage - - class Getter1; - function int get_1; - return 1; - endfunction - endclass - - module cond(input logic clk, input int cyc); - logic a, b, c, d, e, f, g, h, k, l, m; - logic [5:0] tab; - typedef logic [7:0] arr_t[1:0]; - arr_t data[1:0]; - Getter1 getter1 = new; - string s; - - function logic func_side_effect; - $display("SIDE EFFECT"); - return 1; - endfunction - - function arr_t get_arr; - arr_t arr; - return arr; - endfunction - -~000031 assign a = (cyc == 0) ? clk : 1'bz; --000000 point: comment=cond_then hier=top.t.cond1 -+000031 point: comment=cond_else hier=top.t.cond1 -~000028 assign b = (cyc == 1) ? clk : 0; --000003 point: comment=cond_then hier=top.t.cond1 -+000028 point: comment=cond_else hier=top.t.cond1 -~000021 assign c = func_side_effect() ? clk : 0; -+000021 point: comment=cond_then hier=top.t.cond1 --000000 point: comment=cond_else hier=top.t.cond1 - always @(posedge clk) begin -%000007 d = (cyc % 3 == 0) ? 1 : 0; --000003 point: comment=cond_then hier=top.t.cond1 --000007 point: comment=cond_else hier=top.t.cond1 -~000010 s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); --000000 point: comment=cond_then hier=top.t.cond1 -+000010 point: comment=cond_else hier=top.t.cond1 - end -~000019 assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; -+000012 point: comment=cond_then hier=top.t.cond1 -+000019 point: comment=cond_else hier=top.t.cond1 --000007 point: comment=cond_then hier=top.t.cond1 --000005 point: comment=cond_else hier=top.t.cond1 - - // ternary operator in condition shouldn't be included to the coverae -~000011 assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; -+000011 point: comment=cond_then hier=top.t.cond1 --000000 point: comment=cond_else hier=top.t.cond1 - // the same as in index - assign tab[clk ? 1 : 0] = 1; - assign m = tab[clk ? 3 : 4]; - - for (genvar i = 0; i < 2; i++) begin - 000011 assign g = clk ? 1 : 0; -+000010 point: comment=cond_then hier=top.t.cond1 -+000011 point: comment=cond_else hier=top.t.cond1 - end - - always begin -~000010 if (cyc == 5) h = cyc > 5 ? 1 : 0; --000000 point: comment=cond_then hier=top.t.cond1 --000001 point: comment=cond_else hier=top.t.cond1 --000001 point: comment=if hier=top.t.cond1 -+000010 point: comment=else hier=top.t.cond1 - 000010 else h = 1; -+000010 point: comment=else hier=top.t.cond1 - -~000010 data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); --000001 point: comment=cond_then hier=top.t.cond1 -+000010 point: comment=cond_else hier=top.t.cond1 - - // ternary operator in conditions should be skipped - for (int i = 0; (i < 5) ? 1 : 0; i++) begin - k = 1'(i); - end - for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin - k = 1'(i); - end - -~000011 if (k ? 1 : 0) k = 1; --000000 point: comment=if hier=top.t.cond1 -+000011 point: comment=else hier=top.t.cond1 - 000011 else k = 0; -+000011 point: comment=else hier=top.t.cond1 - end - endmodule - diff --git a/test_regress/t/t_cover_branch_option.py b/test_regress/t/t_cover_branch_option.py deleted file mode 100755 index a699cf538..000000000 --- a/test_regress/t/t_cover_branch_option.py +++ /dev/null @@ -1,53 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_cover_line.v" -test.golden_filename = "t/t_cover_branch_option.out" - -test.compile(verilator_flags2=['--cc --coverage +define+ATTRIBUTE']) - -test.execute() - -test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", - "--annotate-points", - "--annotate", test.obj_dir + "/annotated", - "--filter-type branch", - test.obj_dir + "/coverage.dat"], - verilator_run=True) # yapf:disable - -test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) - -# Also try lcov -test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", - "--write-info", test.obj_dir + "/coverage.info", - "--filter-type branch", - test.obj_dir + "/coverage.dat"], - verilator_run=True) # yapf:disable - -test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") - -# If installed -nout = test.run_capture("lcov --version", check=False) -version_match = re.search(r'version ([0-9.]+)', nout, re.IGNORECASE) -if not version_match: - test.skip("lcov or genhtml not installed") - -if float(version_match.group(1)) < 1.14: - test.skip("lcov or genhtml too old (version " + version_match.group(1) + - ", need version >= 1.14") - -test.run(cmd=[ - "genhtml", test.obj_dir + "/coverage.info", "--branch-coverage", "--output-directory " + - test.obj_dir + "/html" -]) - -test.passes() diff --git a/test_regress/t/t_cover_expr_option.out b/test_regress/t/t_cover_expr_option.out deleted file mode 100644 index 7f74da584..000000000 --- a/test_regress/t/t_cover_expr_option.out +++ /dev/null @@ -1,353 +0,0 @@ -// // verilator_coverage annotation - // DESCRIPTION: Verilator: Verilog Test module - // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2024 by Wilson Snyder. - // SPDX-License-Identifier: CC0-1.0 - - class cls; - rand int x; - endclass - - module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - integer cyc; - initial cyc=1; - - logic [63:32] cyc2; - always_comb cyc2 = cyc; - - integer some_int; - integer other_int; - logic some_bool; - - wire t1 = cyc[0]; - wire t2 = cyc[1]; - wire t3 = cyc[2]; - wire t4 = cyc[3]; - - localparam bit ONE = 1'b1; - localparam bit ZERO = 1'b0; - - function automatic bit invert(bit x); - 000015 return ~x; -+000012 point: comment=(x==0) => 1 hier=top.t -+000015 point: comment=(x==1) => 0 hier=top.t - endfunction - - function automatic bit and_oper(bit a, bit b); -%000005 return a & b; --000004 point: comment=(a==0) => 0 hier=top.t --000002 point: comment=(a==1 && b==1) => 1 hier=top.t --000005 point: comment=(b==0) => 0 hier=top.t - endfunction - - localparam int num_intfs = 4; - intf the_intfs [num_intfs-1:0] (); - genvar intf_i; - for (intf_i = 0; intf_i < num_intfs; intf_i++) begin - always_comb the_intfs[intf_i].t = cyc[intf_i]; - end - - always @ (posedge clk) begin - cyc <= cyc + 1; -%000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); --000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -%000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); --000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t --000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t --000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t --000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t -%000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); --000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t --000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t --000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t --000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t -%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t -%000005 if (t3 && (t1 == t2)) $write(""); --000005 point: comment=((t1 == t2)==0) => 0 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t --000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t -%000005 if (123 == (124 - 32'(t1 || t2))) $write(""); --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t -%000004 some_int <= (t2 || t3) ? 345 : 567; --000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t --000004 point: comment=(t3==1) => 1 hier=top.t -%000005 some_bool <= t1 && t2; --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t -%000005 if (t1 & t2) $write(""); --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t -%000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t -%000003 if (t1 ^ t2) $write(""); --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t -%000005 if (~(t1 & t2)) $write(""); --000004 point: comment=(t1==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 1 hier=top.t -%000004 if (t1 -> t2) $write(""); --000004 point: comment=(t1==0) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t -%000003 if (t1 <-> t2) $write(""); --000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -%000005 if (&cyc[2:0]) $write(""); --000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t --000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t -%000007 if (&cyc[3:2]) $write(""); --000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t --000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t --000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t -%000005 if (|cyc[2:0]) $write(""); --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t -%000002 if (^cyc[2:0]) $write(""); --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t --000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -%000005 if (|cyc[2:0] || cyc[3]) $write(""); --000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t --000002 point: comment=(cyc[3]==1) => 1 hier=top.t -%000005 if (t1 & t2 & 1'b1) $write(""); --000000 point: comment=(1'h1==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t -%000009 if (t1 & t2 & 1'b0) $write(""); --000009 point: comment=(1'h0==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t -%000005 if (t1 & t2 & ONE) $write(""); --000000 point: comment=(ONE==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t -%000009 if (t1 & t2 & ZERO) $write(""); --000009 point: comment=(ZERO==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t -%000005 if (t1 && t2) begin --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t - $write(""); -%000003 end else if (t1 || t2) begin --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000003 point: comment=(t1==1) => 1 hier=top.t --000002 point: comment=(t2==1) => 1 hier=top.t - $write(""); - end -%000005 if (invert(t1) && t2) $write(""); --000005 point: comment=(invert(t1)==0) => 0 hier=top.t --000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t - if (and_oper(t1, t2)) $write(""); -%000005 if (t2 && t3) begin --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t -%000001 if (t1 && t2) $write(""); --000001 point: comment=(t1==0) => 0 hier=top.t --000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t - end - if (0 == 1) begin - for (int loop_var = 0; loop_var < 1; loop_var++) begin -%000000 if (cyc[loop_var] && t2) $write(""); --000000 point: comment=(cyc[loop_var[4:0]+:32'h1]]==0) => 0 hier=top.t --000000 point: comment=(cyc[loop_var[4:0]+:32'h1]]==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t - end - end - // stop at the first layer even if there's more to find -%000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); --000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:32'sh2]] == cyc[(32'sh5 + (t3 || t4))[4:0]+:32'sh2]])==0 && cyc[31]==0) => 0 hier=top.t --000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:32'sh2]] == cyc[(32'sh5 + (t3 || t4))[4:0]+:32'sh2]])==1) => 1 hier=top.t --000000 point: comment=(cyc[31]==1) => 1 hier=top.t - // impossible branches and redundant terms -%000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); --000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t --000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t -%000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); --000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t - // demonstrate current limitations of term matching scheme -%000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); --000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:32'h1]]==1 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:32'h1]]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:32'h1]]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:32'h1]]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:32'h1]]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:32'h1]]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t - //verilator coverage_off - if (t1 && t2) $write(""); - //verilator coverage_on - if ((~t1 && t2) -%000004 || --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t - (~t3 && t4)) $write(""); - // intentionally testing wonkified expression terms - if ( - cyc[ - 0 -%000005 ] & --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t - cyc - [1]) $write(""); - // for now each ternary condition is considered in isolation -%000005 other_int <= t1 ? t2 ? 1 : 2 : 3; --000004 point: comment=(t1==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t - // no expression coverage for multi-bit expressions - if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); - // truth table is too large - if (^cyc[6:0]) $write(""); - // this one is too big even for t_cover_expr_max - if (^cyc) $write(""); - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - always_comb begin -%000005 if (t1 && t2) $write(""); --000005 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t - end - - logic ta, tb, tc; - initial begin - cls obj = new; - cls null_obj = null; - int q[5]; - int qv[$]; - - q = '{1, 2, 2, 4, 3}; - // lambas not handled - // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) - // tracing_off does not work around the bug - qv = q.find_first with (item[0] & item[1]); - ta = '1; - tb = '0; - tc = '0; -%000001 while (ta || tb || tc) begin --000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t --000000 point: comment=(ta==1) => 1 hier=top.t --000000 point: comment=(tb==1) => 1 hier=top.t --000000 point: comment=(tc==1) => 1 hier=top.t - tc = tb; - tb = ta; - ta = '0; - end - if (!bit'(obj.randomize() with {x < 100;})) $write(""); - if (null_obj != null && null_obj.x == 5) $write(""); - end - - sub the_sub_1 (.p(t1), .q(t2)); - sub the_sub_2 (.p(t3), .q(t4)); - // TODO -- non-process expressions - sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); - - // TODO - // pragma for expr coverage off / on - // investigate cover point sorting in annotated source - // consider reporting don't care terms - // - // Branches which are statically impossible to reach are still reported. - // E.g. - // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t - // These could potentially be pruned, but they currently follow suit for - // what branch coverage does. Perhaps a switch should be added to not - // count statically impossible things. - - endmodule - - module sub ( - input p, - input q - ); - - always_comb begin -~000019 if (p && q) $write(""); -+000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* --000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* -+000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* - end - - endmodule - - interface intf(); - logic t; - endinterface - diff --git a/test_regress/t/t_cover_expr_option.py b/test_regress/t/t_cover_expr_option.py deleted file mode 100755 index 92e537cde..000000000 --- a/test_regress/t/t_cover_expr_option.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap -from pathlib import Path - -test.scenarios('simulator') - -test.top_filename = "t/t_cover_expr.v" -test.golden_filename = "t/t_cover_expr_option.out" - -test.compile(verilator_flags2=['--cc', '--coverage']) - -test.execute() - -# Read the input .v file and do any CHECK_COVER requests -test.inline_checks() - -test.run(cmd=[ - os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", - "--filter-type expr", - "--annotate-points", - "--annotate", - test.obj_dir + "/annotated", - test.obj_dir + "/coverage.dat", -], - verilator_run=True) - -top = Path(test.top_filename) -test.files_identical(test.obj_dir + f"/annotated/{top.name}", test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_cover_line_option.out b/test_regress/t/t_cover_line_option.out deleted file mode 100644 index f02558ba2..000000000 --- a/test_regress/t/t_cover_line_option.out +++ /dev/null @@ -1,444 +0,0 @@ -// // verilator_coverage annotation - // DESCRIPTION: Verilator: Verilog Test module - // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2008 by Wilson Snyder. - // SPDX-License-Identifier: CC0-1.0 - - module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - reg toggle; -%000001 initial toggle=0; --000001 point: comment=block hier=top.t - - integer cyc; -%000001 initial cyc=1; --000001 point: comment=block hier=top.t - - wire [7:0] cyc_copy = cyc[7:0]; - - alpha a1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - alpha a2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - beta b2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - tsk t1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - tab tab1 (/*AUTOINST*/ - // Inputs - .clk (clk)); - par par1 (/*AUTOINST*/); - cond cond1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .cyc (cyc)); - - 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t - if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= '0; - // Single and multiline if - if (cyc==3) $write(""); - if (cyc==3) - begin - $write(""); - end - // Single and multiline else - if (cyc==3) ; else $write(""); - if (cyc==3) ; - else - begin - $write(""); - end - // Single and multiline if else - if (cyc==3) $write(""); else $write(""); - if (cyc==3) - begin - $write(""); - end - else - begin - $write(""); - end - // multiline elseif -%000001 if (cyc==3) --000001 point: comment=elsif hier=top.t -%000001 begin --000001 point: comment=elsif hier=top.t -%000001 $write(""); --000001 point: comment=elsif hier=top.t - end -%000001 else if (cyc==4) --000001 point: comment=elsif hier=top.t -%000001 begin --000001 point: comment=elsif hier=top.t -%000001 $write(""); --000001 point: comment=elsif hier=top.t - end -%000007 else if (cyc==5) --000001 point: comment=if hier=top.t --000007 point: comment=else hier=top.t -%000001 begin --000001 point: comment=if hier=top.t -%000001 $write(""); --000001 point: comment=if hier=top.t - end - else -%000007 begin --000007 point: comment=else hier=top.t -%000007 $write(""); --000007 point: comment=else hier=top.t - end - // Single and multiline while -%000000 while (0); --000000 point: comment=block hier=top.t -%000000 while (0) begin --000000 point: comment=block hier=top.t -%000000 $write(""); --000000 point: comment=block hier=top.t - end -%000000 do ; while (0); --000000 point: comment=block hier=top.t -%000000 do begin --000000 point: comment=block hier=top.t -%000000 $write(""); --000000 point: comment=block hier=top.t -%000000 end while (0); --000000 point: comment=block hier=top.t - //=== - // Task and complicated -%000001 if (cyc==3) begin --000001 point: comment=elsif hier=top.t -%000001 toggle <= '1; --000001 point: comment=elsif hier=top.t - end -%000001 else if (cyc==5) begin --000001 point: comment=elsif hier=top.t - `ifdef VERILATOR -%000001 $c("this->call_task();"); --000001 point: comment=elsif hier=top.t - `else - call_task(); - `endif - end - else if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end - -%000001 task call_task; --000001 point: comment=block hier=top.t - /* verilator public */ -%000001 t1.center_task(1'b1); --000001 point: comment=block hier=top.t - endtask - - endmodule - - module alpha (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - 000020 always @ (posedge clk) begin -+000020 point: comment=block hier=top.t.a* - if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) - $write(""); - // t.a1 and t.a2 collapse to a count of 2 - end - 000018 if (toggle) begin // *** t_cover_line.vlt turns this off -+000018 point: comment=else hier=top.t.a* - $write(""); // CHECK_COVER_MISSING(0) - // This doesn't even get added - `ifdef ATTRIBUTE - // verilator coverage_block_off - `endif - end - end - endmodule - - module beta (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - - /* verilator public_module */ - - 000020 always @ (posedge clk) begin -+000020 point: comment=block hier=top.t.b* - 000020 $write(""); // Always covered -+000020 point: comment=block hier=top.t.b* - if (0) begin // CHECK_COVER(0,"top.t.b*",0) - // Make sure that we don't optimize away zero buckets - $write(""); - end - if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) - // t.b1 and t.b2 collapse to a count of 2 - $write(""); - end - 000018 if (toggle) begin : block -+000018 point: comment=else hier=top.t.b* - // This doesn't - `ifdef ATTRIBUTE - // verilator coverage_block_off - `endif - begin end // *** t_cover_line.vlt turns this off (so need begin/end) - if (1) begin end // CHECK_COVER_MISSING(0) - $write(""); // CHECK_COVER_MISSING(0) - end - end - endmodule - - class Cls; - bit m_toggle; -%000001 function new(bit toggle); --000001 point: comment=block hier=top.$unit::Cls__Vclpkg -%000001 m_toggle = toggle; --000001 point: comment=block hier=top.$unit::Cls__Vclpkg - if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) - $write(""); - end - endfunction - 000011 static function void fstatic(bit toggle); -+000011 point: comment=block hier=top.$unit::Cls__Vclpkg - if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) - $write(""); - end - endfunction - 000011 function void fauto(); -+000011 point: comment=block hier=top.$unit::Cls__Vclpkg - if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) - $write(""); - end - endfunction - endclass - - module tsk (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - - /* verilator public_module */ - - 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t.t1 - 000010 center_task(1'b0); -+000010 point: comment=block hier=top.t.t1 - end - - 000011 task center_task; -+000011 point: comment=block hier=top.t.t1 - input external; - 000011 begin -+000011 point: comment=block hier=top.t.t1 - if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) - $write(""); - end - if (external) begin // CHECK_COVER(0,"top.t.t1",1) - $write("[%0t] Got external pulse\n", $time); - end - end - 000011 begin -+000011 point: comment=block hier=top.t.t1 -%000001 Cls c = new(1'b1); --000001 point: comment=block hier=top.t.t1 - 000011 c.fauto(); -+000011 point: comment=block hier=top.t.t1 - 000011 Cls::fstatic(1'b1); -+000011 point: comment=block hier=top.t.t1 - end - endtask - endmodule - - module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - - // verilator coverage_off - always @ (posedge clk) begin - if (toggle) begin - $write(""); // CHECK_COVER_MISSING(0) - // because under coverage_module_off - end - end - // verilator coverage_on - 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t.o1 - if (toggle) begin - // because under coverage_module_off - $write(""); - if (0) ; // CHECK_COVER(0,"top.t.o1",1) - end - end - endmodule - - module tab (input clk); - bit [3:0] cyc4; - int decoded; - - 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t.tab1 - 000010 case (cyc4) -+000010 point: comment=block hier=top.t.tab1 -%000001 1: decoded = 10; --000001 point: comment=case hier=top.t.tab1 -%000001 2: decoded = 20; --000001 point: comment=case hier=top.t.tab1 -%000001 3: decoded = 30; --000001 point: comment=case hier=top.t.tab1 -%000001 4: decoded = 40; --000001 point: comment=case hier=top.t.tab1 -%000001 5: decoded = 50; --000001 point: comment=case hier=top.t.tab1 -%000005 default: decoded = 0; --000005 point: comment=case hier=top.t.tab1 - endcase - end - - 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t.tab1 - 000010 cyc4 <= cyc4 + 1; -+000010 point: comment=block hier=top.t.tab1 - end - endmodule - - module par(); - localparam int CALLS_FUNC = param_func(1); - - // We don't currently count elaboration time use towards coverage. This - // seems safer for functions used both at elaboration time and not - but may - // revisit this. -%000000 function automatic int param_func(int i); --000000 point: comment=block hier=top.t.par1 - if (i == 0) begin - i = 99; // Uncovered - end - else begin - i = i + 1; - end -%000000 return i; --000000 point: comment=block hier=top.t.par1 - endfunction - - endmodule - - package my_pkg; -%000001 int x = 1 ? 1 : 0; --000001 point: comment=block hier=top.my_pkg - endpackage - -%000001 class Getter1; --000001 point: comment=block hier=top.$unit::Getter1__Vclpkg - 000020 function int get_1; -+000020 point: comment=block hier=top.$unit::Getter1__Vclpkg - 000020 return 1; -+000020 point: comment=block hier=top.$unit::Getter1__Vclpkg - endfunction - endclass - - module cond(input logic clk, input int cyc); - logic a, b, c, d, e, f, g, h, k, l, m; - logic [5:0] tab; - typedef logic [7:0] arr_t[1:0]; - arr_t data[1:0]; -%000001 Getter1 getter1 = new; --000001 point: comment=block hier=top.t.cond1 - string s; - - 000021 function logic func_side_effect; -+000021 point: comment=block hier=top.t.cond1 - 000021 $display("SIDE EFFECT"); -+000021 point: comment=block hier=top.t.cond1 - 000021 return 1; -+000021 point: comment=block hier=top.t.cond1 - endfunction - - 000010 function arr_t get_arr; -+000010 point: comment=block hier=top.t.cond1 - arr_t arr; - 000010 return arr; -+000010 point: comment=block hier=top.t.cond1 - endfunction - - assign a = (cyc == 0) ? clk : 1'bz; - assign b = (cyc == 1) ? clk : 0; - assign c = func_side_effect() ? clk : 0; - 000010 always @(posedge clk) begin -+000010 point: comment=block hier=top.t.cond1 - 000010 d = (cyc % 3 == 0) ? 1 : 0; -+000010 point: comment=block hier=top.t.cond1 - 000010 s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); -+000010 point: comment=block hier=top.t.cond1 - end - assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; - - // ternary operator in condition shouldn't be included to the coverae - assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; - // the same as in index - assign tab[clk ? 1 : 0] = 1; - assign m = tab[clk ? 3 : 4]; - - for (genvar i = 0; i < 2; i++) begin - assign g = clk ? 1 : 0; - end - - 000011 always begin -+000011 point: comment=block hier=top.t.cond1 - if (cyc == 5) h = cyc > 5 ? 1 : 0; - else h = 1; - - 000011 data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); -+000011 point: comment=block hier=top.t.cond1 - - // ternary operator in conditions should be skipped - 000055 for (int i = 0; (i < 5) ? 1 : 0; i++) begin -+000011 point: comment=block hier=top.t.cond1 -+000055 point: comment=block hier=top.t.cond1 - 000055 k = 1'(i); -+000055 point: comment=block hier=top.t.cond1 - end - 000044 for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin -+000011 point: comment=block hier=top.t.cond1 -+000044 point: comment=block hier=top.t.cond1 - 000044 k = 1'(i); -+000044 point: comment=block hier=top.t.cond1 - end - - if (k ? 1 : 0) k = 1; - else k = 0; - end - endmodule - diff --git a/test_regress/t/t_cover_line_option.py b/test_regress/t/t_cover_line_option.py deleted file mode 100755 index f729b2539..000000000 --- a/test_regress/t/t_cover_line_option.py +++ /dev/null @@ -1,53 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_cover_line.v" -test.golden_filename = "t/t_cover_line_option.out" - -test.compile(verilator_flags2=['--cc --coverage +define+ATTRIBUTE']) - -test.execute() - -test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", - "--annotate-points", - "--annotate", test.obj_dir + "/annotated", - "--filter-type line", - test.obj_dir + "/coverage.dat"], - verilator_run=True) # yapf:disable - -test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) - -# Also try lcov -test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", - "--write-info", test.obj_dir + "/coverage.info", - "--filter-type line", - test.obj_dir + "/coverage.dat"], - verilator_run=True) # yapf:disable - -test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") - -# If installed -nout = test.run_capture("lcov --version", check=False) -version_match = re.search(r'version ([0-9.]+)', nout, re.IGNORECASE) -if not version_match: - test.skip("lcov or genhtml not installed") - -if float(version_match.group(1)) < 1.14: - test.skip("lcov or genhtml too old (version " + version_match.group(1) + - ", need version >= 1.14") - -test.run(cmd=[ - "genhtml", test.obj_dir + "/coverage.info", "--branch-coverage", "--output-directory " + - test.obj_dir + "/html" -]) - -test.passes() diff --git a/test_regress/t/t_cover_toggle_option.out b/test_regress/t/t_cover_toggle_option.out deleted file mode 100644 index d68a87d6d..000000000 --- a/test_regress/t/t_cover_toggle_option.out +++ /dev/null @@ -1,211 +0,0 @@ -// // verilator_coverage annotation - // DESCRIPTION: Verilator: Verilog Test module - // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2008 by Wilson Snyder. - // SPDX-License-Identifier: CC0-1.0 - - module t (/*AUTOARG*/ - // Inputs - clk, check_real, check_array_real, check_string - ); - - 000019 input clk; - input real check_real; // Check issue #2741 - input real check_array_real [1:0]; - input string check_string; // Check issue #2766 - - typedef struct packed { - union packed { - logic ua; - logic ub; - } u; - logic b; - } str_t; - -%000002 reg toggle; initial toggle='0; - -%000002 str_t stoggle; initial stoggle='0; - - union { - real val1; // TODO use bit [7:0] here - real val2; // TODO use bit [3:0] here - } utoggle; - - const reg aconst = '0; - -%000002 reg [1:0][1:0] ptoggle; initial ptoggle=0; - - integer cyc; initial cyc=1; -~000011 wire [7:0] cyc_copy = cyc[7:0]; -%000002 wire toggle_up; - - typedef struct { - int q[$]; - } str_queue_t; - str_queue_t str_queue; - - alpha a1 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); - alpha a2 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); - - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle_up (toggle_up)); - - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - - param#(1) p1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - - param#() p2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - -%000001 reg [1:0] memory[121:110]; - - wire [1023:0] largeish = {992'h0, cyc}; - // CHECK_COVER_MISSING(-1) - - always @ (posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; - memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; - toggle <= '0; - stoggle.u <= toggle; - stoggle.b <= toggle; - utoggle.val1 <= real'(cyc[7:0]); - ptoggle[0][0] <= toggle; - if (cyc == 3) begin - str_queue.q.push_back(1); - toggle <= '1; - end - if (cyc == 4) begin - if (str_queue.q.size() != 1) $stop; - toggle <= '0; - end - else if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end - - endmodule - - module alpha (/*AUTOARG*/ - // Outputs - toggle_up, - // Inputs - clk, toggle, cyc_copy - ); - - // t.a1 and t.a2 collapse to a count of 2 - - 000038 input clk; - -%000004 input toggle; - // CHECK_COVER(-1,"top.t.a*",4) - // 2 edges * (t.a1 and t.a2) - -~000022 input [7:0] cyc_copy; - // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22) - // CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10) - // CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4) - // CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2) - // CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0) - // CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0) - // CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0) - // CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0) - -%000004 reg toggle_internal; - // CHECK_COVER(-1,"top.t.a*",4) - // 2 edges * (t.a1 and t.a2) - -%000004 output reg toggle_up; - // CHECK_COVER(-1,"top.t.a*",4) - // 2 edges * (t.a1 and t.a2) - - always @ (posedge clk) begin - toggle_internal <= toggle; - toggle_up <= toggle; - end - endmodule - - module beta (/*AUTOARG*/ - // Inputs - clk, toggle_up - ); - - 000019 input clk; - -%000002 input toggle_up; - // CHECK_COVER(-1,"top.t.b1","toggle_up",2) - - /* verilator public_module */ - - always @ (posedge clk) begin - if (0 && toggle_up) begin end - end - endmodule - - module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); - - // verilator coverage_off - input clk; - // CHECK_COVER_MISSING(-1) - - // verilator coverage_on -%000002 input toggle; - // CHECK_COVER(-1,"top.t.o1","toggle",2) - - endmodule - - module param #(parameter P = 2) (/*AUTOARG*/ - // Inputs - clk, toggle - ); - - 000019 input clk; -%000002 input toggle; - -%000001 logic z; - - for (genvar i = 0; i < P; i++) begin -%000002 logic x; - always @ (posedge clk) begin - x <= toggle; - end - for (genvar j = 0; j < 3; j++) begin -%000003 logic [2:0] y; - always @ (negedge clk) begin - y <= {toggle, ~toggle, 1'b1}; - end - end - end - if (P > 1) begin : gen_1 - assign z = 1; - end - endmodule - diff --git a/test_regress/t/t_cover_toggle_option.py b/test_regress/t/t_cover_toggle_option.py deleted file mode 100755 index 589c46fdb..000000000 --- a/test_regress/t/t_cover_toggle_option.py +++ /dev/null @@ -1,52 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.top_filename = "t/t_cover_toggle.v" - -test.compile(verilator_flags2=['--cc --coverage --stats']) - -test.execute() - -# Read the input .v file and do any CHECK_COVER requests -test.inline_checks() - -test.file_grep_not(test.obj_dir + "/coverage.dat", "largeish") - -if test.vlt_all: - test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 27) - -test.run(cmd=[ - os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", - "--annotate", - test.obj_dir + "/annotated", - test.obj_dir + "/coverage.dat", - "--filter-type toggle", -], - verilator_run=True) - -test.files_identical(test.obj_dir + "/annotated/t_cover_toggle.v", test.golden_filename) - -test.run(cmd=[ - os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", - "--annotate-points", - "--annotate", - test.obj_dir + "/annotated-points", - test.obj_dir + "/coverage.dat", - "--filter-type toggle", -], - verilator_run=True) - -test.files_identical(test.obj_dir + "/annotated-points/t_cover_toggle.v", - "t/" + test.name + "__points.out") - -test.passes() diff --git a/test_regress/t/t_cover_toggle_option__points.out b/test_regress/t/t_cover_toggle_option__points.out deleted file mode 100644 index f73846a2f..000000000 --- a/test_regress/t/t_cover_toggle_option__points.out +++ /dev/null @@ -1,303 +0,0 @@ -// // verilator_coverage annotation - // DESCRIPTION: Verilator: Verilog Test module - // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2008 by Wilson Snyder. - // SPDX-License-Identifier: CC0-1.0 - - module t (/*AUTOARG*/ - // Inputs - clk, check_real, check_array_real, check_string - ); - - 000019 input clk; -+000019 point: comment=clk hier=top.t - input real check_real; // Check issue #2741 - input real check_array_real [1:0]; - input string check_string; // Check issue #2766 - - typedef struct packed { - union packed { - logic ua; - logic ub; - } u; - logic b; - } str_t; - -%000002 reg toggle; initial toggle='0; --000002 point: comment=toggle hier=top.t - -%000002 str_t stoggle; initial stoggle='0; --000002 point: comment=stoggle.b hier=top.t --000002 point: comment=stoggle.u.ua hier=top.t - - union { - real val1; // TODO use bit [7:0] here - real val2; // TODO use bit [3:0] here - } utoggle; - - const reg aconst = '0; - -%000002 reg [1:0][1:0] ptoggle; initial ptoggle=0; --000002 point: comment=ptoggle[0][0] hier=top.t --000000 point: comment=ptoggle[0][1] hier=top.t --000000 point: comment=ptoggle[1][0] hier=top.t --000000 point: comment=ptoggle[1][1] hier=top.t - - integer cyc; initial cyc=1; -~000011 wire [7:0] cyc_copy = cyc[7:0]; -+000011 point: comment=cyc_copy[0] hier=top.t --000005 point: comment=cyc_copy[1] hier=top.t --000002 point: comment=cyc_copy[2] hier=top.t --000001 point: comment=cyc_copy[3] hier=top.t --000000 point: comment=cyc_copy[4] hier=top.t --000000 point: comment=cyc_copy[5] hier=top.t --000000 point: comment=cyc_copy[6] hier=top.t --000000 point: comment=cyc_copy[7] hier=top.t -%000002 wire toggle_up; --000002 point: comment=toggle_up hier=top.t - - typedef struct { - int q[$]; - } str_queue_t; - str_queue_t str_queue; - - alpha a1 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); - alpha a2 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); - - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle_up (toggle_up)); - - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - - param#(1) p1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - - param#() p2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - -%000001 reg [1:0] memory[121:110]; --000001 point: comment=memory[110][0] hier=top.t --000000 point: comment=memory[110][1] hier=top.t --000000 point: comment=memory[111][0] hier=top.t --000000 point: comment=memory[111][1] hier=top.t --000000 point: comment=memory[112][0] hier=top.t --000000 point: comment=memory[112][1] hier=top.t --000000 point: comment=memory[113][0] hier=top.t --000000 point: comment=memory[113][1] hier=top.t --000000 point: comment=memory[114][0] hier=top.t --000000 point: comment=memory[114][1] hier=top.t --000000 point: comment=memory[115][0] hier=top.t --000000 point: comment=memory[115][1] hier=top.t --000000 point: comment=memory[116][0] hier=top.t --000000 point: comment=memory[116][1] hier=top.t --000000 point: comment=memory[117][0] hier=top.t --000000 point: comment=memory[117][1] hier=top.t --000000 point: comment=memory[118][0] hier=top.t --000000 point: comment=memory[118][1] hier=top.t --000000 point: comment=memory[119][0] hier=top.t --000000 point: comment=memory[119][1] hier=top.t --000000 point: comment=memory[120][0] hier=top.t --000000 point: comment=memory[120][1] hier=top.t --000000 point: comment=memory[121][0] hier=top.t --000000 point: comment=memory[121][1] hier=top.t - - wire [1023:0] largeish = {992'h0, cyc}; - // CHECK_COVER_MISSING(-1) - - always @ (posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; - memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; - toggle <= '0; - stoggle.u <= toggle; - stoggle.b <= toggle; - utoggle.val1 <= real'(cyc[7:0]); - ptoggle[0][0] <= toggle; - if (cyc == 3) begin - str_queue.q.push_back(1); - toggle <= '1; - end - if (cyc == 4) begin - if (str_queue.q.size() != 1) $stop; - toggle <= '0; - end - else if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end - - endmodule - - module alpha (/*AUTOARG*/ - // Outputs - toggle_up, - // Inputs - clk, toggle, cyc_copy - ); - - // t.a1 and t.a2 collapse to a count of 2 - - 000038 input clk; -+000038 point: comment=clk hier=top.t.a* - -%000004 input toggle; --000004 point: comment=toggle hier=top.t.a* - // CHECK_COVER(-1,"top.t.a*",4) - // 2 edges * (t.a1 and t.a2) - -~000022 input [7:0] cyc_copy; -+000022 point: comment=cyc_copy[0] hier=top.t.a* -+000010 point: comment=cyc_copy[1] hier=top.t.a* --000004 point: comment=cyc_copy[2] hier=top.t.a* --000002 point: comment=cyc_copy[3] hier=top.t.a* --000000 point: comment=cyc_copy[4] hier=top.t.a* --000000 point: comment=cyc_copy[5] hier=top.t.a* --000000 point: comment=cyc_copy[6] hier=top.t.a* --000000 point: comment=cyc_copy[7] hier=top.t.a* - // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22) - // CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10) - // CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4) - // CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2) - // CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0) - // CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0) - // CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0) - // CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0) - -%000004 reg toggle_internal; --000004 point: comment=toggle_internal hier=top.t.a* - // CHECK_COVER(-1,"top.t.a*",4) - // 2 edges * (t.a1 and t.a2) - -%000004 output reg toggle_up; --000004 point: comment=toggle_up hier=top.t.a* - // CHECK_COVER(-1,"top.t.a*",4) - // 2 edges * (t.a1 and t.a2) - - always @ (posedge clk) begin - toggle_internal <= toggle; - toggle_up <= toggle; - end - endmodule - - module beta (/*AUTOARG*/ - // Inputs - clk, toggle_up - ); - - 000019 input clk; -+000019 point: comment=clk hier=top.t.b1 - -%000002 input toggle_up; --000002 point: comment=toggle_up hier=top.t.b1 - // CHECK_COVER(-1,"top.t.b1","toggle_up",2) - - /* verilator public_module */ - - always @ (posedge clk) begin - if (0 && toggle_up) begin end - end - endmodule - - module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); - - // verilator coverage_off - input clk; - // CHECK_COVER_MISSING(-1) - - // verilator coverage_on -%000002 input toggle; --000002 point: comment=toggle hier=top.t.o1 - // CHECK_COVER(-1,"top.t.o1","toggle",2) - - endmodule - - module param #(parameter P = 2) (/*AUTOARG*/ - // Inputs - clk, toggle - ); - - 000019 input clk; -+000019 point: comment=clk hier=top.t.p2 -+000019 point: comment=clk hier=top.t.p1 -%000002 input toggle; --000002 point: comment=toggle hier=top.t.p2 --000002 point: comment=toggle hier=top.t.p1 - -%000001 logic z; --000001 point: comment=z hier=top.t.p2 --000000 point: comment=z hier=top.t.p1 - - for (genvar i = 0; i < P; i++) begin -%000002 logic x; --000002 point: comment=genblk1[0].x hier=top.t.p2 --000002 point: comment=genblk1[1].x hier=top.t.p2 --000002 point: comment=genblk1[0].x hier=top.t.p1 - always @ (posedge clk) begin - x <= toggle; - end - for (genvar j = 0; j < 3; j++) begin -%000003 logic [2:0] y; --000001 point: comment=genblk1[0].genblk1[0].y[0] hier=top.t.p2 --000003 point: comment=genblk1[0].genblk1[0].y[1] hier=top.t.p2 --000002 point: comment=genblk1[0].genblk1[0].y[2] hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[1].y[0] hier=top.t.p2 --000003 point: comment=genblk1[0].genblk1[1].y[1] hier=top.t.p2 --000002 point: comment=genblk1[0].genblk1[1].y[2] hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[2].y[0] hier=top.t.p2 --000003 point: comment=genblk1[0].genblk1[2].y[1] hier=top.t.p2 --000002 point: comment=genblk1[0].genblk1[2].y[2] hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[0].y[0] hier=top.t.p2 --000003 point: comment=genblk1[1].genblk1[0].y[1] hier=top.t.p2 --000002 point: comment=genblk1[1].genblk1[0].y[2] hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[1].y[0] hier=top.t.p2 --000003 point: comment=genblk1[1].genblk1[1].y[1] hier=top.t.p2 --000002 point: comment=genblk1[1].genblk1[1].y[2] hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[2].y[0] hier=top.t.p2 --000003 point: comment=genblk1[1].genblk1[2].y[1] hier=top.t.p2 --000002 point: comment=genblk1[1].genblk1[2].y[2] hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[0].y[0] hier=top.t.p1 --000003 point: comment=genblk1[0].genblk1[0].y[1] hier=top.t.p1 --000002 point: comment=genblk1[0].genblk1[0].y[2] hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[1].y[0] hier=top.t.p1 --000003 point: comment=genblk1[0].genblk1[1].y[1] hier=top.t.p1 --000002 point: comment=genblk1[0].genblk1[1].y[2] hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[2].y[0] hier=top.t.p1 --000003 point: comment=genblk1[0].genblk1[2].y[1] hier=top.t.p1 --000002 point: comment=genblk1[0].genblk1[2].y[2] hier=top.t.p1 - always @ (negedge clk) begin - y <= {toggle, ~toggle, 1'b1}; - end - end - end - if (P > 1) begin : gen_1 - assign z = 1; - end - endmodule - diff --git a/test_regress/t/t_vlcov_data_e.dat b/test_regress/t/t_vlcov_data_e.dat new file mode 100644 index 000000000..32c705c59 --- /dev/null +++ b/test_regress/t/t_vlcov_data_e.dat @@ -0,0 +1,226 @@ +# SystemC::Coverage-3 +C 'ft/t_cover_line.vl100n10tlinepagev_line/toblockS100htop.t' 0 +C 'ft/t_cover_line.vl101n10tlinepagev_line/toblockS101-102htop.t' 0 +C 'ft/t_cover_line.vl104n10tlinepagev_line/toblockS104htop.t' 0 +C 'ft/t_cover_line.vl105n10tlinepagev_line/toblockS105-107htop.t' 0 +C 'ft/t_cover_line.vl110n10tlinepagev_line/toelsifS110-111htop.t' 1 +C 'ft/t_cover_line.vl113n15tlinepagev_line/toelsifS113,115htop.t' 1 +C 'ft/t_cover_line.vl12n10ttogglepagev_toggle/toclkhtop.t' 19 +C 'ft/t_cover_line.vl120n15tbranchpagev_branch/toifS120-122htop.t' 1 +C 'ft/t_cover_line.vl120n16tbranchpagev_branch/toelsehtop.t' 7 +C 'ft/t_cover_line.vl127n9tlinepagev_line/toblockS127,129htop.t' 1 +C 'ft/t_cover_line.vl138n10ttogglepagev_toggle/alphaoclkhtop.t.a*' 38 +C 'ft/t_cover_line.vl139n10ttogglepagev_toggle/alphaotogglehtop.t.a*' 4 +C 'ft/t_cover_line.vl14n10ttogglepagev_toggle/totogglehtop.t' 2 +C 'ft/t_cover_line.vl140n4tlinepagev_line/alphaoblockS140htop.t.a*' 20 +C 'ft/t_cover_line.vl141n7tbranchpagev_branch/alphaoifS141-142htop.t.a*' 2 +C 'ft/t_cover_line.vl141n8tbranchpagev_branch/alphaoelsehtop.t.a*' 18 +C 'ft/t_cover_line.vl145n8tlinepagev_line/alphaoelsehtop.t.a*' 18 +C 'ft/t_cover_line.vl15n4tlinepagev_line/toblockS15htop.t' 1 +C 'ft/t_cover_line.vl159n10ttogglepagev_toggle/betaoclkhtop.t.b*' 38 +C 'ft/t_cover_line.vl160n10ttogglepagev_toggle/betaotogglehtop.t.b*' 4 +C 'ft/t_cover_line.vl164n4tlinepagev_line/betaoblockS164-165htop.t.b*' 20 +C 'ft/t_cover_line.vl166n7tbranchpagev_branch/betaoifS166,168htop.t.b*' 0 +C 'ft/t_cover_line.vl166n8tbranchpagev_branch/betaoelsehtop.t.b*' 20 +C 'ft/t_cover_line.vl170n7tbranchpagev_branch/betaoifS170,172htop.t.b*' 2 +C 'ft/t_cover_line.vl170n8tbranchpagev_branch/betaoelsehtop.t.b*' 18 +C 'ft/t_cover_line.vl174n8tlinepagev_line/betaoelsehtop.t.b*' 18 +C 'ft/t_cover_line.vl18n4tlinepagev_line/toblockS18htop.t' 1 +C 'ft/t_cover_line.vl188n13tlinepagev_line/ClsoblockS188-189htop.$unit::Cls__Vclpkg' 1 +C 'ft/t_cover_line.vl190n7tbranchpagev_branch/ClsoifS190-191htop.$unit::Cls__Vclpkg' 1 +C 'ft/t_cover_line.vl190n8tbranchpagev_branch/Clsoelsehtop.$unit::Cls__Vclpkg' 0 +C 'ft/t_cover_line.vl194n25tlinepagev_line/ClsoblockS194htop.$unit::Cls__Vclpkg' 11 +C 'ft/t_cover_line.vl195n7tbranchpagev_branch/ClsoifS195-196htop.$unit::Cls__Vclpkg' 11 +C 'ft/t_cover_line.vl195n8tbranchpagev_branch/Clsoelsehtop.$unit::Cls__Vclpkg' 0 +C 'ft/t_cover_line.vl199n18tlinepagev_line/ClsoblockS199htop.$unit::Cls__Vclpkg' 11 +C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[0]htop.t' 11 +C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[1]htop.t' 5 +C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[2]htop.t' 2 +C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[3]htop.t' 1 +C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[4]htop.t' 0 +C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[5]htop.t' 0 +C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[6]htop.t' 0 +C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[7]htop.t' 0 +C 'ft/t_cover_line.vl200n7tbranchpagev_branch/ClsoifS200-201htop.$unit::Cls__Vclpkg' 11 +C 'ft/t_cover_line.vl200n8tbranchpagev_branch/Clsoelsehtop.$unit::Cls__Vclpkg' 0 +C 'ft/t_cover_line.vl210n10ttogglepagev_toggle/tskoclkhtop.t.t1' 19 +C 'ft/t_cover_line.vl211n10ttogglepagev_toggle/tskotogglehtop.t.t1' 2 +C 'ft/t_cover_line.vl215n4tlinepagev_line/tskoblockS215-216htop.t.t1' 10 +C 'ft/t_cover_line.vl219n9tlinepagev_line/tskoblockS219,221,229,231-232htop.t.t1' 11 +C 'ft/t_cover_line.vl222n10tbranchpagev_branch/tskoifS222-223htop.t.t1' 1 +C 'ft/t_cover_line.vl222n11tbranchpagev_branch/tskoelsehtop.t.t1' 10 +C 'ft/t_cover_line.vl225n10tbranchpagev_branch/tskoifS225-226htop.t.t1' 1 +C 'ft/t_cover_line.vl225n11tbranchpagev_branch/tskoelsehtop.t.t1' 10 +C 'ft/t_cover_line.vl230n18tlinepagev_line/tskoblockS230htop.t.t1' 1 +C 'ft/t_cover_line.vl241n10ttogglepagev_toggle/offoclkhtop.t.o1' 19 +C 'ft/t_cover_line.vl242n10ttogglepagev_toggle/offotogglehtop.t.o1' 2 +C 'ft/t_cover_line.vl252n4tlinepagev_line/offoblockS252htop.t.o1' 10 +C 'ft/t_cover_line.vl253n7tbranchpagev_branch/offoifS253,255htop.t.o1' 1 +C 'ft/t_cover_line.vl253n8tbranchpagev_branch/offoelsehtop.t.o1' 9 +C 'ft/t_cover_line.vl256n10tbranchpagev_branch/offoifS256htop.t.o1' 0 +C 'ft/t_cover_line.vl256n11tbranchpagev_branch/offoelsehtop.t.o1' 1 +C 'ft/t_cover_line.vl261n19ttogglepagev_toggle/taboclkhtop.t.tab1' 19 +C 'ft/t_cover_line.vl262n14ttogglepagev_toggle/tabocyc4[0]htop.t.tab1' 10 +C 'ft/t_cover_line.vl262n14ttogglepagev_toggle/tabocyc4[1]htop.t.tab1' 5 +C 'ft/t_cover_line.vl262n14ttogglepagev_toggle/tabocyc4[2]htop.t.tab1' 2 +C 'ft/t_cover_line.vl262n14ttogglepagev_toggle/tabocyc4[3]htop.t.tab1' 1 +C 'ft/t_cover_line.vl265n4tlinepagev_line/taboblockS265-266htop.t.tab1' 10 +C 'ft/t_cover_line.vl267n10tlinepagev_line/tabocaseS267htop.t.tab1' 1 +C 'ft/t_cover_line.vl268n10tlinepagev_line/tabocaseS268htop.t.tab1' 1 +C 'ft/t_cover_line.vl269n10tlinepagev_line/tabocaseS269htop.t.tab1' 1 +C 'ft/t_cover_line.vl270n10tlinepagev_line/tabocaseS270htop.t.tab1' 1 +C 'ft/t_cover_line.vl271n10tlinepagev_line/tabocaseS271htop.t.tab1' 1 +C 'ft/t_cover_line.vl272n9tlinepagev_line/tabocaseS272htop.t.tab1' 5 +C 'ft/t_cover_line.vl276n4tlinepagev_line/taboblockS276-277htop.t.tab1' 10 +C 'ft/t_cover_line.vl287n27tlinepagev_line/paroblockS287,294htop.t.par1' 0 +C 'ft/t_cover_line.vl288n7tbranchpagev_branch/paroifS288-289htop.t.par1' 0 +C 'ft/t_cover_line.vl288n8tbranchpagev_branch/paroelseS291-292htop.t.par1' 0 +C 'ft/t_cover_line.vl300n14tlinepagev_line/my_pkgoblockS300htop.my_pkg' 1 +C 'ft/t_cover_line.vl303n1tlinepagev_line/Getter1oblockS303htop.$unit::Getter1__Vclpkg' 1 +C 'ft/t_cover_line.vl304n17tlinepagev_line/Getter1oblockS304-305htop.$unit::Getter1__Vclpkg' 20 +C 'ft/t_cover_line.vl309n25ttogglepagev_toggle/condoclkhtop.t.cond1' 19 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[0]htop.t.cond1' 11 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[10]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[11]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[12]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[13]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[14]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[15]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[16]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[17]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[18]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[19]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[1]htop.t.cond1' 5 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[20]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[21]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[22]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[23]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[24]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[25]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[26]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[27]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[28]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[29]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[2]htop.t.cond1' 2 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[30]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[31]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[3]htop.t.cond1' 1 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[4]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[5]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[6]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[7]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[8]htop.t.cond1' 0 +C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[9]htop.t.cond1' 0 +C 'ft/t_cover_line.vl310n10ttogglepagev_toggle/condoahtop.t.cond1' 0 +C 'ft/t_cover_line.vl310n13ttogglepagev_toggle/condobhtop.t.cond1' 2 +C 'ft/t_cover_line.vl310n16ttogglepagev_toggle/condochtop.t.cond1' 19 +C 'ft/t_cover_line.vl310n19ttogglepagev_toggle/condodhtop.t.cond1' 6 +C 'ft/t_cover_line.vl310n22ttogglepagev_toggle/condoehtop.t.cond1' 7 +C 'ft/t_cover_line.vl310n25ttogglepagev_toggle/condofhtop.t.cond1' 1 +C 'ft/t_cover_line.vl310n28ttogglepagev_toggle/condoghtop.t.cond1' 19 +C 'ft/t_cover_line.vl310n31ttogglepagev_toggle/condohhtop.t.cond1' 3 +C 'ft/t_cover_line.vl310n34ttogglepagev_toggle/condokhtop.t.cond1' 0 +C 'ft/t_cover_line.vl310n37ttogglepagev_toggle/condolhtop.t.cond1' 0 +C 'ft/t_cover_line.vl310n40ttogglepagev_toggle/condomhtop.t.cond1' 0 +C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[0]htop.t.cond1' 1 +C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[1]htop.t.cond1' 1 +C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[2]htop.t.cond1' 0 +C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[3]htop.t.cond1' 0 +C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[4]htop.t.cond1' 0 +C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[5]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][0]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][1]htop.t.cond1' 2 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][2]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][3]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][4]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][5]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][6]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][7]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][0]htop.t.cond1' 2 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][1]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][2]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][3]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][4]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][5]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][6]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][7]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][0]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][1]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][2]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][3]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][4]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][5]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][6]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][7]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][0]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][1]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][2]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][3]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][4]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][5]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][6]htop.t.cond1' 0 +C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][7]htop.t.cond1' 0 +C 'ft/t_cover_line.vl314n22tlinepagev_line/condoblockS314htop.t.cond1' 1 +C 'ft/t_cover_line.vl317n19tlinepagev_line/condoblockS317-319htop.t.cond1' 21 +C 'ft/t_cover_line.vl322n19tlinepagev_line/condoblockS322,324htop.t.cond1' 10 +C 'ft/t_cover_line.vl327n26tbranchpagev_branch/condocond_thenS327htop.t.cond1' 0 +C 'ft/t_cover_line.vl327n27tbranchpagev_branch/condocond_elseS327htop.t.cond1' 31 +C 'ft/t_cover_line.vl328n26tbranchpagev_branch/condocond_thenS328htop.t.cond1' 3 +C 'ft/t_cover_line.vl328n27tbranchpagev_branch/condocond_elseS328htop.t.cond1' 28 +C 'ft/t_cover_line.vl329n34tbranchpagev_branch/condocond_thenS329htop.t.cond1' 21 +C 'ft/t_cover_line.vl329n35tbranchpagev_branch/condocond_elseS329htop.t.cond1' 0 +C 'ft/t_cover_line.vl330n4tlinepagev_line/condoblockS330-332htop.t.cond1' 10 +C 'ft/t_cover_line.vl331n20texprpagev_expr/condo(((cyc %25 32'sh3) == 32'sh0)==0) => 0htop.t.cond1' 7 +C 'ft/t_cover_line.vl331n20texprpagev_expr/condo(((cyc %25 32'sh3) == 32'sh0)==1) => 1htop.t.cond1' 3 +C 'ft/t_cover_line.vl331n26tbranchpagev_branch/condocond_thenS331htop.t.cond1' 3 +C 'ft/t_cover_line.vl331n27tbranchpagev_branch/condocond_elseS331htop.t.cond1' 7 +C 'ft/t_cover_line.vl332n34tbranchpagev_branch/condocond_thenS332htop.t.cond1' 0 +C 'ft/t_cover_line.vl332n35tbranchpagev_branch/condocond_elseS332htop.t.cond1' 10 +C 'ft/t_cover_line.vl334n30tbranchpagev_branch/condocond_thenS334htop.t.cond1' 12 +C 'ft/t_cover_line.vl334n31tbranchpagev_branch/condocond_elseS334htop.t.cond1' 19 +C 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11 +C 'ft/t_cover_line.vl360n11texprpagev_expr/condo(k==1) => 1htop.t.cond1' 0 +C 'ft/t_cover_line.vl360n7tbranchpagev_branch/condoifS360htop.t.cond1' 0 +C 'ft/t_cover_line.vl360n8tbranchpagev_branch/condoelseS361htop.t.cond1' 11 +C 'ft/t_cover_line.vl55n4tlinepagev_line/toblockS55htop.t' 10 +C 'ft/t_cover_line.vl56n7tbranchpagev_branch/toifS56-58,105-106htop.t' 10 +C 'ft/t_cover_line.vl56n8tbranchpagev_branch/toelsehtop.t' 0 +C 'ft/t_cover_line.vl60n10tbranchpagev_branch/toifS60htop.t' 1 +C 'ft/t_cover_line.vl60n11tbranchpagev_branch/toelsehtop.t' 9 +C 'ft/t_cover_line.vl61n10tbranchpagev_branch/toifS61-63htop.t' 1 +C 'ft/t_cover_line.vl61n11tbranchpagev_branch/toelsehtop.t' 9 +C 'ft/t_cover_line.vl66n10tbranchpagev_branch/toifS66htop.t' 1 +C 'ft/t_cover_line.vl66n11tbranchpagev_branch/toelseS66htop.t' 9 +C 'ft/t_cover_line.vl67n10tbranchpagev_branch/toifS67htop.t' 1 +C 'ft/t_cover_line.vl67n11tbranchpagev_branch/toelseS69-70htop.t' 9 +C 'ft/t_cover_line.vl73n10tbranchpagev_branch/toifS73htop.t' 1 +C 'ft/t_cover_line.vl73n11tbranchpagev_branch/toelseS73htop.t' 9 +C 'ft/t_cover_line.vl74n10tbranchpagev_branch/toifS74-76htop.t' 1 +C 'ft/t_cover_line.vl74n11tbranchpagev_branch/toelseS79-80htop.t' 9 +C 'ft/t_cover_line.vl83n10tlinepagev_line/toelsifS83-85htop.t' 1 +C 'ft/t_cover_line.vl87n15tlinepagev_line/toelsifS87-89htop.t' 1 +C 'ft/t_cover_line.vl91n15tlinepagev_line/toifS91-93htop.t' 1 +C 'ft/t_cover_line.vl91n16tlinepagev_line/toelseS96-97htop.t' 7 diff --git a/test_regress/t/t_cover_branch_option.info.out b/test_regress/t/t_vlcov_opt_branch.info.out similarity index 100% rename from test_regress/t/t_cover_branch_option.info.out rename to test_regress/t/t_vlcov_opt_branch.info.out diff --git a/test_regress/t/t_vlcov_opt_branch.py b/test_regress/t/t_vlcov_opt_branch.py new file mode 100755 index 000000000..d784b9006 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_branch.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type branch", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_opt_expr.info.out b/test_regress/t/t_vlcov_opt_expr.info.out new file mode 100644 index 000000000..33c3c1c89 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_expr.info.out @@ -0,0 +1,23 @@ +TN:verilator_coverage +SF:t/t_cover_line.v +DA:331,7 +BRDA:331,0,0,7 +BRDA:331,0,1,3 +DA:347,1 +BRDA:347,0,0,1 +BRDA:347,0,1,0 +DA:350,10 +BRDA:350,0,0,10 +BRDA:350,0,1,1 +DA:353,11 +BRDA:353,0,0,11 +BRDA:353,0,1,0 +DA:356,11 +BRDA:356,0,0,0 +BRDA:356,0,1,11 +DA:360,11 +BRDA:360,0,0,11 +BRDA:360,0,1,0 +BRF:12 +BRH:4 +end_of_record diff --git a/test_regress/t/t_vlcov_opt_expr.py b/test_regress/t/t_vlcov_opt_expr.py new file mode 100755 index 000000000..4fa8200d2 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_expr.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type expr", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_cover_line_option.info.out b/test_regress/t/t_vlcov_opt_line.info.out similarity index 100% rename from test_regress/t/t_cover_line_option.info.out rename to test_regress/t/t_vlcov_opt_line.info.out diff --git a/test_regress/t/t_vlcov_opt_line.py b/test_regress/t/t_vlcov_opt_line.py new file mode 100755 index 000000000..f5f4b8195 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_line.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type line", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_opt_toggle.info.out b/test_regress/t/t_vlcov_opt_toggle.info.out new file mode 100644 index 000000000..7740e44dc --- /dev/null +++ b/test_regress/t/t_vlcov_opt_toggle.info.out @@ -0,0 +1,116 @@ +TN:verilator_coverage +SF:t/t_cover_line.v +DA:12,19 +DA:14,2 +DA:20,11 +BRDA:20,0,0,11 +BRDA:20,0,1,5 +BRDA:20,0,2,2 +BRDA:20,0,3,1 +BRDA:20,0,4,0 +BRDA:20,0,5,0 +BRDA:20,0,6,0 +BRDA:20,0,7,0 +DA:138,38 +DA:139,4 +DA:159,38 +DA:160,4 +DA:210,19 +DA:211,2 +DA:241,19 +DA:242,2 +DA:261,19 +DA:262,10 +BRDA:262,0,0,10 +BRDA:262,0,1,5 +BRDA:262,0,2,2 +BRDA:262,0,3,1 +DA:309,19 +BRDA:309,0,0,19 +BRDA:309,0,1,11 +BRDA:309,0,2,0 +BRDA:309,0,3,0 +BRDA:309,0,4,0 +BRDA:309,0,5,0 +BRDA:309,0,6,0 +BRDA:309,0,7,0 +BRDA:309,0,8,0 +BRDA:309,0,9,0 +BRDA:309,0,10,0 +BRDA:309,0,11,0 +BRDA:309,0,12,5 +BRDA:309,0,13,0 +BRDA:309,0,14,0 +BRDA:309,0,15,0 +BRDA:309,0,16,0 +BRDA:309,0,17,0 +BRDA:309,0,18,0 +BRDA:309,0,19,0 +BRDA:309,0,20,0 +BRDA:309,0,21,0 +BRDA:309,0,22,0 +BRDA:309,0,23,2 +BRDA:309,0,24,0 +BRDA:309,0,25,0 +BRDA:309,0,26,1 +BRDA:309,0,27,0 +BRDA:309,0,28,0 +BRDA:309,0,29,0 +BRDA:309,0,30,0 +BRDA:309,0,31,0 +BRDA:309,0,32,0 +DA:310,19 +BRDA:310,0,0,0 +BRDA:310,0,1,2 +BRDA:310,0,2,19 +BRDA:310,0,3,6 +BRDA:310,0,4,7 +BRDA:310,0,5,1 +BRDA:310,0,6,19 +BRDA:310,0,7,3 +BRDA:310,0,8,0 +BRDA:310,0,9,0 +BRDA:310,0,10,0 +DA:311,1 +BRDA:311,0,0,1 +BRDA:311,0,1,1 +BRDA:311,0,2,0 +BRDA:311,0,3,0 +BRDA:311,0,4,0 +BRDA:311,0,5,0 +DA:313,2 +BRDA:313,0,0,0 +BRDA:313,0,1,2 +BRDA:313,0,2,0 +BRDA:313,0,3,0 +BRDA:313,0,4,0 +BRDA:313,0,5,0 +BRDA:313,0,6,0 +BRDA:313,0,7,0 +BRDA:313,0,8,2 +BRDA:313,0,9,0 +BRDA:313,0,10,0 +BRDA:313,0,11,0 +BRDA:313,0,12,0 +BRDA:313,0,13,0 +BRDA:313,0,14,0 +BRDA:313,0,15,0 +BRDA:313,0,16,0 +BRDA:313,0,17,0 +BRDA:313,0,18,0 +BRDA:313,0,19,0 +BRDA:313,0,20,0 +BRDA:313,0,21,0 +BRDA:313,0,22,0 +BRDA:313,0,23,0 +BRDA:313,0,24,0 +BRDA:313,0,25,0 +BRDA:313,0,26,0 +BRDA:313,0,27,0 +BRDA:313,0,28,0 +BRDA:313,0,29,0 +BRDA:313,0,30,0 +BRDA:313,0,31,0 +BRF:94 +BRH:6 +end_of_record diff --git a/test_regress/t/t_vlcov_opt_toggle.py b/test_regress/t/t_vlcov_opt_toggle.py new file mode 100755 index 000000000..49da6830d --- /dev/null +++ b/test_regress/t/t_vlcov_opt_toggle.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type toggle", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes()