diff --git a/Changes b/Changes
index 547244db7..29dada666 100644
--- a/Changes
+++ b/Changes
@@ -13,6 +13,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix cell port connection to unsized integer causing false width warning.
 
+**** Fix erroring on strings with backslashed newlines, bug168. [Pete Nixon]
+
 * Verilator 3.714 2009/09/18
 
 **   Add --bbox-sys option to blackbox $system calls.
diff --git a/src/V3PreLex.l b/src/V3PreLex.l
index 1f397b202..3980745a7 100644
--- a/src/V3PreLex.l
+++ b/src/V3PreLex.l
@@ -107,6 +107,7 @@ psl		[p]sl
 <STRMODE><<EOF>>	{ linenoInc(); yyerrorf("EOF in unterminated string"); yyleng=0; yyterminate(); }
 <STRMODE>{crnl}		{ linenoInc(); yyerrorf("Unterminated string"); BEGIN(INITIAL); }
 <STRMODE>[^\"\\]	{ yymore(); }
+<STRMODE>{backslash}{crnl} { linenoInc(); yymore(); }
 <STRMODE>{backslash}.	{ yymore(); }
 <STRMODE>{quote} 	{ yy_pop_state();
 			  if (V3PreLex::s_currentLexp->m_parenLevel) appendDefValue(yytext,yyleng);
diff --git a/src/verilog.l b/src/verilog.l
index 80bc47e9e..1bb3fa2ed 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -767,6 +767,7 @@ escid	\\[^ \t\f\r\n]+
   /************************************************************************/
   /* STRINGS */
 <STRING>{crnl} 		{ yyerrorf("Unterminated string"); }
+<STRING>\\{crnl}	{ yymore(); NEXTLINE(); }
 <STRING>\\.	 	{ yymore(); }
 <STRING>\" 		{ yy_pop_state();
 			  yylval.strp = V3Read::newString(yytext+1,yyleng-2);
diff --git a/test_regress/t/t_display.pl b/test_regress/t/t_display.pl
index 47839d1cf..6920c0b18 100755
--- a/test_regress/t/t_display.pl
+++ b/test_regress/t/t_display.pl
@@ -27,6 +27,8 @@ execute (
 [0] %s=! %s= what! %s= hmmm!1234
 [0] hello, from a very long string. Percent %s are literally substituted in.
 [0] Embedded <#013> return
+[0] Embedded
+multiline
 *-* All Finished *-*
 ')),
      );
diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v
index b826236f3..ab411bb3e 100644
--- a/test_regress/t/t_display.v
+++ b/test_regress/t/t_display.v
@@ -38,6 +38,8 @@ module t;
       $display("[%0t] %s%s%s", $time,
 	       "hel", "lo, fr", "om a very long string. Percent %s are literally substituted in.");
       $write("[%0t] Embedded \r return\n", $time);
+      $display("[%0t] Embedded\
+multiline", $time);
 
       // Str check
 `ifndef nc	// NC-Verilog 5.3 chokes on this test
diff --git a/test_regress/t/t_display_noopt.pl b/test_regress/t/t_display_noopt.pl
index f2b76d55f..0ed664dab 100755
--- a/test_regress/t/t_display_noopt.pl
+++ b/test_regress/t/t_display_noopt.pl
@@ -30,6 +30,8 @@ execute (
 [0] %s=! %s= what! %s= hmmm!1234
 [0] hello, from a very long string. Percent %s are literally substituted in.
 [0] Embedded <#013> return
+[0] Embedded
+multiline
 *-* All Finished *-*
 ')),
      );