diff --git a/Changes b/Changes
index acf90fded..993e647bc 100644
--- a/Changes
+++ b/Changes
@@ -107,6 +107,7 @@ Verilator 5.047 devel
 * Fix false ASSIGNIN on interface input ports driven from outside (#7322). [Yilou Wang]
 * Fix static initialization order for packages with class hierarchies (#7324). [Yilou Wang]
 * Fix `disable iff` imply-delay statement linking (#7337). [Nick Brereton]
+* Fix lost `$stop` on implied assertion `$error` failures.
 
 
 Verilator 5.046 2026-02-28
diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index d95431fe1..f72fdbfab 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -737,9 +737,8 @@ class AssertVisitor final : public VNVisitor {
                 // Cover adds COVERINC by AstNode::addNext, thus need to clone next too.
                 nodep->replaceWith(m_passsp->cloneTree(true));
             } else if (!nodep->pass() && m_failsp) {
-                // Asserts with multiple statements are wrapped in implicit begin/end blocks so no
-                // need to clone next.
-                nodep->replaceWith(m_failsp->cloneTree(false));
+                // Stop may be added, thus need to clone next too.
+                nodep->replaceWith(m_failsp->cloneTree(true));
             } else {
                 nodep->unlinkFrBack();
             }
diff --git a/test_regress/t/t_assert_property_stop_bad.out b/test_regress/t/t_assert_property_stop_bad.out
new file mode 100644
index 000000000..73ef02c88
--- /dev/null
+++ b/test_regress/t/t_assert_property_stop_bad.out
@@ -0,0 +1,3 @@
+[50] %Error: t_assert_property_stop_bad.v:24: Assertion failed in t.__VforkTask_0: 'assert' failed.
+%Error: t/t_assert_property_stop_bad.v:24: Verilog $stop
+Aborting...
diff --git a/test_regress/t/t_assert_property_stop_bad.py b/test_regress/t/t_assert_property_stop_bad.py
new file mode 100755
index 000000000..20a9b4950
--- /dev/null
+++ b/test_regress/t/t_assert_property_stop_bad.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_assert_property_stop_bad.v b/test_regress/t/t_assert_property_stop_bad.v
new file mode 100644
index 000000000..62afe512d
--- /dev/null
+++ b/test_regress/t/t_assert_property_stop_bad.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+  bit valid;
+  bit clk;
+  logic [7:0] out;
+  logic [7:0] in;
+
+  initial begin
+    valid = 1;
+    out = 2;
+    in = 2;
+  end
+
+  property prop;
+    @(posedge clk) (valid) |-> ##2 (out == in + 3);
+  endproperty
+
+  assert property (prop);
+
+  initial begin
+    forever begin
+      #(10) clk = ~clk;
+    end
+  end
+
+  initial #200 $finish;
+
+endmodule