From e01f0f5e674535a457e0804e797de5af55ba7009 Mon Sep 17 00:00:00 2001
From: Iztok Jeras <iztok.jeras@gmail.com>
Date: Thu, 1 Jan 2026 17:16:47 +0100
Subject: [PATCH] Tests: Add interface_array_parameter_aggregate_access (#6873)

---
 ...erface_array_parameter_aggregate_access.py | 18 ++++++
 ...terface_array_parameter_aggregate_access.v | 61 +++++++++++++++++++
 2 files changed, 79 insertions(+)
 create mode 100755 test_regress/t/t_interface_array_parameter_aggregate_access.py
 create mode 100644 test_regress/t/t_interface_array_parameter_aggregate_access.v

diff --git a/test_regress/t/t_interface_array_parameter_aggregate_access.py b/test_regress/t/t_interface_array_parameter_aggregate_access.py
new file mode 100755
index 000000000..f7fdf9c4f
--- /dev/null
+++ b/test_regress/t/t_interface_array_parameter_aggregate_access.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+
+test.compile(fails=True)
+
+#test.execute(fails=True)
+
+test.passes()
diff --git a/test_regress/t/t_interface_array_parameter_aggregate_access.v b/test_regress/t/t_interface_array_parameter_aggregate_access.v
new file mode 100644
index 000000000..f855eb665
--- /dev/null
+++ b/test_regress/t/t_interface_array_parameter_aggregate_access.v
@@ -0,0 +1,61 @@
+// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2024 by Todd Strader
+// SPDX-License-Identifier: CC0-1.0
+
+typedef struct {
+    int BAR_INT;
+    bit BAR_BIT;
+    byte BAR_ARRAY [0:3];
+} foo_t;
+
+interface intf
+  #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}})
+    (input wire clk,
+     input wire rst);
+    modport modp (input  clk, rst);
+endinterface
+
+module sub (intf.modp the_intf_port [4], intf.modp single_intf_port);
+    localparam foo_t intf_foo          = the_intf_port[0].FOO;
+    localparam int   intf_foo_bar_int  = the_intf_port[0].FOO.BAR_INT;
+    localparam bit   intf_foo_bar_bit  = the_intf_port[0].FOO.BAR_BIT;
+    localparam byte  intf_foo_bar_byte = the_intf_port[0].FOO.BAR_ARRAY[3];
+    localparam foo_t single_foo          = single_intf_port.FOO;
+    localparam int   single_foo_bar_int  = single_intf_port.FOO.BAR_INT;
+    localparam bit   single_foo_bar_bit  = single_intf_port.FOO.BAR_BIT;
+    localparam byte  single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3];
+
+    initial begin
+        if (intf_foo          != foo_t'{4, 1'b1, '{1, 2, 4, 8}}) $stop;
+        if (intf_foo_bar_int  != 4) $stop;
+        if (intf_foo_bar_bit  != 1'b1) $stop;
+        if (intf_foo_bar_byte != 8'd8) $stop;
+        if (single_foo          != foo_t'{4, 1'b1, '{1, 2, 4, 8}}) $stop;
+        if (single_foo_bar_int  != 4) $stop;
+        if (single_foo_bar_bit  != 1'b1) $stop;
+        if (single_foo_bar_byte != 8'd8) $stop;
+    end
+endmodule
+
+module t (
+    clk
+);
+    logic rst;
+    input clk;
+
+    intf the_intf [4] (.*);
+    intf single_intf (.*);
+
+    sub
+    the_sub (
+        .the_intf_port   (the_intf),
+        .single_intf_port(single_intf)
+    );
+
+   always @(posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule