diff --git a/Changes b/Changes
index 4dcccebc8..7c13df3f2 100644
--- a/Changes
+++ b/Changes
@@ -9,6 +9,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  For --xml, add additional information, bug1372. [Jonathan Kimmitt]
 
+****  Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov]
+
 
 * Verilator 4.008 2018-12-01
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 0aff35210..e410cebf2 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1806,9 +1806,10 @@ private:
 			}
 			else {
                             if (!VN_IS(classp, UnionDType)) {
-				patp->v3error("Assignment pattern missed initializing elements: "<<memp->prettyTypeName());
-			    }
-			}
+                                nodep->v3error("Assignment pattern missed initializing elements: "
+                                               <<memp->prettyTypeName());
+                            }
+                        }
 		    } else {
 			patp = it->second;
 		    }
diff --git a/test_regress/t/t_array_list_bad.out b/test_regress/t/t_array_list_bad.out
new file mode 100644
index 000000000..39dbacb69
--- /dev/null
+++ b/test_regress/t/t_array_list_bad.out
@@ -0,0 +1,4 @@
+%Error: t/t_array_list_bad.v:37: Assignment pattern missed initializing elements: MEMBERDTYPE 't3'
+%Warning-WIDTH: t/t_array_list_bad.v:37: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
+%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
+%Error: Exiting due to
diff --git a/test_regress/t/t_array_list_bad.pl b/test_regress/t/t_array_list_bad.pl
new file mode 100755
index 000000000..3361369bf
--- /dev/null
+++ b/test_regress/t/t_array_list_bad.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_array_list_bad.v b/test_regress/t/t_array_list_bad.v
new file mode 100644
index 000000000..25c115c78
--- /dev/null
+++ b/test_regress/t/t_array_list_bad.v
@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+package pkg;
+   typedef struct packed {
+      logic 	  t1;
+      logic 	  t2;
+      logic 	  t3;
+   } type_t;
+endpackage : pkg
+
+module t
+  (
+   input logic sys_clk,
+   input logic sys_rst_n,
+   input logic sys_ena,
+
+   input       pkg::type_t test_in,
+   output      pkg::type_t test_out
+   );
+
+   import pkg::*;
+
+   always_ff @(posedge sys_clk or negedge sys_rst_n) begin
+      if (~sys_rst_n) begin
+         test_out <= '{'0, '0, '0};
+      end
+      else begin
+         if(sys_ena) begin
+            test_out.t1 <= ~test_in.t1;
+            test_out.t2 <= ~test_in.t2;
+            test_out.t3 <= ~test_in.t3;
+         end
+         else begin
+            test_out <= '{'0, '0}; /* Inconsistent array list; */
+         end
+      end
+   end
+endmodule: t