From dff2606c0cae96df559c9da1b4581068da78e884 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 14 May 2026 17:38:11 -0400 Subject: [PATCH] Commentary: Changes update --- Changes | 12 +++++++++++- docs/spelling.txt | 2 +- test_regress/t/t_force_struct_trace.v | 4 +--- test_regress/t/t_force_wide_sel.v | 12 ++++++------ 4 files changed, 19 insertions(+), 11 deletions(-) diff --git a/Changes b/Changes index 8b83c7f71..6cb097930 100644 --- a/Changes +++ b/Changes @@ -28,15 +28,22 @@ Verilator 5.049 devel * Support procedural continuous assign/deassign (#7493). [Artur Bieniek, Antmicro Ltd.] * Support randsequence production function ports (#7522). [Yilou Wang] * Support followed-by operators `#-#` and `#=#` in properties (#7523). [Yilou Wang] +* Support expression coverage on assign statements (#7542) (#7543). [Thomas Brown] * Support TERMUX (#7559). [Laurent CHARRIER] * Support SVA goto repetition with range `[->M:N]` (#7569). [Yilou Wang] +* Support procedural concurrent assertions with inferred clock (#7581). [Yilou Wang] +* Support calling interface functions without parens (#7584). [Krzysztof Bieganski, Antmicro Ltd.] * Add peak memory usage to `--stats`. [Geza Lore, Testorrent USA, Inc.] * Add error on mixed-initialization (#7352) (#7357). -* Improve `--coverage-fsm` (#7490) (#7529) (#7561). [Yogish Sekhar] +* Improve `--coverage-fsm` (#7490) (#7529) (#7561) (#7573). [Yogish Sekhar] * Change `+verilator+seed` to default to 1, and 0 to randomly select (#7325) (#7516). [Miguel] * Change JSON to include parameter constant mnemonics for FSM Coverage (#7531). [Yogish Sekhar] +* Optimize emitting to_string() for compiler speedup (#7468). [Jakub Michalski, Antmicro Ltd.] * Optimize additional DFG peephole cases (#7553). [Varun Koyyalagunta, Testorrent USA, Inc.] +* Optimize forced signal handling (#7554 partial) (#7572) (#7504_. [Krzysztof Bieganski, Artur Bieniek, Antmicro Ltd.] * Fix inlining static initializer in V3Gate (#5381) (#7503). [Andrew Nolte] [Geza Lore, Testorrent USA, Inc.] +* Fix segmentation fault when using --trace with --lib-create (#7299) (#7518). [anonkey] +* Fix destructive event state before dynamic waits (#7340). [Nick Brereton] * Fix generic interface port forwarded to a nested instance (#7454) (#7457). [Yilou Wang] * Fix internal error on multi-cycle SVA under default clocking (#7472) (#7506). [Yilou Wang] * Fix internal error instead of missing prototype error (#7485). [Alex Solomatnikov] @@ -54,6 +61,9 @@ Verilator 5.049 devel * Fix exponential expansion in V3Gate (#7550). [Geza Lore, Testorrent USA, Inc.] * Fix display of %m in non-first argument (#7574). * Fix floating point compile warning on min/max delays. +* Fix force of unpacked arrays (#7579) (#7580). [Zubin Jain] +* Fix property argument retaining type of the previous variable (#7582). [Jakub Michalski] +* Fix NBA to whole arrays (#7583) (#7575). [Geza Lore, Testorrent USA, Inc.] Verilator 5.048 2026-04-26 diff --git a/docs/spelling.txt b/docs/spelling.txt index 8b6492d3a..8ef845d93 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -180,8 +180,8 @@ Guo Gustafsson Güzel Hameed -Hammoud Hamming +Hammoud Hao Haojin Harboe diff --git a/test_regress/t/t_force_struct_trace.v b/test_regress/t/t_force_struct_trace.v index 3dd1aeb83..5298c71c9 100644 --- a/test_regress/t/t_force_struct_trace.v +++ b/test_regress/t/t_force_struct_trace.v @@ -10,9 +10,7 @@ module t; logic forced_sig; - typedef struct { - logic [1:0] d[0:1]; - } payload_t; + typedef struct {logic [1:0] d[0:1];} payload_t; payload_t s; initial begin force forced_sig = 1'b1; diff --git a/test_regress/t/t_force_wide_sel.v b/test_regress/t/t_force_wide_sel.v index b83ef8c29..ea7aa54a3 100644 --- a/test_regress/t/t_force_wide_sel.v +++ b/test_regress/t/t_force_wide_sel.v @@ -10,7 +10,7 @@ // verilog_format: on module t ( - input clk + input clk ); integer cyc = 0; logic [127:0] sig; @@ -30,14 +30,14 @@ module t ( force publicSig[32] = 1'b1; end else if (cyc == 3) begin - `checkh(sig[33:26], 8'h60); // width <= 8 - `checkh(sig[39:24], 16'h180); // 8 < width <= 16 - `checkh(sig[40:20], 21'h1800); // 16 < width <= 32 + `checkh(sig[33:26], 8'h60); // width <= 8 + `checkh(sig[39:24], 16'h180); // 8 < width <= 16 + `checkh(sig[40:20], 21'h1800); // 16 < width <= 32 `checkh(sig[51:20], 32'h1800); `checkh(sig[29:0], 30'h0); - `checkh(sig[50:10], 41'h600000); // 32 < width <= 64 + `checkh(sig[50:10], 41'h600000); // 32 < width <= 64 `checkh(sig[73:10], 64'h600000); - `checkh(sig[100:5], (96'h1 << 26) | (96'h1 << 27)); // width > 64 + `checkh(sig[100:5], (96'h1 << 26) | (96'h1 << 27)); // width > 64 `checkh(sig[70:6], (65'h1 << 25) | (65'h1 << 26)); `checkh(publicSig[33:26], 8'h60); // width <= 8