diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 7035d515e..5d3757fe7 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3692,6 +3692,8 @@ private:
         case AstType::atNeq:    nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
         case AstType::atEqCase: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
         case AstType::atNeqCase: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
+        case AstType::atEqWild: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
+        case AstType::atNeqWild: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
         case AstType::atAdd:    nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
         case AstType::atSub:    nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
         case AstType::atShiftL: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
diff --git a/test_regress/t/t_math_eq.v b/test_regress/t/t_math_eq.v
index dad6aeab8..36a46643f 100644
--- a/test_regress/t/t_math_eq.v
+++ b/test_regress/t/t_math_eq.v
@@ -77,4 +77,16 @@ module Test (/*AUTOARG*/
    assign 	out[1] = in[3:0] !=? 4'b1001;
    assign 	out[2] = in[3:0] ==? 4'bx01x;
    assign 	out[3] = in[3:0] !=? 4'bx01x;
+
+   wire signed [3:0] ins = in[3:0];
+
+   wire signed [3:0] outs;
+
+   assign 	outs[0] = ins ==? 4'sb1001;
+   assign 	outs[1] = ins !=? 4'sb1001;
+   assign 	outs[2] = ins ==? 4'sbx01x;
+   assign 	outs[3] = ins !=? 4'sbx01x;
+
+   always_comb if (out != outs) $stop;
+
 endmodule