diff --git a/Changes b/Changes
index 5ffac9a75..e605d1378 100644
--- a/Changes
+++ b/Changes
@@ -36,6 +36,7 @@ Verilator 4.201 devel
 * Fix Cygwin example compile issues (#2856). [Mark Shaw]
 * Fix select of with index variable (#2880). [Alexander Grobman]
 * Fix cmake version number to be numeric (#2881). [Yuri Victorovich]
+* Fix V3Premit infinite loop on always read-and-write (#2898). [Raynard Qiao]
 
 
 Verilator 4.200 2021-03-12
diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp
index 465bc93b5..97bb3357f 100644
--- a/src/V3Premit.cpp
+++ b/src/V3Premit.cpp
@@ -167,6 +167,7 @@ private:
     }
 
     void createDeepTemp(AstNode* nodep, bool noSubst) {
+        if (nodep->user1()) return;
         if (debug() > 8) nodep->dumpTree(cout, "deepin:");
 
         AstNRelinker linker;
@@ -224,6 +225,7 @@ private:
         {
             bool noopt = PremitAssignVisitor(nodep).noOpt();
             if (noopt && !nodep->user1()) {
+                nodep->user1(true);
                 // Need to do this even if not wide, as e.g. a select may be on a wide operator
                 UINFO(4, "Deep temp for LHS/RHS\n");
                 createDeepTemp(nodep->rhsp(), false);
diff --git a/test_regress/t/t_premit_rw.pl b/test_regress/t/t_premit_rw.pl
new file mode 100755
index 000000000..691e0fb35
--- /dev/null
+++ b/test_regress/t/t_premit_rw.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+#execute(
+#    check_finished => 1,
+#    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_premit_rw.v b/test_regress/t/t_premit_rw.v
new file mode 100644
index 000000000..ba7872a43
--- /dev/null
+++ b/test_regress/t/t_premit_rw.v
@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef struct packed {
+   logic         car_enable;
+   logic [3-1:0] car_rpv;
+   logic [2-1:0] car_sn;
+} car_s;
+
+module t (/*AUTOARG*/
+   // Outputs
+   action,
+   // Inputs
+   rsp
+   );
+   input rsp;
+   output action;
+   car_s  rsp;
+   car_s  action;
+   always @(*) begin
+      action = rsp;
+      if (rsp.car_enable == 1'b1) begin
+         action.car_rpv[ action.car_sn] = 1'b0;    // causing problem
+         // OK
+         //action.car_rpv[ rsp.car_sn] = 1'b0;
+      end
+   end
+endmodule