From dcaf6476e8419433939f7f91f045ae74a2c5965a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 5 Jan 2025 22:52:29 -0500
Subject: [PATCH] Fix matching language extension options including dots.

---
 Changes                            |  1 +
 src/V3Options.cpp                  |  6 ++++--
 test_regress/t/t_langext_1d.py     | 18 ++++++++++++++++++
 test_regress/t/t_langext_1d_bad.py | 18 ++++++++++++++++++
 4 files changed, 41 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_langext_1d.py
 create mode 100755 test_regress/t/t_langext_1d_bad.py

diff --git a/Changes b/Changes
index 8254e2147..7702f91a7 100644
--- a/Changes
+++ b/Changes
@@ -21,6 +21,7 @@ Verilator 5.033 devel
 * Fix pattern assignment to real inside struct (#5713).
 * Fix %p format output for real inside struct (#5713).
 * Fix segfault when only enum value referenced in package (#5714). [Dan Katz]
+* Fix matching language extension options including dots.
 
 
 Verilator 5.032 2025-01-01
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 5e78fd40e..85bba8027 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -99,8 +99,10 @@ public:
     }
     void addLangExt(const string& langext, const V3LangCode& lc) {
         // New language extension replaces any pre-existing one.
-        (void)m_langExts.erase(langext);
-        m_langExts[langext] = lc;
+        string addext = langext;
+        if (addext[0] == '.') addext = addext.substr(1);
+        (void)m_langExts.erase(addext);
+        m_langExts[addext] = lc;
     }
 
     void addLibExtV(const string& libext) {
diff --git a/test_regress/t/t_langext_1d.py b/test_regress/t/t_langext_1d.py
new file mode 100755
index 000000000..6b8d4bc93
--- /dev/null
+++ b/test_regress/t/t_langext_1d.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_langext_1.v"
+
+# This is a compile only test.
+test.compile(v_flags2=["+verilog2001ext+.v"])
+
+test.passes()
diff --git a/test_regress/t/t_langext_1d_bad.py b/test_regress/t/t_langext_1d_bad.py
new file mode 100755
index 000000000..706e9ab40
--- /dev/null
+++ b/test_regress/t/t_langext_1d_bad.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+test.top_filename = "t/t_langext_1.v"
+
+# This is a lint only test.
+test.lint(v_flags2=["+verilog1995ext+.v"], fails=True)
+
+test.passes()