From dbfbc657e16fb7281763e83342a1d280f5ae94d4 Mon Sep 17 00:00:00 2001
From: Igor Zaworski <84542280+igorosky@users.noreply.github.com>
Date: Wed, 9 Jul 2025 23:12:11 +0200
Subject: [PATCH] Fix class extends dotted error (#6162)

---
 src/V3LinkDot.cpp                             |  1 +
 ...m_extends_static_member_function_access.py | 18 +++++++++++++
 ...am_extends_static_member_function_access.v | 26 +++++++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100755 test_regress/t/t_class_param_extends_static_member_function_access.py
 create mode 100644 test_regress/t/t_class_param_extends_static_member_function_access.v

diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 85da123c9..b84b8ba6c 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -4233,6 +4233,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
         if (nodep->classOrNullp()) return;
         LINKDOT_VISIT_START();
         if (m_statep->forPrimary()) {
+            if (nodep->childDTypep()) return;
             AstNode* cprp = nodep->classOrPkgsp();
             VSymEnt* lookSymp = m_curSymp;
             if (AstDot* const dotp = VN_CAST(cprp, Dot)) {
diff --git a/test_regress/t/t_class_param_extends_static_member_function_access.py b/test_regress/t/t_class_param_extends_static_member_function_access.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_class_param_extends_static_member_function_access.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_class_param_extends_static_member_function_access.v b/test_regress/t/t_class_param_extends_static_member_function_access.v
new file mode 100644
index 000000000..09cf19ee2
--- /dev/null
+++ b/test_regress/t/t_class_param_extends_static_member_function_access.v
@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Class1 #(type T);
+  static function int get_p();
+    return 7;
+  endfunction
+endclass
+
+class Class2 #(type T) extends Class1 #(T);
+   static function int get_p2;
+     return T::get_p();
+   endfunction
+endclass
+
+module t;
+  initial begin
+    typedef Class2#(Class1#(int)) Class;
+    if (Class::get_p2() != Class1#(int)::get_p()) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule