From db6ecbd57e2b038d66644fc99479d4036a8872ad Mon Sep 17 00:00:00 2001
From: Todd Strader <todd.strader@gmail.com>
Date: Tue, 18 Feb 2020 17:52:28 -0500
Subject: [PATCH] Test for #2169

---
 test_regress/t/t_prot_lib.v            |  3 ++
 test_regress/t/t_prot_lib_clk_gated.pl | 74 ++++++++++++++++++++++++++
 test_regress/t/t_prot_lib_secret.v     |  7 ++-
 3 files changed, 82 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_prot_lib_clk_gated.pl

diff --git a/test_regress/t/t_prot_lib.v b/test_regress/t/t_prot_lib.v
index d511fe16f..ce80add05 100644
--- a/test_regress/t/t_prot_lib.v
+++ b/test_regress/t/t_prot_lib.v
@@ -55,6 +55,8 @@ module t (/*AUTOARG*/
          logic [3:0] [31:0] s4x32_in;
          logic [3:0] [31:0] s4x32_out;
 
+         wire clk_en = crc[0];
+
          secret
            secret (
                    .accum_in,
@@ -77,6 +79,7 @@ module t (/*AUTOARG*/
                    .s129_out,
                    .s4x32_in,
                    .s4x32_out,
+                   .clk_en,
                    .clk);
 
          always @(posedge clk) begin
diff --git a/test_regress/t/t_prot_lib_clk_gated.pl b/test_regress/t/t_prot_lib_clk_gated.pl
new file mode 100755
index 000000000..9862323a7
--- /dev/null
+++ b/test_regress/t/t_prot_lib_clk_gated.pl
@@ -0,0 +1,74 @@
+#!/usr/bin/perl
+# Makes the test run with tracing enabled by default, can be overridden
+# with --notrace
+unshift(@ARGV, "--trace");
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Todd Strader. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(
+    vlt => 1,
+    xsim => 1,
+    );
+
+$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark};
+
+top_filename("t/t_prot_lib.v");
+my $secret_prefix = "secret";
+my $secret_dir = "$Self->{obj_dir}/$secret_prefix";
+mkdir $secret_dir;
+
+while (1) {
+    # Always compile the secret file with Verilator no matter what simulator
+    #   we are testing with
+    run(logfile => "$secret_dir/vlt_compile.log",
+        cmd => ["perl",
+                "$ENV{VERILATOR_ROOT}/bin/verilator",
+                "--prefix",
+                "Vt_prot_lib_secret",
+                "-cc",
+                "-Mdir",
+                $secret_dir,
+                "-GGATED_CLK=1",
+                "--protect-lib",
+                $secret_prefix,
+                "t/t_prot_lib_secret.v"]);
+    last if $Self->{errors};
+
+    run(logfile => "$secret_dir/secret_gcc.log",
+        cmd=>["make",
+              "-C",
+              $secret_dir,
+              "-f",
+              "Vt_prot_lib_secret.mk"]);
+    last if $Self->{errors};
+
+    compile(
+        verilator_flags2 => ["$secret_dir/secret.sv",
+                             "-LDFLAGS",
+                             "'-L$secret_prefix -lsecret -static'"],
+        xsim_flags2 => ["$secret_dir/secret.sv"],
+        );
+
+    execute(
+        check_finished => 1,
+        xsim_run_flags2 => ["--sv_lib",
+                            "$secret_dir/libsecret",
+                            "--dpi_absolute"],
+        );
+
+    if ($Self->{vlt} && $Self->{trace}) {
+        # We can see the ports of the secret module
+        file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/);
+        # but we can't see what's inside
+        file_grep_not("$Self->{obj_dir}/simx.vcd", qr/secret_/);
+    }
+
+    ok(1);
+    last;
+}
+1;
diff --git a/test_regress/t/t_prot_lib_secret.v b/test_regress/t/t_prot_lib_secret.v
index b55164988..534aca6a1 100644
--- a/test_regress/t/t_prot_lib_secret.v
+++ b/test_regress/t/t_prot_lib_secret.v
@@ -2,7 +2,8 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2019 by Todd Strader.
 
-module secret (
+module secret #(parameter GATED_CLK = 0)
+              (
                input [31:0] 		 accum_in,
                output wire [31:0] 	 accum_out,
                input 			 accum_bypass,
@@ -23,6 +24,7 @@ module secret (
                output logic [128:0] 	 s129_out,
                input [3:0] [31:0] 	 s4x32_in,
                output logic [3:0] [31:0] s4x32_out,
+               input                     clk_en,
                input 			 clk);
 
    logic [31:0] 			 secret_accum_q = 0;
@@ -30,7 +32,8 @@ module secret (
 
    initial $display("created %m");
 
-   always @(posedge clk) begin
+   wire the_clk = GATED_CLK != 0 ? clk & clk_en : clk;
+   always @(posedge the_clk) begin
       secret_accum_q <= secret_accum_q + accum_in + secret_value;
    end