From da4323062d30a9f948b475ee1871be297882bfc1 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 1 Jul 2011 15:23:09 -0400
Subject: [PATCH] Commentary

---
 test_regress/t/t_assert_synth.v   | 2 +-
 test_regress/t/t_case_huge_sub2.v | 2 +-
 test_regress/t/t_clk_gater.v      | 2 +-
 test_regress/t/t_dpi_import.v     | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/test_regress/t/t_assert_synth.v b/test_regress/t/t_assert_synth.v
index a65acf774..8506ca13a 100644
--- a/test_regress/t/t_assert_synth.v
+++ b/test_regress/t/t_assert_synth.v
@@ -47,7 +47,7 @@ module t (/*AUTOARG*/
       endcase
    end
 
-`ifdef NOT_YET_verilator
+`ifdef NOT_YET_VERILATOR // Unsupported
    // ambit synthesis one_hot "a, b_oh"
    // cadence one_cold "a_l, b_oc_l"
 `endif
diff --git a/test_regress/t/t_case_huge_sub2.v b/test_regress/t/t_case_huge_sub2.v
index 2dec19bbb..53e2ab113 100644
--- a/test_regress/t/t_case_huge_sub2.v
+++ b/test_regress/t/t_case_huge_sub2.v
@@ -25,7 +25,7 @@ module t_case_huge_sub2 (/*AUTOARG*/
 
    always @(/*AS*/index) begin
       case (index[7:0])
-`ifdef verilator
+`ifdef VERILATOR // Harder test
 	8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
 `else
 	8'h00: begin outa = 10'h0; end
diff --git a/test_regress/t/t_clk_gater.v b/test_regress/t/t_clk_gater.v
index 0fe44d6fd..4a8bdfe88 100644
--- a/test_regress/t/t_clk_gater.v
+++ b/test_regress/t/t_clk_gater.v
@@ -86,7 +86,7 @@ module Test (/*AUTOARG*/
    end
 
    reg displayit;
-`ifdef verilator
+`ifdef VERILATOR  // Harder test
    initial displayit = $c1("0");  // Something that won't optimize away
 `else
    initial displayit = '0;
diff --git a/test_regress/t/t_dpi_import.v b/test_regress/t/t_dpi_import.v
index 6661a3eb3..4d73d6a04 100644
--- a/test_regress/t/t_dpi_import.v
+++ b/test_regress/t/t_dpi_import.v
@@ -11,7 +11,7 @@
 `ifdef NC
  `define NO_SHORTREAL
 `endif
-`ifdef VERILATOR
+`ifdef VERILATOR  // Unsupported
  `define NO_SHORTREAL
 `endif