diff --git a/src/V3Force.cpp b/src/V3Force.cpp
index ca20d3c61..fef1fce69 100644
--- a/src/V3Force.cpp
+++ b/src/V3Force.cpp
@@ -1400,6 +1400,12 @@ class ForceReplaceVisitor final : public VNVisitor {
             iterateChildren(nodep);
             return;
         }
+        if (m_state.doingAssign() && varInfo->m_forceRdVscp) {
+            baseRefp->varp(varInfo->m_forceRdVscp->varp());
+            baseRefp->varScopep(varInfo->m_forceRdVscp);
+            iterateChildren(nodep);
+            return;
+        }
         const ForceState::ArraySelInfo arrayInfo = ForceState::getArraySelInfo(nodep);
         // Substitute forced reads inside the index expressions before anything is cloned,
         // so the fallback value and the flattened index use the same, force-aware index.
diff --git a/test_regress/t/t_forceable_unpacked_assign.py b/test_regress/t/t_forceable_unpacked_assign.py
new file mode 100755
index 000000000..7ded63f3a
--- /dev/null
+++ b/test_regress/t/t_forceable_unpacked_assign.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_forceable_unpacked_assign.v b/test_regress/t/t_forceable_unpacked_assign.v
new file mode 100644
index 000000000..f0b1b2388
--- /dev/null
+++ b/test_regress/t/t_forceable_unpacked_assign.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Nikolai Kumar
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkh(g,e) do if ((g) !== (e)) begin $write("%%Error: %s:%0d: got=%x exp=%x\n", `__FILE__,`__LINE__, (g),(e)); `stop; end while(0)
+// verilog_format: on
+
+module t;
+  logic var_en [0:1] /*verilator forceable*/;
+  logic sig;
+
+  initial begin
+    var_en[0] = 1'b0;
+    var_en[1] = 1'b0;
+  end
+
+  //verilator lint_off IEEEMAYDEPRECATE
+  initial assign sig = 1'b1;
+  //verilator lint_on IEEEMAYDEPRECATE
+
+  initial begin
+    #1;
+    force var_en[0] = 1'b1;
+    #1;
+    `checkh(var_en[0], 1'b1);
+    `checkh(var_en[1], 1'b0);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule