diff --git a/bin/verilator b/bin/verilator
index 8e4815aaf..03a8cd2a2 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -104,7 +104,7 @@ if ($Opt_Sp) {
 }
 if ($Opt_Sp eq 'sp' || $Opt_Trace) {
     if (!defined $ENV{SYSTEMPERL}) {
-	my $try = "$ENV{W}/hw/utils/perltools/SystemC/src";
+	my $try = "$ENV{W}/hw/utils/perltools/SystemC";
 	$ENV{SYSTEMPERL} = $try if -d $try;
     }
     (defined $ENV{SYSTEMPERL}) or die "%Error: verilator: Need \$SYSTEMPERL in environment for --sp or --trace\nProbably System-Perl isn't installed, see http://www.veripool.com/systemperl.html\n";
diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 629a22ce6..7ba1b4814 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -197,9 +197,11 @@ sub new {
 	# VCS
 	vcs => 0,
 	vcs_flags => [split(/\s+/,"+cli -I +define+vcs+1 -q +v2k")],
+	vcs_flags2 => [],  # Overridden in some sim files
 	# NC
 	nc => 0,
 	nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+nc=1 -q +assert +sv31a")],
+	nc_flags2 => [],  # Overridden in some sim files
 	# Verilator
 	'v3' => 0,
 	verilator_flags => [split(/\s+/,"-cc")],
@@ -291,6 +293,7 @@ sub compile {
 		    fails=>$param{fails},
 		    cmd=>["vcs",
 			  @{$param{vcs_flags}},
+			  @{$param{vcs_flags2}},
 			  @{$param{v_flags}},
 			  @{$param{v_flags2}},
 			  $param{top_filename},
@@ -304,6 +307,7 @@ sub compile {
 		    fails=>$param{fails},
 		    cmd=>["ncverilog",
 			  @{$param{nc_flags}},
+			  @{$param{nc_flags2}},
 			  @{$param{v_flags}},
 			  @{$param{v_flags2}},
 			  $param{top_filename},
diff --git a/test_regress/t/t_case_nest.v b/test_regress/t/t_case_nest.v
index e72d4eb5f..566016889 100644
--- a/test_regress/t/t_case_nest.v
+++ b/test_regress/t/t_case_nest.v
@@ -31,7 +31,7 @@ module t (/*AUTOARG*/
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum != 64'h2e5cb972eb02b8a0) $stop;
+	 if (sum !== 64'h2e5cb972eb02b8a0) $stop;
       end
       else if (cyc==91) begin
       end
diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v
index 93a110709..6dd82d997 100644
--- a/test_regress/t/t_case_wild.v
+++ b/test_regress/t/t_case_wild.v
@@ -30,7 +30,7 @@ module t (/*AUTOARG*/
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum != 64'hf0afc2bfa78277c5) $stop;
+	 if (sum !== 64'hf0afc2bfa78277c5) $stop;
       end
       else if (cyc==91) begin
       end
diff --git a/test_regress/t/t_gen_assign.v b/test_regress/t/t_gen_assign.v
index 435339a2e..ad011d8b2 100644
--- a/test_regress/t/t_gen_assign.v
+++ b/test_regress/t/t_gen_assign.v
@@ -39,7 +39,7 @@ module t (/*AUTOARG*/
 	 sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]};
       end
       else if (cyc==99) begin
-	 if (sum != 32'he8bbd130) $stop;
+	 if (sum !== 32'he8bbd130) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end
diff --git a/test_regress/t/t_gen_forif.pl b/test_regress/t/t_gen_forif.pl
new file mode 100755
index 000000000..e0edd0ab2
--- /dev/null
+++ b/test_regress/t/t_gen_forif.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 nc_flags2 => ['+access+r'],
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_forif.v b/test_regress/t/t_gen_forif.v
new file mode 100644
index 000000000..2f188a698
--- /dev/null
+++ b/test_regress/t/t_gen_forif.v
@@ -0,0 +1,111 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] crc;
+   reg [63:0] sum;
+
+   wire [3:0] Value = crc[3:0];
+
+   wire [3:0] Result;
+   wire [3:0] Result2;
+
+   Testit testit (/*AUTOINST*/
+		  // Outputs
+		  .Result		(Result[3:0]),
+		  .Result2		(Result2[3:0]),
+		  // Inputs
+		  .clk			(clk),
+		  .Value		(Value[3:0]));
+
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= {56'h0, Result, Result2}
+	     ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'h4af37965592f64f9) $stop;
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   reg Internal;
+
+   assign Result = Internal ^ clk;
+  
+   always @(posedge clk)
+     Internal <= #1 Value;
+endmodule
+
+module Test_wrap1 (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   Test t (clk, Value, Result);
+endmodule
+	
+module Test_wrap2 (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   Test t (clk, Value, Result);
+endmodule
+
+module Testit (clk, Value, Result, Result2);
+   input clk;
+   input [3:0] Value;
+   output [3:0] Result;
+   output [3:0] Result2;
+
+   genvar i;
+   generate
+      for (i = 0; i < 4; i = i + 1)
+	begin : a
+	   if ((i == 0) || (i == 2)) begin : gblk
+	     Test_wrap1 test (clk, Value[i] , Result[i]);
+	   end
+	   else begin : gblk
+	     Test_wrap2 test (clk, Value[i], Result[i]);
+	   end
+	end
+   endgenerate
+
+   assign Result2[0] = a[0].gblk.test.t.Internal;
+   assign Result2[1] = a[1].gblk.test.t.Internal;
+   assign Result2[2] = a[2].gblk.test.t.Internal;
+   assign Result2[3] = a[3].gblk.test.t.Internal;
+
+endmodule
diff --git a/test_regress/t/t_math_imm.v b/test_regress/t/t_math_imm.v
index a98ac80e3..9bebcae4f 100644
--- a/test_regress/t/t_math_imm.v
+++ b/test_regress/t/t_math_imm.v
@@ -67,8 +67,8 @@ module t (/*AUTOARG*/
       end
       else if (cyc==99) begin
 	 $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
-	 if (crc != 8'b00111000) $stop;
-	 if (sum != 64'h58743ffa61e41075) $stop;
+	 if (crc !== 8'b00111000) $stop;
+	 if (sum !== 64'h58743ffa61e41075) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end
diff --git a/test_regress/t/t_math_mul.v b/test_regress/t/t_math_mul.v
index 14e33416b..cc35ad092 100644
--- a/test_regress/t/t_math_mul.v
+++ b/test_regress/t/t_math_mul.v
@@ -29,7 +29,7 @@ module t (/*AUTOARG*/
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum != 64'hc1f743ad62c2c04d) $stop;
+	 if (sum !== 64'hc1f743ad62c2c04d) $stop;
       end
       else if (cyc==91) begin
       end
diff --git a/test_regress/t/t_math_vliw.v b/test_regress/t/t_math_vliw.v
index 1df656ec9..2a13f76a8 100644
--- a/test_regress/t/t_math_vliw.v
+++ b/test_regress/t/t_math_vliw.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -47,8 +47,8 @@ module t (/*AUTOARG*/
       end
       else if (cyc==99) begin
 	 $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
-	 if (crc != 8'b01110000) $stop;
-	 if (sum != 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
+	 if (crc !== 8'b01110000) $stop;
+	 if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end
diff --git a/test_regress/t/t_mem_file.v b/test_regress/t/t_mem_file.v
index e1aeb4f9b..05edda729 100644
--- a/test_regress/t/t_mem_file.v
+++ b/test_regress/t/t_mem_file.v
@@ -66,8 +66,8 @@ module t (/*AUTOARG*/
       else if (cyc==99) begin
 	 $write("*-* All Finished *-*\n");
 	 $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
-	 if (crc != 64'hc77bb9b3784ea091) $stop;
-	 if (sum != 64'h5e9ea8c33a97f81e) $stop;
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'h5e9ea8c33a97f81e) $stop;
 	 $finish;
       end
    end
diff --git a/test_regress/t/t_mem_iforder.v b/test_regress/t/t_mem_iforder.v
index b2e16f87f..f8c065382 100644
--- a/test_regress/t/t_mem_iforder.v
+++ b/test_regress/t/t_mem_iforder.v
@@ -48,7 +48,7 @@ module t (/*AUTOARG*/
 	 sum <= {sum[30:0],sum[31]} ^ {out1, out0};
       end
       else if (cyc==99) begin
-	 if (sum != 32'he8bbd130) $stop;
+	 if (sum !== 32'he8bbd130) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end
diff --git a/test_regress/t/t_unopt_combo.v b/test_regress/t/t_unopt_combo.v
index 55d16547e..48e098804 100644
--- a/test_regress/t/t_unopt_combo.v
+++ b/test_regress/t/t_unopt_combo.v
@@ -53,8 +53,8 @@ module t (/*AUTOARG*/
       else if (cyc==99) begin
 	 $write("*-* All Finished *-*\n");
 	 $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
-	 if (crc != 64'hc77bb9b3784ea091) $stop;
-	 if (sum != 64'he281f003f6dd16b2) $stop;
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'he281f003f6dd16b2) $stop;
 	 $finish;
       end
    end