From d9a0e6959745ec69875a5d72db0124500b23b57d Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 28 Feb 2023 01:09:09 -0500
Subject: [PATCH] Commentary, fix copyright

---
 test_regress/t/t_timing_wait_long.pl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test_regress/t/t_timing_wait_long.pl b/test_regress/t/t_timing_wait_long.pl
index 42423c59c..549b8ba35 100755
--- a/test_regress/t/t_timing_wait_long.pl
+++ b/test_regress/t/t_timing_wait_long.pl
@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.