diff --git a/test_regress/t/t_param_avec.pl b/test_regress/t/t_param_avec.pl
new file mode 100755
index 000000000..18bb867d4
--- /dev/null
+++ b/test_regress/t/t_param_avec.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug477");
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_avec.v b/test_regress/t/t_param_avec.v
new file mode 100644
index 000000000..809f43768
--- /dev/null
+++ b/test_regress/t/t_param_avec.v
@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2016 by Wilson Snyder.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   sub #(.IDX(0), .CHK(10)) i0;
+   sub #(.IDX(2), .CHK(12)) i2;
+   sub #(.IDX(7), .CHK(17)) i7;
+   always @ (posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module sub ();
+   function integer get_element;
+      input integer index;
+      input integer array_arg[7:0];
+      get_element = array_arg[index];
+   endfunction
+
+   parameter integer IDX = 5;
+   parameter integer CHK = 5;
+   localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17};
+   localparam element1 = array[IDX];
+   localparam elementf = get_element(IDX, array);
+   initial begin
+      `checkh (element1, CHK);
+      `checkh (elementf, CHK);
+   end
+endmodule