From d66733aeb8772e09c5cb8a3f0de9faf2f76fdf93 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 14 May 2026 17:52:28 -0400
Subject: [PATCH] Fix process comparison compile error with `--public-flat-rw`
 (#7592).

Fixes #7592.
---
 Changes                                  |  1 +
 include/verilated_std.sv                 |  1 +
 src/V3AstNodeOther.h                     |  3 ++-
 src/V3Name.cpp                           | 18 ++++++++++++++----
 test_regress/t/t_process_compare_flat.py | 19 +++++++++++++++++++
 5 files changed, 37 insertions(+), 5 deletions(-)
 create mode 100755 test_regress/t/t_process_compare_flat.py

diff --git a/Changes b/Changes
index 6cb097930..0fb419f78 100644
--- a/Changes
+++ b/Changes
@@ -64,6 +64,7 @@ Verilator 5.049 devel
 * Fix force of unpacked arrays (#7579) (#7580). [Zubin Jain]
 * Fix property argument retaining type of the previous variable (#7582). [Jakub Michalski]
 * Fix NBA to whole arrays (#7583) (#7575). [Geza Lore, Testorrent USA, Inc.]
+* Fix process comparison compile error with `--public-flat-rw` (#7592).
 
 
 Verilator 5.048 2026-04-26
diff --git a/include/verilated_std.sv b/include/verilated_std.sv
index 7dfd98f31..e2862ed7c 100644
--- a/include/verilated_std.sv
+++ b/include/verilated_std.sv
@@ -193,6 +193,7 @@ package std;
     // Two process references are equal if the different classes' containing
     // m_process are equal. Can't yet use <=> as the base class template
     // comparisons doesn't define <=> as they don't yet require --timing and C++20.
+    // V3Name may remove the __PVT__ from this text.
     // verilog_format: off
 `ifdef VERILATOR_TIMING
 `systemc_header_post
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 5e44fbb11..d65aec4a4 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -1677,7 +1677,7 @@ class AstSystemCSection final : public AstNode {
     // containing arbitrary text that is emitted to the C++ output in various
     // locations depending on the sectionType.
     const VSystemCSectionType m_sectionType;  // The section type
-    const std::string m_text;  // The text content
+    std::string m_text;  // The text content
 
 public:
     AstSystemCSection(FileLine* fl, VSystemCSectionType sectionType, const std::string& text)
@@ -1689,6 +1689,7 @@ public:
     ASTGEN_MEMBERS_AstSystemCSection;
     VSystemCSectionType sectionType() const { return m_sectionType; }
     const std::string& text() const { return m_text; }
+    void text(const std::string& value) { m_text = value; }
     void dump(std::ostream&) const override;
     void dumpJson(std::ostream&) const override;
     bool sameNode(const AstNode*) const override { return false; }
diff --git a/src/V3Name.cpp b/src/V3Name.cpp
index 8e763dc32..e38c53912 100644
--- a/src/V3Name.cpp
+++ b/src/V3Name.cpp
@@ -24,6 +24,7 @@
 #include "V3Name.h"
 
 #include "V3LanguageWords.h"
+#include "V3MemberMap.h"
 #include "V3UniqueNames.h"
 
 #include <vector>
@@ -80,10 +81,8 @@ class NameVisitor final : public VNVisitorConst {
     // VISITORS
     void visit(AstNodeModule* nodep) override {
         VL_RESTORER(m_modp);
-        {
-            m_modp = nodep;
-            iterateChildrenConst(nodep);
-        }
+        m_modp = nodep;
+        iterateChildrenConst(nodep);
     }
     // Add __PVT__ to names of local signals
     void visit(AstVar* nodep) override {
@@ -154,6 +153,17 @@ class NameVisitor final : public VNVisitorConst {
             iterateChildrenConst(nodep);
         }
     }
+    void visit(AstSystemCSection* nodep) override {
+        // include/verilated_std.sv assumes that V3Name does renaming of std::process;
+        // if V3Name does not, remove the __PVT__.
+        if (m_modp && m_modp->name() == "std__03a__03aprocess") {
+            VMemberMap memberMap;
+            if (memberMap.findMember(m_modp, "m_process")) {
+                nodep->text(VString::replaceSubstr(nodep->text(), "__PVT__", ""));
+            }
+        }
+        iterateChildrenConst(nodep);
+    }
 
     //--------------------
     void visit(AstNode* nodep) override { iterateChildrenConst(nodep); }
diff --git a/test_regress/t/t_process_compare_flat.py b/test_regress/t/t_process_compare_flat.py
new file mode 100755
index 000000000..15559c749
--- /dev/null
+++ b/test_regress/t/t_process_compare_flat.py
@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_process_compare.v"
+
+test.compile(verilator_flags2=['--binary --public-flat-rw'])
+
+test.execute()
+
+test.passes()