diff --git a/test_regress/t/t_covergroup_cross.out b/test_regress/t/t_covergroup_cross.out
new file mode 100644
index 000000000..3414a344b
--- /dev/null
+++ b/test_regress/t/t_covergroup_cross.out
@@ -0,0 +1,51 @@
+cg2.addr_cmd.addr0_x_read [cross]: 1
+cg2.addr_cmd.addr0_x_write [cross]: 1
+cg2.addr_cmd.addr1_x_read [cross]: 1
+cg2.addr_cmd.addr1_x_write [cross]: 1
+cg2.cp_addr.addr0: 2
+cg2.cp_addr.addr1: 2
+cg2.cp_cmd.read: 2
+cg2.cp_cmd.write: 2
+cg3.addr_cmd_mode.addr0_x_read_x_debug [cross]: 0
+cg3.addr_cmd_mode.addr0_x_read_x_normal [cross]: 1
+cg3.addr_cmd_mode.addr0_x_write_x_debug [cross]: 1
+cg3.addr_cmd_mode.addr0_x_write_x_normal [cross]: 0
+cg3.addr_cmd_mode.addr1_x_read_x_debug [cross]: 0
+cg3.addr_cmd_mode.addr1_x_read_x_normal [cross]: 0
+cg3.addr_cmd_mode.addr1_x_write_x_debug [cross]: 0
+cg3.addr_cmd_mode.addr1_x_write_x_normal [cross]: 1
+cg3.addr_cmd_mode.addr2_x_read_x_debug [cross]: 1
+cg3.addr_cmd_mode.addr2_x_read_x_normal [cross]: 0
+cg3.addr_cmd_mode.addr2_x_write_x_debug [cross]: 0
+cg3.addr_cmd_mode.addr2_x_write_x_normal [cross]: 0
+cg3.cp_addr.addr0: 2
+cg3.cp_addr.addr1: 1
+cg3.cp_addr.addr2: 1
+cg3.cp_cmd.read: 2
+cg3.cp_cmd.write: 2
+cg3.cp_mode.debug: 2
+cg3.cp_mode.normal: 2
+cg4.addr_cmd_mode_parity.addr0_x_read_x_debug_x_even [cross]: 0
+cg4.addr_cmd_mode_parity.addr0_x_read_x_debug_x_odd [cross]: 0
+cg4.addr_cmd_mode_parity.addr0_x_read_x_normal_x_even [cross]: 1
+cg4.addr_cmd_mode_parity.addr0_x_read_x_normal_x_odd [cross]: 0
+cg4.addr_cmd_mode_parity.addr0_x_write_x_debug_x_even [cross]: 1
+cg4.addr_cmd_mode_parity.addr0_x_write_x_debug_x_odd [cross]: 0
+cg4.addr_cmd_mode_parity.addr0_x_write_x_normal_x_even [cross]: 0
+cg4.addr_cmd_mode_parity.addr0_x_write_x_normal_x_odd [cross]: 0
+cg4.addr_cmd_mode_parity.addr1_x_read_x_debug_x_even [cross]: 0
+cg4.addr_cmd_mode_parity.addr1_x_read_x_debug_x_odd [cross]: 1
+cg4.addr_cmd_mode_parity.addr1_x_read_x_normal_x_even [cross]: 0
+cg4.addr_cmd_mode_parity.addr1_x_read_x_normal_x_odd [cross]: 0
+cg4.addr_cmd_mode_parity.addr1_x_write_x_debug_x_even [cross]: 0
+cg4.addr_cmd_mode_parity.addr1_x_write_x_debug_x_odd [cross]: 0
+cg4.addr_cmd_mode_parity.addr1_x_write_x_normal_x_even [cross]: 0
+cg4.addr_cmd_mode_parity.addr1_x_write_x_normal_x_odd [cross]: 1
+cg4.cp_addr.addr0: 2
+cg4.cp_addr.addr1: 2
+cg4.cp_cmd.read: 2
+cg4.cp_cmd.write: 2
+cg4.cp_mode.debug: 2
+cg4.cp_mode.normal: 2
+cg4.cp_parity.even: 2
+cg4.cp_parity.odd: 2
diff --git a/test_regress/t/t_covergroup_trans_3value.py b/test_regress/t/t_covergroup_cross.py
old mode 100755
new mode 100644
similarity index 95%
rename from test_regress/t/t_covergroup_trans_3value.py
rename to test_regress/t/t_covergroup_cross.py
index 10b6f7cd5..ceec4c59e
--- a/test_regress/t/t_covergroup_trans_3value.py
+++ b/test_regress/t/t_covergroup_cross.py
@@ -9,7 +9,7 @@
 
 import vltest_bootstrap
 
-test.scenarios('vlt')
+test.scenarios('vlt_all')
 
 test.compile(verilator_flags2=['--coverage'])
 
diff --git a/test_regress/t/t_covergroup_cross.v b/test_regress/t/t_covergroup_cross.v
new file mode 100644
index 000000000..390eb1258
--- /dev/null
+++ b/test_regress/t/t_covergroup_cross.v
@@ -0,0 +1,94 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+// Test cross coverage: 2-way, 3-way, and 4-way crosses
+
+module t;
+  logic [1:0] addr;
+  logic cmd;
+  logic mode;
+  logic parity;
+
+  // 2-way cross
+  covergroup cg2;
+    cp_addr: coverpoint addr {
+      bins addr0 = {0};
+      bins addr1 = {1};
+    }
+    cp_cmd: coverpoint cmd {
+      bins read  = {0};
+      bins write = {1};
+    }
+    addr_cmd: cross cp_addr, cp_cmd;
+  endgroup
+
+  // 3-way cross
+  covergroup cg3;
+    cp_addr: coverpoint addr {
+      bins addr0 = {0};
+      bins addr1 = {1};
+      bins addr2 = {2};
+    }
+    cp_cmd: coverpoint cmd {
+      bins read  = {0};
+      bins write = {1};
+    }
+    cp_mode: coverpoint mode {
+      bins normal = {0};
+      bins debug  = {1};
+    }
+    addr_cmd_mode: cross cp_addr, cp_cmd, cp_mode;
+  endgroup
+
+  // 4-way cross
+  covergroup cg4;
+    cp_addr: coverpoint addr {
+      bins addr0 = {0};
+      bins addr1 = {1};
+    }
+    cp_cmd: coverpoint cmd {
+      bins read  = {0};
+      bins write = {1};
+    }
+    cp_mode: coverpoint mode {
+      bins normal = {0};
+      bins debug  = {1};
+    }
+    cp_parity: coverpoint parity {
+      bins even = {0};
+      bins odd  = {1};
+    }
+    addr_cmd_mode_parity: cross cp_addr, cp_cmd, cp_mode, cp_parity;
+  endgroup
+
+  cg2 cg2_inst = new;
+  cg3 cg3_inst = new;
+  cg4 cg4_inst = new;
+
+  initial begin
+    // Sample 2-way: hit all 4 combinations
+    addr = 0; cmd = 0; mode = 0; parity = 0; cg2_inst.sample();  // addr0 x read
+    addr = 1; cmd = 1; mode = 0; parity = 0; cg2_inst.sample();  // addr1 x write
+    addr = 0; cmd = 1; mode = 0; parity = 0; cg2_inst.sample();  // addr0 x write
+    addr = 1; cmd = 0; mode = 0; parity = 0; cg2_inst.sample();  // addr1 x read
+
+    // Sample 3-way: hit 4 of 12 combinations
+    addr = 0; cmd = 0; mode = 0; cg3_inst.sample();  // addr0 x read x normal
+    addr = 1; cmd = 1; mode = 0; cg3_inst.sample();  // addr1 x write x normal
+    addr = 2; cmd = 0; mode = 1; cg3_inst.sample();  // addr2 x read x debug
+    addr = 0; cmd = 1; mode = 1; cg3_inst.sample();  // addr0 x write x debug
+
+    // Sample 4-way: hit 4 of 16 combinations
+    addr = 0; cmd = 0; mode = 0; parity = 0; cg4_inst.sample();
+    addr = 1; cmd = 1; mode = 0; parity = 1; cg4_inst.sample();
+    addr = 0; cmd = 1; mode = 1; parity = 0; cg4_inst.sample();
+    addr = 1; cmd = 0; mode = 1; parity = 1; cg4_inst.sample();
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule
diff --git a/test_regress/t/t_covergroup_cross_3way.out b/test_regress/t/t_covergroup_cross_3way.out
deleted file mode 100644
index fa424c7e6..000000000
--- a/test_regress/t/t_covergroup_cross_3way.out
+++ /dev/null
@@ -1,19 +0,0 @@
-cg.addr_cmd_mode.addr0_x_read_x_debug [cross]: 0
-cg.addr_cmd_mode.addr0_x_read_x_normal [cross]: 1
-cg.addr_cmd_mode.addr0_x_write_x_debug [cross]: 1
-cg.addr_cmd_mode.addr0_x_write_x_normal [cross]: 0
-cg.addr_cmd_mode.addr1_x_read_x_debug [cross]: 0
-cg.addr_cmd_mode.addr1_x_read_x_normal [cross]: 0
-cg.addr_cmd_mode.addr1_x_write_x_debug [cross]: 0
-cg.addr_cmd_mode.addr1_x_write_x_normal [cross]: 1
-cg.addr_cmd_mode.addr2_x_read_x_debug [cross]: 1
-cg.addr_cmd_mode.addr2_x_read_x_normal [cross]: 0
-cg.addr_cmd_mode.addr2_x_write_x_debug [cross]: 0
-cg.addr_cmd_mode.addr2_x_write_x_normal [cross]: 0
-cg.cp_addr.addr0: 2
-cg.cp_addr.addr1: 1
-cg.cp_addr.addr2: 1
-cg.cp_cmd.read: 2
-cg.cp_cmd.write: 2
-cg.cp_mode.debug: 2
-cg.cp_mode.normal: 2
diff --git a/test_regress/t/t_covergroup_cross_3way.py b/test_regress/t/t_covergroup_cross_3way.py
deleted file mode 100755
index f8f6ee53a..000000000
--- a/test_regress/t/t_covergroup_cross_3way.py
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2024 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-FileCopyrightText: 2024 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt')
-
-test.compile(verilator_flags2=['--coverage'])
-
-test.execute()
-
-test.covergroup_coverage_report()
-test.files_identical(test.obj_dir + '/covergroup_report.txt', test.golden_filename)
-
-test.passes()
diff --git a/test_regress/t/t_covergroup_cross_3way.v b/test_regress/t/t_covergroup_cross_3way.v
deleted file mode 100644
index 7550966dd..000000000
--- a/test_regress/t/t_covergroup_cross_3way.v
+++ /dev/null
@@ -1,45 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain
-// SPDX-FileCopyrightText: 2026 Matthew Ballance
-// SPDX-License-Identifier: CC0-1.0
-
-// Test 3-way cross coverage
-
-module t;
-  logic [1:0] addr;
-  logic cmd;
-  logic mode;
-
-  // Covergroup with 3-way cross coverage
-  covergroup cg;
-    cp_addr: coverpoint addr {
-      bins addr0 = {0};
-      bins addr1 = {1};
-      bins addr2 = {2};
-    }
-    cp_cmd: coverpoint cmd {
-      bins read = {0};
-      bins write = {1};
-    }
-    cp_mode: coverpoint mode {
-      bins normal = {0};
-      bins debug = {1};
-    }
-    // 3-way cross: addr x cmd x mode = 3 x 2 x 2 = 12 cross bins
-    addr_cmd_mode: cross cp_addr, cp_cmd, cp_mode;
-  endgroup
-
-  cg cg_inst = new;
-
-  initial begin
-    addr = 0; cmd = 0; mode = 0; cg_inst.sample();  // addr0 x read x normal
-    addr = 1; cmd = 1; mode = 0; cg_inst.sample();  // addr1 x write x normal
-    addr = 2; cmd = 0; mode = 1; cg_inst.sample();  // addr2 x read x debug
-    addr = 0; cmd = 1; mode = 1; cg_inst.sample();  // addr0 x write x debug
-
-    $write("*-* All Finished *-*\n");
-    $finish;
-  end
-
-endmodule
diff --git a/test_regress/t/t_covergroup_cross_4way.out b/test_regress/t/t_covergroup_cross_4way.out
deleted file mode 100644
index f376f5437..000000000
--- a/test_regress/t/t_covergroup_cross_4way.out
+++ /dev/null
@@ -1,24 +0,0 @@
-cg.addr_cmd_mode_parity.addr0_x_read_x_debug_x_even [cross]: 0
-cg.addr_cmd_mode_parity.addr0_x_read_x_debug_x_odd [cross]: 0
-cg.addr_cmd_mode_parity.addr0_x_read_x_normal_x_even [cross]: 1
-cg.addr_cmd_mode_parity.addr0_x_read_x_normal_x_odd [cross]: 0
-cg.addr_cmd_mode_parity.addr0_x_write_x_debug_x_even [cross]: 1
-cg.addr_cmd_mode_parity.addr0_x_write_x_debug_x_odd [cross]: 0
-cg.addr_cmd_mode_parity.addr0_x_write_x_normal_x_even [cross]: 0
-cg.addr_cmd_mode_parity.addr0_x_write_x_normal_x_odd [cross]: 0
-cg.addr_cmd_mode_parity.addr1_x_read_x_debug_x_even [cross]: 0
-cg.addr_cmd_mode_parity.addr1_x_read_x_debug_x_odd [cross]: 1
-cg.addr_cmd_mode_parity.addr1_x_read_x_normal_x_even [cross]: 0
-cg.addr_cmd_mode_parity.addr1_x_read_x_normal_x_odd [cross]: 0
-cg.addr_cmd_mode_parity.addr1_x_write_x_debug_x_even [cross]: 0
-cg.addr_cmd_mode_parity.addr1_x_write_x_debug_x_odd [cross]: 0
-cg.addr_cmd_mode_parity.addr1_x_write_x_normal_x_even [cross]: 0
-cg.addr_cmd_mode_parity.addr1_x_write_x_normal_x_odd [cross]: 1
-cg.cp_addr.addr0: 2
-cg.cp_addr.addr1: 2
-cg.cp_cmd.read: 2
-cg.cp_cmd.write: 2
-cg.cp_mode.debug: 2
-cg.cp_mode.normal: 2
-cg.cp_parity.even: 2
-cg.cp_parity.odd: 2
diff --git a/test_regress/t/t_covergroup_cross_4way.py b/test_regress/t/t_covergroup_cross_4way.py
deleted file mode 100755
index f8f6ee53a..000000000
--- a/test_regress/t/t_covergroup_cross_4way.py
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2024 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-FileCopyrightText: 2024 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt')
-
-test.compile(verilator_flags2=['--coverage'])
-
-test.execute()
-
-test.covergroup_coverage_report()
-test.files_identical(test.obj_dir + '/covergroup_report.txt', test.golden_filename)
-
-test.passes()
diff --git a/test_regress/t/t_covergroup_cross_4way.v b/test_regress/t/t_covergroup_cross_4way.v
deleted file mode 100644
index 6535ea135..000000000
--- a/test_regress/t/t_covergroup_cross_4way.v
+++ /dev/null
@@ -1,49 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain
-// SPDX-FileCopyrightText: 2026 Matthew Ballance
-// SPDX-License-Identifier: CC0-1.0
-
-// Test 4-way cross coverage
-
-module t;
-  logic [1:0] addr;
-  logic cmd;
-  logic mode;
-  logic parity;
-
-  // Covergroup with 4-way cross coverage
-  covergroup cg;
-    cp_addr: coverpoint addr {
-      bins addr0 = {0};
-      bins addr1 = {1};
-    }
-    cp_cmd: coverpoint cmd {
-      bins read = {0};
-      bins write = {1};
-    }
-    cp_mode: coverpoint mode {
-      bins normal = {0};
-      bins debug = {1};
-    }
-    cp_parity: coverpoint parity {
-      bins even = {0};
-      bins odd = {1};
-    }
-    // 4-way cross: addr x cmd x mode x parity = 2 x 2 x 2 x 2 = 16 cross bins
-    addr_cmd_mode_parity: cross cp_addr, cp_cmd, cp_mode, cp_parity;
-  endgroup
-
-  cg cg_inst = new;
-
-  initial begin
-    addr = 0; cmd = 0; mode = 0; parity = 0; cg_inst.sample();
-    addr = 1; cmd = 1; mode = 0; parity = 1; cg_inst.sample();
-    addr = 0; cmd = 1; mode = 1; parity = 0; cg_inst.sample();
-    addr = 1; cmd = 0; mode = 1; parity = 1; cg_inst.sample();
-
-    $write("*-* All Finished *-*\n");
-    $finish;
-  end
-
-endmodule
diff --git a/test_regress/t/t_covergroup_cross_inline.out b/test_regress/t/t_covergroup_cross_inline.out
deleted file mode 100644
index 3b930a824..000000000
--- a/test_regress/t/t_covergroup_cross_inline.out
+++ /dev/null
@@ -1,24 +0,0 @@
-cg.cp_a.a0: 9
-cg.cp_a.a1: 4
-cg.cp_a.a2: 4
-cg.cp_a.a3: 4
-cg.cp_b.b0: 21
-cg.cp_b.b1: 0
-cg.cp_b.b2: 0
-cg.cp_b.b3: 0
-cg.cross_ab.a0_x_b0 [cross]: 9
-cg.cross_ab.a0_x_b1 [cross]: 0
-cg.cross_ab.a0_x_b2 [cross]: 0
-cg.cross_ab.a0_x_b3 [cross]: 0
-cg.cross_ab.a1_x_b0 [cross]: 4
-cg.cross_ab.a1_x_b1 [cross]: 0
-cg.cross_ab.a1_x_b2 [cross]: 0
-cg.cross_ab.a1_x_b3 [cross]: 0
-cg.cross_ab.a2_x_b0 [cross]: 4
-cg.cross_ab.a2_x_b1 [cross]: 0
-cg.cross_ab.a2_x_b2 [cross]: 0
-cg.cross_ab.a2_x_b3 [cross]: 0
-cg.cross_ab.a3_x_b0 [cross]: 4
-cg.cross_ab.a3_x_b1 [cross]: 0
-cg.cross_ab.a3_x_b2 [cross]: 0
-cg.cross_ab.a3_x_b3 [cross]: 0
diff --git a/test_regress/t/t_covergroup_cross_inline.py b/test_regress/t/t_covergroup_cross_inline.py
deleted file mode 100755
index 10b6f7cd5..000000000
--- a/test_regress/t/t_covergroup_cross_inline.py
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of either the GNU Lesser General Public License Version 3
-# or the Perl Artistic License Version 2.0.
-# SPDX-FileCopyrightText: 2026 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt')
-
-test.compile(verilator_flags2=['--coverage'])
-
-test.execute()
-
-test.covergroup_coverage_report()
-test.files_identical(test.obj_dir + '/covergroup_report.txt', test.golden_filename)
-
-test.passes()
diff --git a/test_regress/t/t_covergroup_cross_inline.v b/test_regress/t/t_covergroup_cross_inline.v
deleted file mode 100644
index 3db7b9917..000000000
--- a/test_regress/t/t_covergroup_cross_inline.v
+++ /dev/null
@@ -1,56 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2024 by Wilson Snyder.
-// SPDX-FileCopyrightText: 2024 Wilson Snyder
-// SPDX-License-Identifier: CC0-1.0
-
-// Test small cross coverage with inline implementation
-
-module t(/*AUTOARG*/
-  // Inputs
-  clk
-  );
-  input clk;
-
-  int cyc = 0;
-
-  logic [3:0] a;
-  logic [3:0] b;
-
-  covergroup cg @(posedge clk);
-    option.per_instance = 1;
-
-    // 2-way cross: 44 = 16 bins (< 64 threshold, should use inline)
-    cp_a: coverpoint a {
-      bins a0 = {0,1,2,3};
-      bins a1 = {4,5,6,7};
-      bins a2 = {8,9,10,11};
-      bins a3 = {12,13,14,15};
-    }
-
-    cp_b: coverpoint b {
-      bins b0 = {0,1,2,3};
-      bins b1 = {4,5,6,7};
-      bins b2 = {8,9,10,11};
-      bins b3 = {12,13,14,15};
-    }
-
-    cross_ab: cross cp_a, cp_b;
-  endgroup
-
-  cg cg_inst = new;
-
-  always @(posedge clk) begin
-    cyc <= cyc + 1;
-
-    a <= cyc[3:0];
-    b <= cyc[7:4];
-
-    if (cyc == 20) begin
-      $write("*-* All Finished *-*\n");
-      $finish;
-    end
-  end
-
-endmodule
diff --git a/test_regress/t/t_covergroup_cross_simple.out b/test_regress/t/t_covergroup_cross_simple.out
deleted file mode 100644
index 55fc0aae4..000000000
--- a/test_regress/t/t_covergroup_cross_simple.out
+++ /dev/null
@@ -1,8 +0,0 @@
-cg.addr_cmd.addr0_x_read [cross]: 1
-cg.addr_cmd.addr0_x_write [cross]: 1
-cg.addr_cmd.addr1_x_read [cross]: 1
-cg.addr_cmd.addr1_x_write [cross]: 1
-cg.cp_addr.addr0: 2
-cg.cp_addr.addr1: 2
-cg.cp_cmd.read: 2
-cg.cp_cmd.write: 2
diff --git a/test_regress/t/t_covergroup_cross_simple.py b/test_regress/t/t_covergroup_cross_simple.py
deleted file mode 100755
index ce66dd04d..000000000
--- a/test_regress/t/t_covergroup_cross_simple.py
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2024 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-FileCopyrightText: 2024 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt_all')
-
-test.compile(verilator_flags2=['--coverage'])
-
-test.execute()
-
-test.covergroup_coverage_report()
-test.files_identical(test.obj_dir + '/covergroup_report.txt', test.golden_filename)
-
-test.passes()
diff --git a/test_regress/t/t_covergroup_cross_simple.v b/test_regress/t/t_covergroup_cross_simple.v
deleted file mode 100644
index 352efa2a4..000000000
--- a/test_regress/t/t_covergroup_cross_simple.v
+++ /dev/null
@@ -1,37 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain
-// SPDX-FileCopyrightText: 2026 Matthew Ballance
-// SPDX-License-Identifier: CC0-1.0
-
-// Test basic cross coverage with 2-way cross
-
-module t;
-  logic [1:0] addr;
-  logic cmd;
-
-  covergroup cg;
-    cp_addr: coverpoint addr {
-      bins addr0 = {0};
-      bins addr1 = {1};
-    }
-    cp_cmd: coverpoint cmd {
-      bins read  = {0};
-      bins write = {1};
-    }
-    addr_cmd: cross cp_addr, cp_cmd;
-  endgroup
-
-  cg cg_inst = new;
-
-  initial begin
-    addr = 0; cmd = 0; cg_inst.sample();  // addr0 x read
-    addr = 1; cmd = 1; cg_inst.sample();  // addr1 x write
-    addr = 0; cmd = 1; cg_inst.sample();  // addr0 x write
-    addr = 1; cmd = 0; cg_inst.sample();  // addr1 x read
-
-    $write("*-* All Finished *-*\n");
-    $finish;
-  end
-
-endmodule
diff --git a/test_regress/t/t_covergroup_cross_sparse_map.out b/test_regress/t/t_covergroup_cross_sparse_map.out
deleted file mode 100644
index 319b5df8b..000000000
--- a/test_regress/t/t_covergroup_cross_sparse_map.out
+++ /dev/null
@@ -1,93 +0,0 @@
-cg.cp_a.a0: 10
-cg.cp_a.a1: 5
-cg.cp_a.a2: 6
-cg.cp_b.b0: 21
-cg.cp_b.b1: 0
-cg.cp_b.b2: 0
-cg.cp_c.c0: 10
-cg.cp_c.c1: 5
-cg.cp_c.c2: 6
-cg.cp_d.d0: 21
-cg.cp_d.d1: 0
-cg.cp_d.d2: 0
-cg.cross_abcd.a0_x_b0_x_c0_x_d0 [cross]: 10
-cg.cross_abcd.a0_x_b0_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b0_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a0_x_b0_x_c1_x_d0 [cross]: 0
-cg.cross_abcd.a0_x_b0_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b0_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a0_x_b0_x_c2_x_d0 [cross]: 0
-cg.cross_abcd.a0_x_b0_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b0_x_c2_x_d2 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c0_x_d0 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c1_x_d0 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c2_x_d0 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b1_x_c2_x_d2 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c0_x_d0 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c1_x_d0 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c2_x_d0 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a0_x_b2_x_c2_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b0_x_c0_x_d0 [cross]: 0
-cg.cross_abcd.a1_x_b0_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b0_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b0_x_c1_x_d0 [cross]: 5
-cg.cross_abcd.a1_x_b0_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b0_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b0_x_c2_x_d0 [cross]: 0
-cg.cross_abcd.a1_x_b0_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b0_x_c2_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c0_x_d0 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c1_x_d0 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c2_x_d0 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b1_x_c2_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c0_x_d0 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c1_x_d0 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c2_x_d0 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a1_x_b2_x_c2_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b0_x_c0_x_d0 [cross]: 0
-cg.cross_abcd.a2_x_b0_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b0_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b0_x_c1_x_d0 [cross]: 0
-cg.cross_abcd.a2_x_b0_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b0_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b0_x_c2_x_d0 [cross]: 6
-cg.cross_abcd.a2_x_b0_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b0_x_c2_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c0_x_d0 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c1_x_d0 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c2_x_d0 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b1_x_c2_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c0_x_d0 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c0_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c0_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c1_x_d0 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c1_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c1_x_d2 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c2_x_d0 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c2_x_d1 [cross]: 0
-cg.cross_abcd.a2_x_b2_x_c2_x_d2 [cross]: 0
diff --git a/test_regress/t/t_covergroup_cross_sparse_map.py b/test_regress/t/t_covergroup_cross_sparse_map.py
deleted file mode 100755
index f8f6ee53a..000000000
--- a/test_regress/t/t_covergroup_cross_sparse_map.py
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2024 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-FileCopyrightText: 2024 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt')
-
-test.compile(verilator_flags2=['--coverage'])
-
-test.execute()
-
-test.covergroup_coverage_report()
-test.files_identical(test.obj_dir + '/covergroup_report.txt', test.golden_filename)
-
-test.passes()
diff --git a/test_regress/t/t_covergroup_cross_sparse_map.v b/test_regress/t/t_covergroup_cross_sparse_map.v
deleted file mode 100644
index 82ac84c3d..000000000
--- a/test_regress/t/t_covergroup_cross_sparse_map.v
+++ /dev/null
@@ -1,73 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2024 by Wilson Snyder.
-// SPDX-FileCopyrightText: 2024 Wilson Snyder
-// SPDX-License-Identifier: CC0-1.0
-
-// Test large cross coverage with sparse map implementation
-
-module t(/*AUTOARG*/
-  // Inputs
-  clk
-  );
-  input clk;
-
-  int cyc = 0;
-
-  logic [3:0] a;
-  logic [3:0] b;
-  logic [3:0] c;
-  logic [3:0] d;
-
-  covergroup cg @(posedge clk);
-    option.per_instance = 1;
-
-    // Each coverpoint has 3 bins, total cross: 3*3*3*3 = 81 bins
-    // This exceeds threshold of 64, so should use sparse map
-    cp_a: coverpoint a {
-      bins a0 = {0,1,2,3,4};
-      bins a1 = {5,6,7,8,9};
-      bins a2 = {10,11,12,13,14,15};
-    }
-
-    cp_b: coverpoint b {
-      bins b0 = {0,1,2,3,4};
-      bins b1 = {5,6,7,8,9};
-      bins b2 = {10,11,12,13,14,15};
-    }
-
-    cp_c: coverpoint c {
-      bins c0 = {0,1,2,3,4};
-      bins c1 = {5,6,7,8,9};
-      bins c2 = {10,11,12,13,14,15};
-    }
-
-    cp_d: coverpoint d {
-      bins d0 = {0,1,2,3,4};
-      bins d1 = {5,6,7,8,9};
-      bins d2 = {10,11,12,13,14,15};
-    }
-
-    // 4-way cross: 3*3*3*3 = 81 bins (> 64 threshold, uses sparse map)
-    cross_abcd: cross cp_a, cp_b, cp_c, cp_d;
-  endgroup
-
-  cg cg_inst = new;
-
-  always @(posedge clk) begin
-    cyc <= cyc + 1;
-
-    // Generate some cross coverage
-    a <= cyc[3:0];
-    b <= cyc[7:4];
-    c <= cyc[3:0];  // Intentionally correlate some
-    d <= cyc[7:4];
-
-    if (cyc == 20) begin
-      $write("*-* All Finished *-*\n");
-      $finish;
-    end
-  end
-
-endmodule
diff --git a/test_regress/t/t_covergroup_trans.out b/test_regress/t/t_covergroup_trans.out
new file mode 100644
index 000000000..40f75ca02
--- /dev/null
+++ b/test_regress/t/t_covergroup_trans.out
@@ -0,0 +1,6 @@
+cg.cp_array.arr: 3
+cg.cp_trans2.trans1: 1
+cg.cp_trans2.trans2: 1
+cg.cp_trans2.trans3: 1
+cg.cp_trans3.seq_a: 1
+cg.cp_trans3.seq_b: 1
diff --git a/test_regress/t/t_covergroup_trans_ranges.py b/test_regress/t/t_covergroup_trans.py
old mode 100755
new mode 100644
similarity index 95%
rename from test_regress/t/t_covergroup_trans_ranges.py
rename to test_regress/t/t_covergroup_trans.py
index 10b6f7cd5..ceec4c59e
--- a/test_regress/t/t_covergroup_trans_ranges.py
+++ b/test_regress/t/t_covergroup_trans.py
@@ -9,7 +9,7 @@
 
 import vltest_bootstrap
 
-test.scenarios('vlt')
+test.scenarios('vlt_all')
 
 test.compile(verilator_flags2=['--coverage'])
 
diff --git a/test_regress/t/t_covergroup_trans.v b/test_regress/t/t_covergroup_trans.v
new file mode 100644
index 000000000..664c75e24
--- /dev/null
+++ b/test_regress/t/t_covergroup_trans.v
@@ -0,0 +1,44 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+// Test transition bins: simple 2-value, 3-value sequences, and array bins
+
+module t;
+  logic [2:0] state;
+
+  covergroup cg;
+    // Simple 2-value transitions
+    cp_trans2: coverpoint state {
+      bins trans1 = (0 => 1);
+      bins trans2 = (1 => 2);
+      bins trans3 = (2 => 3);
+    }
+    // 3-value sequence transitions
+    cp_trans3: coverpoint state {
+      bins seq_a = (0 => 1 => 2);
+      bins seq_b = (2 => 3 => 4);
+    }
+    // Array bins: creates a separate bin per listed transition
+    cp_array: coverpoint state {
+      bins arr[] = (0 => 1), (1 => 2), (2 => 3);
+    }
+  endgroup
+
+  cg cg_inst = new;
+
+  initial begin
+    // Drive sequence 0->1->2->3->4 which hits all bins
+    state = 0; cg_inst.sample();
+    state = 1; cg_inst.sample();  // 0=>1: trans1, seq_a pos1, arr[0=>1]
+    state = 2; cg_inst.sample();  // 1=>2: trans2, seq_a done, arr[1=>2]
+    state = 3; cg_inst.sample();  // 2=>3: trans3, seq_b pos1, arr[2=>3]
+    state = 4; cg_inst.sample();  // 3=>4: seq_b done
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule
diff --git a/test_regress/t/t_covergroup_trans_3value.out b/test_regress/t/t_covergroup_trans_3value.out
deleted file mode 100644
index 13a295c7a..000000000
--- a/test_regress/t/t_covergroup_trans_3value.out
+++ /dev/null
@@ -1,2 +0,0 @@
-cg.cp_state.trans_3val: 1
-cg.cp_state.trans_3val_2: 1
diff --git a/test_regress/t/t_covergroup_trans_3value.v b/test_regress/t/t_covergroup_trans_3value.v
deleted file mode 100644
index ea0f4d0bf..000000000
--- a/test_regress/t/t_covergroup_trans_3value.v
+++ /dev/null
@@ -1,42 +0,0 @@
-// DESCRIPTION: Verilator: Test transition bins - 3-value sequences
-// Known limitation: multi-value (3+) transition bins generate incomplete case
-// statements; complex transitions are not fully supported.
-// This file ONLY is placed into the Public Domain, for any use, without warranty.
-// SPDX-FileCopyrightText: 2025 Wilson Snyder
-// SPDX-License-Identifier: CC0-1.0
-
-module t;
-  logic [2:0] state;
-
-  covergroup cg;
-    cp_state: coverpoint state {
-      bins trans_3val = (0 => 1 => 2);  // 3-value sequence
-      bins trans_3val_2 = (2 => 3 => 4);  // Another 3-value sequence
-    }
-  endgroup
-
-  cg cg_inst = new;
-
-  initial begin
-    // Test sequence 1: 0 => 1 => 2 (should complete trans_3val)
-    state = 0;
-    cg_inst.sample();
-
-    state = 1;  // 0 => 1 (state machine now at position 1)
-    cg_inst.sample();
-
-    state = 2;  // 1 => 2 (completes trans_3val: 0=>1=>2)
-    cg_inst.sample();
-
-    // Test sequence 2: 2 => 3 => 4 (should complete trans_3val_2)
-    state = 3;  // 2 => 3 (state machine now at position 1 for trans_3val_2)
-    cg_inst.sample();
-
-    state = 4;  // 3 => 4 (completes trans_3val_2: 2=>3=>4)
-    cg_inst.sample();
-
-    $write("*-* All Finished *-*\n");
-    $finish;
-  end
-
-endmodule
diff --git a/test_regress/t/t_covergroup_trans_errors_bad.out b/test_regress/t/t_covergroup_trans_errors_bad.out
new file mode 100644
index 000000000..316978e46
--- /dev/null
+++ b/test_regress/t/t_covergroup_trans_errors_bad.out
@@ -0,0 +1,15 @@
+%Warning-COVERIGN: t/t_covergroup_trans_errors_bad.v:16:26: Unsupported: '[*]' in cover transition
+   16 |       bins t_repeat = (1 [*2]);    
+      |                          ^~
+                   ... For warning description see https://verilator.org/warn/COVERIGN?v=latest
+                   ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.
+%Error: t/t_covergroup_trans_errors_bad.v:15:12: Transition requires at least two values
+                                               : ... note: In instance 't'
+   15 |       bins t_single = (1);         
+      |            ^~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_covergroup_trans_errors_bad.v:16:12: Transition set without items
+                                               : ... note: In instance 't'
+   16 |       bins t_repeat = (1 [*2]);    
+      |            ^~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_covergroup_trans_repeat_unsup_bad.py b/test_regress/t/t_covergroup_trans_errors_bad.py
old mode 100755
new mode 100644
similarity index 100%
rename from test_regress/t/t_covergroup_trans_repeat_unsup_bad.py
rename to test_regress/t/t_covergroup_trans_errors_bad.py
diff --git a/test_regress/t/t_covergroup_trans_single_bad.v b/test_regress/t/t_covergroup_trans_errors_bad.v
similarity index 64%
rename from test_regress/t/t_covergroup_trans_single_bad.v
rename to test_regress/t/t_covergroup_trans_errors_bad.v
index 8a743fdf5..e572aa41e 100644
--- a/test_regress/t/t_covergroup_trans_single_bad.v
+++ b/test_regress/t/t_covergroup_trans_errors_bad.v
@@ -5,14 +5,15 @@
 // SPDX-FileCopyrightText: 2025 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-// Test: transition bin requires at least two values
+// Test: invalid transition bin syntax - single value and unsupported repetition
 
 module t;
   logic [3:0] cp_expr;
 
   covergroup cg;
     cp1: coverpoint cp_expr {
-      bins t1 = (1);
+      bins t_single = (1);        // Error: requires at least two values
+      bins t_repeat = (1 [*2]);   // Error: unsupported repetition operator
     }
   endgroup
 
diff --git a/test_regress/t/t_covergroup_trans_ranges.out b/test_regress/t/t_covergroup_trans_ranges.out
deleted file mode 100644
index b4a9b64c1..000000000
--- a/test_regress/t/t_covergroup_trans_ranges.out
+++ /dev/null
@@ -1 +0,0 @@
-cg.cp_array.trans_array: 3
diff --git a/test_regress/t/t_covergroup_trans_ranges.v b/test_regress/t/t_covergroup_trans_ranges.v
deleted file mode 100644
index 935ed2c4d..000000000
--- a/test_regress/t/t_covergroup_trans_ranges.v
+++ /dev/null
@@ -1,47 +0,0 @@
-// DESCRIPTION: Verilator: Test transition bins - array bins
-// Transition array bins are supported.
-// This file ONLY is placed into the Public Domain, for any use, without warranty.
-// SPDX-FileCopyrightText: 2025 Wilson Snyder
-// SPDX-License-Identifier: CC0-1.0
-
-module t (/*AUTOARG*/
-  // Inputs
-  clk
-  );
-  input clk;
-
-  logic [2:0] state;
-
-  covergroup cg;
-    // Test array bins: creates separate bin for each transition
-    cp_array: coverpoint state {
-      bins trans_array[] = (0 => 1), (1 => 2), (2 => 3);
-    }
-  endgroup
-
-  cg cg_inst = new;
-
-  int cyc = 0;
-
-  always @(posedge clk) begin
-    cyc <= cyc + 1;
-
-    case (cyc)
-      0: state <= 0;
-      1: state <= 1;  // 0 => 1 (hits trans_array[0=>1])
-      2: state <= 2;  // 1 => 2 (hits trans_array[1=>2])
-      3: state <= 3;  // 2 => 3 (hits trans_array[2=>3])
-      4: begin
-        $write("*-* All Finished *-*\n");
-        $finish;
-      end
-    endcase
-
-    cg_inst.sample();
-
-    if (cyc > 10) begin
-      $display("ERROR: Test timed out");
-      $stop;
-    end
-  end
-endmodule
diff --git a/test_regress/t/t_covergroup_trans_repeat_unsup_bad.out b/test_regress/t/t_covergroup_trans_repeat_unsup_bad.out
deleted file mode 100644
index 90d00a753..000000000
--- a/test_regress/t/t_covergroup_trans_repeat_unsup_bad.out
+++ /dev/null
@@ -1,11 +0,0 @@
-%Warning-COVERIGN: t/t_covergroup_trans_repeat_unsup_bad.v:15:20: Unsupported: '[*]' in cover transition
-   15 |       bins t1 = (1 [*2]);
-      |                    ^~
-                   ... For warning description see https://verilator.org/warn/COVERIGN?v=latest
-                   ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.
-%Error: t/t_covergroup_trans_repeat_unsup_bad.v:15:12: Transition set without items
-                                                     : ... note: In instance 't'
-   15 |       bins t1 = (1 [*2]);
-      |            ^~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: Exiting due to
diff --git a/test_regress/t/t_covergroup_trans_repeat_unsup_bad.v b/test_regress/t/t_covergroup_trans_repeat_unsup_bad.v
deleted file mode 100644
index a29b07e16..000000000
--- a/test_regress/t/t_covergroup_trans_repeat_unsup_bad.v
+++ /dev/null
@@ -1,21 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2025 by Wilson Snyder.
-// SPDX-FileCopyrightText: 2025 Wilson Snyder
-// SPDX-License-Identifier: CC0-1.0
-
-// Test: transition bin with unsupported repetition operator causes empty transition set
-
-module t;
-  logic [3:0] cp_expr;
-
-  covergroup cg;
-    cp1: coverpoint cp_expr {
-      bins t1 = (1 [*2]);
-    }
-  endgroup
-
-  cg cg_inst = new;
-  initial $finish;
-endmodule
diff --git a/test_regress/t/t_covergroup_trans_simple.out b/test_regress/t/t_covergroup_trans_simple.out
deleted file mode 100644
index 1d15da204..000000000
--- a/test_regress/t/t_covergroup_trans_simple.out
+++ /dev/null
@@ -1,3 +0,0 @@
-cg.cp_state.trans1: 1
-cg.cp_state.trans2: 1
-cg.cp_state.trans3: 1
diff --git a/test_regress/t/t_covergroup_trans_simple.py b/test_regress/t/t_covergroup_trans_simple.py
deleted file mode 100755
index 10b6f7cd5..000000000
--- a/test_regress/t/t_covergroup_trans_simple.py
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of either the GNU Lesser General Public License Version 3
-# or the Perl Artistic License Version 2.0.
-# SPDX-FileCopyrightText: 2026 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt')
-
-test.compile(verilator_flags2=['--coverage'])
-
-test.execute()
-
-test.covergroup_coverage_report()
-test.files_identical(test.obj_dir + '/covergroup_report.txt', test.golden_filename)
-
-test.passes()
diff --git a/test_regress/t/t_covergroup_trans_simple.v b/test_regress/t/t_covergroup_trans_simple.v
deleted file mode 100644
index a50738a4b..000000000
--- a/test_regress/t/t_covergroup_trans_simple.v
+++ /dev/null
@@ -1,49 +0,0 @@
-// DESCRIPTION: Verilator: Test transition bins - simple two-value transitions
-// This file ONLY is placed into the Public Domain, for any use, without warranty.
-// SPDX-FileCopyrightText: 2025 Wilson Snyder
-// SPDX-License-Identifier: CC0-1.0
-
-module t (/*AUTOARG*/
-  // Inputs
-  clk
-  );
-  input clk;
-
-  logic [2:0] state;
-
-  covergroup cg;
-    cp_state: coverpoint state {
-      bins trans1 = (0 => 1);
-      bins trans2 = (1 => 2);
-      bins trans3 = (2 => 3);
-    }
-  endgroup
-
-  cg cg_inst = new;
-
-  int cyc = 0;
-
-  always @(posedge clk) begin
-    cyc <= cyc + 1;
-
-    case (cyc)
-      0: state <= 0;
-      1: state <= 1;  // 0 => 1 (trans1 should hit)
-      2: state <= 2;  // 1 => 2 (trans2 should hit)
-      3: state <= 3;  // 2 => 3 (trans3 should hit)
-      4: begin
-        $write("*-* All Finished *-*\n");
-        $finish;
-      end
-    endcase
-
-    // Sample the covergroup manually each clock
-    cg_inst.sample();
-
-    // Auto-stop after 10 cycles to prevent infinite loop
-    if (cyc > 10) begin
-      $display("ERROR: Test timed out");
-      $stop;
-    end
-  end
-endmodule
diff --git a/test_regress/t/t_covergroup_trans_single_bad.out b/test_regress/t/t_covergroup_trans_single_bad.out
deleted file mode 100644
index e4ea4b229..000000000
--- a/test_regress/t/t_covergroup_trans_single_bad.out
+++ /dev/null
@@ -1,6 +0,0 @@
-%Error: t/t_covergroup_trans_single_bad.v:15:12: Transition requires at least two values
-                                               : ... note: In instance 't'
-   15 |       bins t1 = (1);
-      |            ^~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: Exiting due to
diff --git a/test_regress/t/t_covergroup_trans_single_bad.py b/test_regress/t/t_covergroup_trans_single_bad.py
deleted file mode 100755
index ef7407f24..000000000
--- a/test_regress/t/t_covergroup_trans_single_bad.py
+++ /dev/null
@@ -1,16 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of either the GNU Lesser General Public License Version 3
-# or the Perl Artistic License Version 2.0.
-# SPDX-FileCopyrightText: 2025 Wilson Snyder
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt')
-
-test.lint(expect_filename=test.golden_filename, fails=True)
-
-test.passes()
diff --git a/test_regress/t/t_vlcov_covergroup.annotate.out b/test_regress/t/t_vlcov_covergroup.annotate.out
new file mode 100644
index 000000000..38ff6dfcb
--- /dev/null
+++ b/test_regress/t/t_vlcov_covergroup.annotate.out
@@ -0,0 +1,96 @@
+//      // verilator_coverage annotation
+        // DESCRIPTION: Verilator: Verilog Test module
+        //
+        // This file ONLY is placed under the Creative Commons Public Domain
+        // SPDX-FileCopyrightText: 2026 Wilson Snyder
+        // SPDX-License-Identifier: CC0-1.0
+        
+        // Test cross coverage: 2-way, 3-way, and 4-way crosses
+        
+        module t;
+%000001   logic [1:0] addr;
+%000000   logic cmd;
+%000001   logic mode;
+%000001   logic parity;
+        
+          // 2-way cross
+%000004   covergroup cg2;
+%000001     cp_addr: coverpoint addr {
+%000002       bins addr0 = {0};
+%000002       bins addr1 = {1};
+            }
+%000001     cp_cmd: coverpoint cmd {
+%000002       bins read  = {0};
+%000002       bins write = {1};
+            }
+%000001     addr_cmd: cross cp_addr, cp_cmd;
+          endgroup
+        
+          // 3-way cross
+%000004   covergroup cg3;
+%000001     cp_addr: coverpoint addr {
+%000002       bins addr0 = {0};
+%000001       bins addr1 = {1};
+%000001       bins addr2 = {2};
+            }
+%000001     cp_cmd: coverpoint cmd {
+%000002       bins read  = {0};
+%000002       bins write = {1};
+            }
+%000001     cp_mode: coverpoint mode {
+%000002       bins normal = {0};
+%000002       bins debug  = {1};
+            }
+%000001     addr_cmd_mode: cross cp_addr, cp_cmd, cp_mode;
+          endgroup
+        
+          // 4-way cross
+%000004   covergroup cg4;
+%000001     cp_addr: coverpoint addr {
+%000002       bins addr0 = {0};
+%000002       bins addr1 = {1};
+            }
+%000001     cp_cmd: coverpoint cmd {
+%000002       bins read  = {0};
+%000002       bins write = {1};
+            }
+%000001     cp_mode: coverpoint mode {
+%000002       bins normal = {0};
+%000002       bins debug  = {1};
+            }
+%000001     cp_parity: coverpoint parity {
+%000002       bins even = {0};
+%000002       bins odd  = {1};
+            }
+%000001     addr_cmd_mode_parity: cross cp_addr, cp_cmd, cp_mode, cp_parity;
+          endgroup
+        
+%000001   cg2 cg2_inst = new;
+%000001   cg3 cg3_inst = new;
+%000001   cg4 cg4_inst = new;
+        
+%000001   initial begin
+            // Sample 2-way: hit all 4 combinations
+%000001     addr = 0; cmd = 0; mode = 0; parity = 0; cg2_inst.sample();  // addr0 x read
+%000001     addr = 1; cmd = 1; mode = 0; parity = 0; cg2_inst.sample();  // addr1 x write
+%000001     addr = 0; cmd = 1; mode = 0; parity = 0; cg2_inst.sample();  // addr0 x write
+%000001     addr = 1; cmd = 0; mode = 0; parity = 0; cg2_inst.sample();  // addr1 x read
+        
+            // Sample 3-way: hit 4 of 12 combinations
+%000001     addr = 0; cmd = 0; mode = 0; cg3_inst.sample();  // addr0 x read x normal
+%000001     addr = 1; cmd = 1; mode = 0; cg3_inst.sample();  // addr1 x write x normal
+%000001     addr = 2; cmd = 0; mode = 1; cg3_inst.sample();  // addr2 x read x debug
+%000001     addr = 0; cmd = 1; mode = 1; cg3_inst.sample();  // addr0 x write x debug
+        
+            // Sample 4-way: hit 4 of 16 combinations
+%000001     addr = 0; cmd = 0; mode = 0; parity = 0; cg4_inst.sample();
+%000001     addr = 1; cmd = 1; mode = 0; parity = 1; cg4_inst.sample();
+%000001     addr = 0; cmd = 1; mode = 1; parity = 0; cg4_inst.sample();
+%000001     addr = 1; cmd = 0; mode = 1; parity = 1; cg4_inst.sample();
+        
+%000001     $write("*-* All Finished *-*\n");
+%000001     $finish;
+          end
+        
+        endmodule
+        
diff --git a/test_regress/t/t_vlcov_covergroup.out b/test_regress/t/t_vlcov_covergroup.out
index e0eae46f8..0ec7fa5b7 100644
--- a/test_regress/t/t_vlcov_covergroup.out
+++ b/test_regress/t/t_vlcov_covergroup.out
@@ -1,10 +1,10 @@
 COVERGROUP COVERAGE REPORT
 ==========================
 
-TOTAL: 8/8 bins covered (100.00%)
+TOTAL: 31/51 bins covered (60.78%)
 
 ------------------------------------------------------------------------------
-Covergroup Type: cg  [t/t_covergroup_cross_simple.v:15]
+Covergroup Type: cg2  [t/t_covergroup_cross.v:18]
   Type Coverage: 8/8 bins (100.00%)
 
   Coverpoint: cp_addr
@@ -28,3 +28,90 @@ Covergroup Type: cg  [t/t_covergroup_cross_simple.v:15]
       COVERED  addr1_x_write  1 hits
 
 ------------------------------------------------------------------------------
+Covergroup Type: cg3  [t/t_covergroup_cross.v:31]
+  Type Coverage: 11/19 bins (57.89%)
+
+  Coverpoint: cp_addr
+    Coverage: 3/3 bins (100.00%)
+    Bins:
+      COVERED  addr0  2 hits
+      COVERED  addr1  1 hits
+      COVERED  addr2  1 hits
+
+  Coverpoint: cp_cmd
+    Coverage: 2/2 bins (100.00%)
+    Bins:
+      COVERED  read   2 hits
+      COVERED  write  2 hits
+
+  Coverpoint: cp_mode
+    Coverage: 2/2 bins (100.00%)
+    Bins:
+      COVERED  normal  2 hits
+      COVERED  debug   2 hits
+
+  Cross: addr_cmd_mode
+    Coverage: 4/12 bins (33.33%)
+    Bins:
+      ZERO     addr0_x_read_x_debug    0 hits
+      COVERED  addr0_x_read_x_normal   1 hits
+      COVERED  addr0_x_write_x_debug   1 hits
+      ZERO     addr0_x_write_x_normal  0 hits
+      ZERO     addr1_x_read_x_debug    0 hits
+      ZERO     addr1_x_read_x_normal   0 hits
+      ZERO     addr1_x_write_x_debug   0 hits
+      COVERED  addr1_x_write_x_normal  1 hits
+      COVERED  addr2_x_read_x_debug    1 hits
+      ZERO     addr2_x_read_x_normal   0 hits
+      ZERO     addr2_x_write_x_debug   0 hits
+      ZERO     addr2_x_write_x_normal  0 hits
+
+------------------------------------------------------------------------------
+Covergroup Type: cg4  [t/t_covergroup_cross.v:49]
+  Type Coverage: 12/24 bins (50.00%)
+
+  Coverpoint: cp_addr
+    Coverage: 2/2 bins (100.00%)
+    Bins:
+      COVERED  addr0  2 hits
+      COVERED  addr1  2 hits
+
+  Coverpoint: cp_cmd
+    Coverage: 2/2 bins (100.00%)
+    Bins:
+      COVERED  read   2 hits
+      COVERED  write  2 hits
+
+  Coverpoint: cp_mode
+    Coverage: 2/2 bins (100.00%)
+    Bins:
+      COVERED  normal  2 hits
+      COVERED  debug   2 hits
+
+  Coverpoint: cp_parity
+    Coverage: 2/2 bins (100.00%)
+    Bins:
+      COVERED  even  2 hits
+      COVERED  odd   2 hits
+
+  Cross: addr_cmd_mode_parity
+    Coverage: 4/16 bins (25.00%)
+    Bins:
+      ZERO     addr0_x_read_x_debug_x_even    0 hits
+      ZERO     addr0_x_read_x_debug_x_odd     0 hits
+      COVERED  addr0_x_read_x_normal_x_even   1 hits
+      ZERO     addr0_x_read_x_normal_x_odd    0 hits
+      COVERED  addr0_x_write_x_debug_x_even   1 hits
+      ZERO     addr0_x_write_x_debug_x_odd    0 hits
+      ZERO     addr0_x_write_x_normal_x_even  0 hits
+      ZERO     addr0_x_write_x_normal_x_odd   0 hits
+      ZERO     addr1_x_read_x_debug_x_even    0 hits
+      COVERED  addr1_x_read_x_debug_x_odd     1 hits
+      ZERO     addr1_x_read_x_normal_x_even   0 hits
+      ZERO     addr1_x_read_x_normal_x_odd    0 hits
+      ZERO     addr1_x_write_x_debug_x_even   0 hits
+      ZERO     addr1_x_write_x_debug_x_odd    0 hits
+      ZERO     addr1_x_write_x_normal_x_even  0 hits
+      COVERED  addr1_x_write_x_normal_x_odd   1 hits
+
+------------------------------------------------------------------------------
diff --git a/test_regress/t/t_vlcov_covergroup.py b/test_regress/t/t_vlcov_covergroup.py
index 1736f22dc..f85debfbe 100755
--- a/test_regress/t/t_vlcov_covergroup.py
+++ b/test_regress/t/t_vlcov_covergroup.py
@@ -12,7 +12,7 @@ import vltest_bootstrap
 
 test.scenarios('vlt')
 
-test.top_filename = "t/t_covergroup_cross_simple.v"
+test.top_filename = "t/t_covergroup_cross.v"
 
 test.compile(verilator_flags2=['--coverage'])
 
@@ -37,7 +37,7 @@ test.run(cmd=[
 ],
          verilator_run=True)
 
-test.files_identical(test.obj_dir + "/annotated/t_covergroup_cross_simple.v",
+test.files_identical(test.obj_dir + "/annotated/t_covergroup_cross.v",
                      "t/" + test.name + ".annotate.out")
 
 test.passes()