diff --git a/Changes b/Changes
index f0d5947e2..f1863246f 100644
--- a/Changes
+++ b/Changes
@@ -28,6 +28,7 @@ Verilator 5.031 devel
 * Add error on `solve before` or soft constraints of `randc` variable.
 * Improve concatenation performance (#5598) (#5599) (#5602). [Geza Lore]
 * Fix dotted reference in delay value (#2410).
+* Fix `function fork...join_none` regression with unknown type (#4449).
 * Fix can't locate scope error in interface task delayed assignment (#5462) (#5568). [Zhou Shen]
 * Fix BLKANDNBLK for for VARXREFs (#5569). [Todd Strader]
 * Fix VPI error instead of fatal for vpi_get_value() on large signals (#5571). [Todd Strader]
diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index 389b5d012..a0eca3cd1 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -354,7 +354,7 @@ public:
              * executing in the wrong path to make verilator-generated code
              * run faster.
              */
-            puts("auto &vlSelfRef = std::ref(*vlSelf).get();\n");
+            puts("auto& vlSelfRef = std::ref(*vlSelf).get();\n");
         }
 
         if (nodep->initsp()) {
diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp
index 0532ba998..13e2f0b88 100644
--- a/src/V3SchedTiming.cpp
+++ b/src/V3SchedTiming.cpp
@@ -422,7 +422,6 @@ void transformForks(AstNetlist* const netlistp) {
         void visit(AstExprStmt* nodep) override { iterateChildren(nodep); }
 
         //--------------------
-        void visit(AstNodeExpr*) override {}  // Accelerate
         void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
     public:
diff --git a/test_regress/t/t_timing_func_join.py b/test_regress/t/t_timing_func_join.py
new file mode 100755
index 000000000..671072f97
--- /dev/null
+++ b/test_regress/t/t_timing_func_join.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_timing_func_join.v b/test_regress/t/t_timing_func_join.v
new file mode 100644
index 000000000..e8b6b6816
--- /dev/null
+++ b/test_regress/t/t_timing_func_join.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+   function int fun(int val);
+      fork
+         $display("abc");
+         $display("def");
+      join_none  // Although join is illegal, join_none legal (IEEE 1800-2023 13.4)
+      return val + 2;
+   endfunction
+
+   task tsk();
+      fork
+         $display("ghi");
+         $display("jkl");
+      join_none
+   endtask
+
+   initial begin
+      $display("$d", fun(2));
+      tsk();
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule